diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info index 4737fc9..c459498 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info @@ -1,35 +1,35 @@ -commit 55f7a2c187139d471143f91dc368bb1497e2eb78 -Merge: 1f3e656f 93e7107d +commit 520e54d7abecebf75310bb901ce702532148d686 +Merge: 4a53640c 056b7c0c Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com> -Date: Wed Nov 4 21:55:37 2020 -0700 +Date: Fri Nov 6 13:25:29 2020 -0700 - Merge pull request #116 from LNIS-Projects/dev + Merge pull request #118 from LNIS-Projects/dev - Extended I/O Support for SoC I/O interface + Remove the restrictions on requiring two outputs for configurable memory circuits -commit 93e7107d800259ad9031c6b5d4572e8a971c6403 +commit 056b7c0c7997d2d12473f2fc4b7915e25ff74820 Author: tangxifan -Date: Wed Nov 4 20:59:34 2020 -0700 +Date: Fri Nov 6 12:22:22 2020 -0700 - [Test] Add new test to CI + [Doc] Update documentation about CCFF circuit model examples -commit bce8233019cec3b7f778befd9457c9c637b05c6c +commit 70734abc35347dbc27113200908858c9a66e9945 Author: tangxifan -Date: Wed Nov 4 20:58:58 2020 -0700 +Date: Fri Nov 6 11:20:13 2020 -0700 - [Arch] Bug fix in caravel arch + [Arch] Remove QN from stdcell arch -commit 6b48ee7f0bd6c86181cdbbb468c4cf8e7af5c4c6 +commit 1a79a556467ae8d9d4d791b94462e168e15635ca Author: tangxifan -Date: Wed Nov 4 20:58:40 2020 -0700 +Date: Fri Nov 6 11:19:19 2020 -0700 - [Test] Add new test for caravel io support + [HDL] Add DFF cell with reset but only 1 output -commit c85edb4738a24c394b5eeefb08586da7bd4ead6a +commit 0a273ffab65b1f503d6e63da59c93644375dc3b1 Author: tangxifan -Date: Wed Nov 4 20:52:47 2020 -0700 +Date: Fri Nov 6 11:16:46 2020 -0700 - [Arch] Bug fix for embedded io arch + [Tool] Bug fix in the tight requirements on CCFF circuit model On branch master Your branch is up to date with 'origin/master'. diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v index d6db793..f1a9d36 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v @@ -19,7 +19,7 @@ `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxbp/sky130_fd_sc_hd__dfxbp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" `include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" // `include "./SRC/sub_module/inv_buf_passgate.v" diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v index 356dd66..3a475bf 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v @@ -400,7 +400,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(clb_sc_out[0])); direct_interc direct_interc_18_ ( - .in(clb_I0[2]), + .in(clb_I0[0]), .out(direct_interc_18_out[0])); direct_interc direct_interc_19_ ( @@ -408,7 +408,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_19_out[0])); direct_interc direct_interc_20_ ( - .in(clb_I0[0]), + .in(clb_I0[2]), .out(direct_interc_20_out[0])); direct_interc direct_interc_21_ ( @@ -428,7 +428,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_24_out[0])); direct_interc direct_interc_25_ ( - .in(clb_I1[2]), + .in(clb_I1[0]), .out(direct_interc_25_out[0])); direct_interc direct_interc_26_ ( @@ -436,7 +436,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_26_out[0])); direct_interc direct_interc_27_ ( - .in(clb_I1[0]), + .in(clb_I1[2]), .out(direct_interc_27_out[0])); direct_interc direct_interc_28_ ( @@ -456,7 +456,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_31_out[0])); direct_interc direct_interc_32_ ( - .in(clb_I2[2]), + .in(clb_I2[0]), .out(direct_interc_32_out[0])); direct_interc direct_interc_33_ ( @@ -464,7 +464,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_33_out[0])); direct_interc direct_interc_34_ ( - .in(clb_I2[0]), + .in(clb_I2[2]), .out(direct_interc_34_out[0])); direct_interc direct_interc_35_ ( @@ -484,7 +484,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_38_out[0])); direct_interc direct_interc_39_ ( - .in(clb_I3[2]), + .in(clb_I3[0]), .out(direct_interc_39_out[0])); direct_interc direct_interc_40_ ( @@ -492,7 +492,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_40_out[0])); direct_interc direct_interc_41_ ( - .in(clb_I3[0]), + .in(clb_I3[2]), .out(direct_interc_41_out[0])); direct_interc direct_interc_42_ ( @@ -512,7 +512,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_45_out[0])); direct_interc direct_interc_46_ ( - .in(clb_I4[2]), + .in(clb_I4[0]), .out(direct_interc_46_out[0])); direct_interc direct_interc_47_ ( @@ -520,7 +520,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_47_out[0])); direct_interc direct_interc_48_ ( - .in(clb_I4[0]), + .in(clb_I4[2]), .out(direct_interc_48_out[0])); direct_interc direct_interc_49_ ( @@ -540,7 +540,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_52_out[0])); direct_interc direct_interc_53_ ( - .in(clb_I5[2]), + .in(clb_I5[0]), .out(direct_interc_53_out[0])); direct_interc direct_interc_54_ ( @@ -548,7 +548,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_54_out[0])); direct_interc direct_interc_55_ ( - .in(clb_I5[0]), + .in(clb_I5[2]), .out(direct_interc_55_out[0])); direct_interc direct_interc_56_ ( @@ -568,7 +568,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_59_out[0])); direct_interc direct_interc_60_ ( - .in(clb_I6[2]), + .in(clb_I6[0]), .out(direct_interc_60_out[0])); direct_interc direct_interc_61_ ( @@ -576,7 +576,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_61_out[0])); direct_interc direct_interc_62_ ( - .in(clb_I6[0]), + .in(clb_I6[2]), .out(direct_interc_62_out[0])); direct_interc direct_interc_63_ ( @@ -596,7 +596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_66_out[0])); direct_interc direct_interc_67_ ( - .in(clb_I7[2]), + .in(clb_I7[0]), .out(direct_interc_67_out[0])); direct_interc direct_interc_68_ ( @@ -604,7 +604,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; .out(direct_interc_68_out[0])); direct_interc direct_interc_69_ ( - .in(clb_I7[0]), + .in(clb_I7[2]), .out(direct_interc_69_out[0])); direct_interc direct_interc_70_ ( diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 047fb7b..6fd6b63 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -75,13 +75,13 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; +wire [0:1] mux_fabric_out_0_undriven_sram_inv; +wire [0:1] mux_fabric_out_1_undriven_sram_inv; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv; wire [0:1] mux_tree_size2_0_sram; -wire [0:1] mux_tree_size2_0_sram_inv; wire [0:1] mux_tree_size2_1_sram; -wire [0:1] mux_tree_size2_1_sram_inv; wire [0:0] mux_tree_size2_2_out; wire [0:1] mux_tree_size2_2_sram; -wire [0:1] mux_tree_size2_2_sram_inv; wire [0:0] mux_tree_size2_mem_0_ccff_tail; wire [0:0] mux_tree_size2_mem_1_ccff_tail; @@ -116,41 +116,38 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail; mux_tree_size2 mux_fabric_out_0 ( .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), .sram(mux_tree_size2_0_sram[0:1]), - .sram_inv(mux_tree_size2_0_sram_inv[0:1]), + .sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]), .out(fabric_out[0])); mux_tree_size2 mux_fabric_out_1 ( .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), .sram(mux_tree_size2_1_sram[0:1]), - .sram_inv(mux_tree_size2_1_sram_inv[0:1]), + .sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]), .out(fabric_out[1])); mux_tree_size2 mux_ff_0_D_0 ( .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_regin[0]}), .sram(mux_tree_size2_2_sram[0:1]), - .sram_inv(mux_tree_size2_2_sram_inv[0:1]), + .sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]), .out(mux_tree_size2_2_out[0])); mux_tree_size2_mem mem_fabric_out_0 ( .prog_clk(prog_clk[0]), .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]), .ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_size2_0_sram[0:1]), - .mem_outb(mux_tree_size2_0_sram_inv[0:1])); + .mem_out(mux_tree_size2_0_sram[0:1])); mux_tree_size2_mem mem_fabric_out_1 ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_size2_1_sram[0:1]), - .mem_outb(mux_tree_size2_1_sram_inv[0:1])); + .mem_out(mux_tree_size2_1_sram[0:1])); mux_tree_size2_mem mem_ff_0_D_0 ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_size2_mem_1_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_size2_2_sram[0:1]), - .mem_outb(mux_tree_size2_2_sram_inv[0:1])); + .mem_out(mux_tree_size2_2_sram[0:1])); direct_interc direct_interc_0_ ( .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v index 83abac9..fc0f064 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -43,8 +43,8 @@ wire [0:0] direct_interc_4_out; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv; wire [0:1] mux_tree_size2_0_sram; -wire [0:1] mux_tree_size2_0_sram_inv; // // @@ -62,15 +62,14 @@ wire [0:1] mux_tree_size2_0_sram_inv; mux_tree_size2 mux_frac_logic_out_0 ( .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), .sram(mux_tree_size2_0_sram[0:1]), - .sram_inv(mux_tree_size2_0_sram_inv[0:1]), + .sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]), .out(frac_logic_out[0])); mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk(prog_clk[0]), .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_size2_0_sram[0:1]), - .mem_outb(mux_tree_size2_0_sram_inv[0:1])); + .mem_out(mux_tree_size2_0_sram[0:1])); direct_interc direct_interc_0_ ( .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v index d27a5da..ba910ab 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -39,10 +39,10 @@ wire [0:0] frac_lut4_lut4_out; // +wire [0:0] frac_lut4_0__undriven_mode_inv; +wire [0:15] frac_lut4_0__undriven_sram_inv; wire [0:0] frac_lut4_0_mode; -wire [0:0] frac_lut4_0_mode_inv; wire [0:15] frac_lut4_0_sram; -wire [0:15] frac_lut4_0_sram_inv; // // @@ -52,18 +52,17 @@ wire [0:15] frac_lut4_0_sram_inv; frac_lut4 frac_lut4_0_ ( .in(frac_lut4_in[0:3]), .sram(frac_lut4_0_sram[0:15]), - .sram_inv(frac_lut4_0_sram_inv[0:15]), + .sram_inv(frac_lut4_0__undriven_sram_inv[0:15]), .mode(frac_lut4_0_mode[0]), - .mode_inv(frac_lut4_0_mode_inv[0]), + .mode_inv(frac_lut4_0__undriven_mode_inv[0]), .lut3_out(frac_lut4_lut3_out[0:1]), .lut4_out(frac_lut4_lut4_out[0])); - frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), - .mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]}), - .mem_outb({frac_lut4_0_sram_inv[0:15], frac_lut4_0_mode_inv[0]})); + .mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]})); endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v index 0d0c7f5..2a2d521 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v @@ -45,7 +45,6 @@ wire [0:0] iopad_inpad; wire [0:0] EMBEDDED_IO_0_en; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; // // @@ -60,12 +59,11 @@ wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb; .FPGA_DIR(EMBEDDED_IO_0_en[0]), .FPGA_IN(iopad_inpad[0])); - EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail[0]), - .mem_out(EMBEDDED_IO_0_en[0]), - .mem_outb(EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb[0])); + .mem_out(EMBEDDED_IO_0_en[0])); endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v index 05101ad..be730ed 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v @@ -41,18 +41,18 @@ module cbx_1__0_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:3] mux_top_ipin_0_undriven_sram_inv; + wire [0:3] mux_top_ipin_1_undriven_sram_inv; + wire [0:3] mux_top_ipin_2_undriven_sram_inv; + wire [0:3] mux_top_ipin_3_undriven_sram_inv; + wire [0:3] mux_top_ipin_4_undriven_sram_inv; + wire [0:3] mux_top_ipin_5_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; @@ -118,7 +118,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), .out(bottom_grid_pin_0_[0]) ); @@ -128,7 +128,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), .out(bottom_grid_pin_2_[0]) ); @@ -138,7 +138,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), .out(bottom_grid_pin_4_[0]) ); @@ -148,7 +148,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), .out(bottom_grid_pin_6_[0]) ); @@ -158,7 +158,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), .out(bottom_grid_pin_8_[0]) ); @@ -168,7 +168,7 @@ module cbx_1__0_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), .out(bottom_grid_pin_10_[0]) ); @@ -179,8 +179,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -190,8 +189,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -201,8 +199,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -212,8 +209,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -223,8 +219,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -234,8 +229,7 @@ module cbx_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -261,7 +255,7 @@ module cbx_1__0_ .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), .io_outpad(top_width_0_height_0__pin_2_[0]), - .ccff_head(ccff_tail_mid), + .ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]), .io_inpad(top_width_0_height_0__pin_3_upper[0]), .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]) ); @@ -275,7 +269,7 @@ module cbx_1__0_ .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), .io_outpad(top_width_0_height_0__pin_4_[0]), - .ccff_head(ccff_tail_mid), + .ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]), .io_inpad(top_width_0_height_0__pin_5_upper[0]), .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]) ); @@ -289,7 +283,7 @@ module cbx_1__0_ .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), .io_outpad(top_width_0_height_0__pin_6_[0]), - .ccff_head(ccff_tail_mid), + .ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]), .io_inpad(top_width_0_height_0__pin_7_upper[0]), .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]) ); @@ -303,7 +297,7 @@ module cbx_1__0_ .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), .io_outpad(top_width_0_height_0__pin_8_[0]), - .ccff_head(ccff_tail_mid), + .ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]), .io_inpad(top_width_0_height_0__pin_9_upper[0]), .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]) ); @@ -317,7 +311,7 @@ module cbx_1__0_ .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), .io_outpad(top_width_0_height_0__pin_10_[0]), - .ccff_head(ccff_tail_mid), + .ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]), .io_inpad(top_width_0_height_0__pin_11_upper[0]), .ccff_tail(ccff_tail[0]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v index 59817c2..31c9a6e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v @@ -30,22 +30,30 @@ module cbx_1__1_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:3] mux_top_ipin_0_undriven_sram_inv; + wire [0:3] mux_top_ipin_10_undriven_sram_inv; + wire [0:3] mux_top_ipin_11_undriven_sram_inv; + wire [0:3] mux_top_ipin_12_undriven_sram_inv; + wire [0:3] mux_top_ipin_13_undriven_sram_inv; + wire [0:3] mux_top_ipin_14_undriven_sram_inv; + wire [0:3] mux_top_ipin_15_undriven_sram_inv; + wire [0:3] mux_top_ipin_1_undriven_sram_inv; + wire [0:3] mux_top_ipin_2_undriven_sram_inv; + wire [0:3] mux_top_ipin_3_undriven_sram_inv; + wire [0:3] mux_top_ipin_4_undriven_sram_inv; + wire [0:3] mux_top_ipin_5_undriven_sram_inv; + wire [0:3] mux_top_ipin_6_undriven_sram_inv; + wire [0:3] mux_top_ipin_7_undriven_sram_inv; + wire [0:3] mux_top_ipin_8_undriven_sram_inv; + wire [0:3] mux_top_ipin_9_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; @@ -54,21 +62,13 @@ module cbx_1__1_ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; @@ -125,7 +125,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), .out(bottom_grid_pin_0_[0]) ); @@ -135,7 +135,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), .out(bottom_grid_pin_3_[0]) ); @@ -145,7 +145,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), .out(bottom_grid_pin_4_[0]) ); @@ -155,7 +155,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), .out(bottom_grid_pin_7_[0]) ); @@ -165,7 +165,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), .out(bottom_grid_pin_8_[0]) ); @@ -175,7 +175,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), .out(bottom_grid_pin_11_[0]) ); @@ -185,7 +185,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), .out(bottom_grid_pin_12_[0]) ); @@ -195,7 +195,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), .out(bottom_grid_pin_15_[0]) ); @@ -206,8 +206,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -217,8 +216,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -228,8 +226,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -239,8 +236,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -250,8 +246,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -261,8 +256,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -272,8 +266,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) ); @@ -283,8 +276,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) ); @@ -293,7 +285,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), .out(bottom_grid_pin_1_[0]) ); @@ -303,7 +295,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), .out(bottom_grid_pin_2_[0]) ); @@ -313,7 +305,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), .out(bottom_grid_pin_5_[0]) ); @@ -323,7 +315,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), .out(bottom_grid_pin_6_[0]) ); @@ -333,7 +325,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), .out(bottom_grid_pin_9_[0]) ); @@ -343,7 +335,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), .out(bottom_grid_pin_10_[0]) ); @@ -353,7 +345,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), .out(bottom_grid_pin_13_[0]) ); @@ -363,7 +355,7 @@ module cbx_1__1_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), .out(bottom_grid_pin_14_[0]) ); @@ -374,8 +366,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -385,8 +376,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -396,8 +386,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -407,8 +396,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) ); @@ -418,8 +406,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) ); @@ -429,8 +416,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) ); @@ -440,8 +426,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) ); @@ -451,8 +436,7 @@ module cbx_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v index 569a3a3..959cf8c 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v @@ -37,24 +37,32 @@ module cbx_1__2_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:3] mux_bottom_ipin_0_undriven_sram_inv; + wire [0:3] mux_top_ipin_0_undriven_sram_inv; + wire [0:3] mux_top_ipin_10_undriven_sram_inv; + wire [0:3] mux_top_ipin_11_undriven_sram_inv; + wire [0:3] mux_top_ipin_12_undriven_sram_inv; + wire [0:3] mux_top_ipin_13_undriven_sram_inv; + wire [0:3] mux_top_ipin_14_undriven_sram_inv; + wire [0:3] mux_top_ipin_15_undriven_sram_inv; + wire [0:3] mux_top_ipin_1_undriven_sram_inv; + wire [0:3] mux_top_ipin_2_undriven_sram_inv; + wire [0:3] mux_top_ipin_3_undriven_sram_inv; + wire [0:3] mux_top_ipin_4_undriven_sram_inv; + wire [0:3] mux_top_ipin_5_undriven_sram_inv; + wire [0:3] mux_top_ipin_6_undriven_sram_inv; + wire [0:3] mux_top_ipin_7_undriven_sram_inv; + wire [0:3] mux_top_ipin_8_undriven_sram_inv; + wire [0:3] mux_top_ipin_9_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; @@ -64,21 +72,13 @@ module cbx_1__2_ wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; @@ -137,7 +137,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]), .out(top_grid_pin_0_[0]) ); @@ -147,7 +147,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), .out(bottom_grid_pin_0_[0]) ); @@ -157,7 +157,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), .out(bottom_grid_pin_3_[0]) ); @@ -167,7 +167,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), .out(bottom_grid_pin_4_[0]) ); @@ -177,7 +177,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), .out(bottom_grid_pin_7_[0]) ); @@ -187,7 +187,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), .out(bottom_grid_pin_8_[0]) ); @@ -197,7 +197,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), .out(bottom_grid_pin_11_[0]) ); @@ -207,7 +207,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }), .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), .out(bottom_grid_pin_12_[0]) ); @@ -217,7 +217,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), .out(bottom_grid_pin_15_[0]) ); @@ -228,8 +228,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -239,8 +238,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -250,8 +248,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -261,8 +258,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -272,8 +268,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -283,8 +278,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -294,8 +288,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) ); @@ -305,8 +298,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) ); @@ -316,8 +308,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) ); @@ -326,7 +317,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), .out(bottom_grid_pin_1_[0]) ); @@ -336,7 +327,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), .out(bottom_grid_pin_2_[0]) ); @@ -346,7 +337,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), .out(bottom_grid_pin_5_[0]) ); @@ -356,7 +347,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), .out(bottom_grid_pin_6_[0]) ); @@ -366,7 +357,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), .out(bottom_grid_pin_9_[0]) ); @@ -376,7 +367,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), .out(bottom_grid_pin_10_[0]) ); @@ -386,7 +377,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), .out(bottom_grid_pin_13_[0]) ); @@ -396,7 +387,7 @@ module cbx_1__2_ ( .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), .out(bottom_grid_pin_14_[0]) ); @@ -407,8 +398,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -418,8 +408,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -429,8 +418,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -440,8 +428,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) ); @@ -451,8 +438,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) ); @@ -462,8 +448,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) ); @@ -473,8 +458,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) ); @@ -484,8 +468,7 @@ module cbx_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v index 0b8a313..914fb20 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v @@ -17,8 +17,8 @@ module cby_0__1_ output [0:0] right_width_0_height_0__pin_1_upper; output [0:0] right_width_0_height_0__pin_1_lower; + wire [0:3] mux_right_ipin_0_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire ccff_tail_mid; assign chany_top_out[0] = chany_bottom_in[0]; assign chany_top_out[1] = chany_bottom_in[1]; @@ -67,7 +67,7 @@ module cby_0__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), .out(left_grid_pin_0_[0]) ); @@ -78,8 +78,7 @@ module cby_0__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v index a9e4085..8f85e08 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v @@ -26,22 +26,30 @@ module cby_1__1_ output [0:0] left_grid_pin_31_; output [0:0] ccff_tail; + wire [0:3] mux_right_ipin_0_undriven_sram_inv; + wire [0:3] mux_right_ipin_10_undriven_sram_inv; + wire [0:3] mux_right_ipin_11_undriven_sram_inv; + wire [0:3] mux_right_ipin_12_undriven_sram_inv; + wire [0:3] mux_right_ipin_13_undriven_sram_inv; + wire [0:3] mux_right_ipin_14_undriven_sram_inv; + wire [0:3] mux_right_ipin_15_undriven_sram_inv; + wire [0:3] mux_right_ipin_1_undriven_sram_inv; + wire [0:3] mux_right_ipin_2_undriven_sram_inv; + wire [0:3] mux_right_ipin_3_undriven_sram_inv; + wire [0:3] mux_right_ipin_4_undriven_sram_inv; + wire [0:3] mux_right_ipin_5_undriven_sram_inv; + wire [0:3] mux_right_ipin_6_undriven_sram_inv; + wire [0:3] mux_right_ipin_7_undriven_sram_inv; + wire [0:3] mux_right_ipin_8_undriven_sram_inv; + wire [0:3] mux_right_ipin_9_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; @@ -50,21 +58,13 @@ module cby_1__1_ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; @@ -119,7 +119,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), .out(left_grid_pin_16_[0]) ); @@ -129,7 +129,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), .out(left_grid_pin_19_[0]) ); @@ -139,7 +139,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), .out(left_grid_pin_20_[0]) ); @@ -149,7 +149,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), .out(left_grid_pin_23_[0]) ); @@ -159,7 +159,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), .out(left_grid_pin_24_[0]) ); @@ -169,7 +169,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), .out(left_grid_pin_27_[0]) ); @@ -179,7 +179,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), .out(left_grid_pin_28_[0]) ); @@ -189,7 +189,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }), .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), .out(left_grid_pin_31_[0]) ); @@ -200,8 +200,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -211,8 +210,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -222,8 +220,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -233,8 +230,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -244,8 +240,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -255,8 +250,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -266,8 +260,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) ); @@ -277,8 +270,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) ); @@ -287,7 +279,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), .out(left_grid_pin_17_[0]) ); @@ -297,7 +289,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), .out(left_grid_pin_18_[0]) ); @@ -307,7 +299,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), .out(left_grid_pin_21_[0]) ); @@ -317,7 +309,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), .out(left_grid_pin_22_[0]) ); @@ -327,7 +319,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), .out(left_grid_pin_25_[0]) ); @@ -337,7 +329,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), .out(left_grid_pin_26_[0]) ); @@ -347,7 +339,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), .out(left_grid_pin_29_[0]) ); @@ -357,7 +349,7 @@ module cby_1__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), .out(left_grid_pin_30_[0]) ); @@ -368,8 +360,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -379,8 +370,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -390,8 +380,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -401,8 +390,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) ); @@ -412,8 +400,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) ); @@ -423,8 +410,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) ); @@ -434,8 +420,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) ); @@ -445,8 +430,7 @@ module cby_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v index 5dcc50c..594a219 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v @@ -33,24 +33,32 @@ module cby_2__1_ output [0:0] left_width_0_height_0__pin_1_upper; output [0:0] left_width_0_height_0__pin_1_lower; + wire [0:3] mux_left_ipin_0_undriven_sram_inv; + wire [0:3] mux_right_ipin_0_undriven_sram_inv; + wire [0:3] mux_right_ipin_10_undriven_sram_inv; + wire [0:3] mux_right_ipin_11_undriven_sram_inv; + wire [0:3] mux_right_ipin_12_undriven_sram_inv; + wire [0:3] mux_right_ipin_13_undriven_sram_inv; + wire [0:3] mux_right_ipin_14_undriven_sram_inv; + wire [0:3] mux_right_ipin_15_undriven_sram_inv; + wire [0:3] mux_right_ipin_1_undriven_sram_inv; + wire [0:3] mux_right_ipin_2_undriven_sram_inv; + wire [0:3] mux_right_ipin_3_undriven_sram_inv; + wire [0:3] mux_right_ipin_4_undriven_sram_inv; + wire [0:3] mux_right_ipin_5_undriven_sram_inv; + wire [0:3] mux_right_ipin_6_undriven_sram_inv; + wire [0:3] mux_right_ipin_7_undriven_sram_inv; + wire [0:3] mux_right_ipin_8_undriven_sram_inv; + wire [0:3] mux_right_ipin_9_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; @@ -60,21 +68,13 @@ module cby_2__1_ wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram_inv; wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram_inv; wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram_inv; wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram_inv; wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; @@ -131,7 +131,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]), .out(right_grid_pin_0_[0]) ); @@ -141,7 +141,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), .out(left_grid_pin_16_[0]) ); @@ -151,7 +151,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), .out(left_grid_pin_19_[0]) ); @@ -161,7 +161,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), .out(left_grid_pin_20_[0]) ); @@ -171,7 +171,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), .out(left_grid_pin_23_[0]) ); @@ -181,7 +181,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), .out(left_grid_pin_24_[0]) ); @@ -191,7 +191,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), .out(left_grid_pin_27_[0]) ); @@ -201,7 +201,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }), .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), .out(left_grid_pin_28_[0]) ); @@ -211,7 +211,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), .out(left_grid_pin_31_[0]) ); @@ -222,8 +222,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -233,8 +232,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -244,8 +242,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -255,8 +252,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -266,8 +262,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -277,8 +272,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -288,8 +282,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) ); @@ -299,8 +292,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) ); @@ -310,8 +302,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) ); @@ -320,7 +311,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), .out(left_grid_pin_17_[0]) ); @@ -330,7 +321,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), .out(left_grid_pin_18_[0]) ); @@ -340,7 +331,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), .out(left_grid_pin_21_[0]) ); @@ -350,7 +341,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_3_sram_inv[0:3]), + .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), .out(left_grid_pin_22_[0]) ); @@ -360,7 +351,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_4_sram_inv[0:3]), + .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), .out(left_grid_pin_25_[0]) ); @@ -370,7 +361,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_5_sram_inv[0:3]), + .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), .out(left_grid_pin_26_[0]) ); @@ -380,7 +371,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_6_sram_inv[0:3]), + .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), .out(left_grid_pin_29_[0]) ); @@ -390,7 +381,7 @@ module cby_2__1_ ( .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_7_sram_inv[0:3]), + .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), .out(left_grid_pin_30_[0]) ); @@ -401,8 +392,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -412,8 +402,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -423,8 +412,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -434,8 +422,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) ); @@ -445,8 +432,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) ); @@ -456,8 +442,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) ); @@ -467,8 +452,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) ); @@ -478,8 +462,7 @@ module cby_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v index 48f09c7..6932ebf 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v @@ -17,38 +17,42 @@ module sb_0__0_ output [0:19] chanx_right_out; output [0:0] ccff_tail; + wire [0:2] mux_right_track_0_undriven_sram_inv; + wire [0:1] mux_right_track_10_undriven_sram_inv; + wire [0:1] mux_right_track_12_undriven_sram_inv; + wire [0:1] mux_right_track_14_undriven_sram_inv; + wire [0:1] mux_right_track_16_undriven_sram_inv; + wire [0:1] mux_right_track_18_undriven_sram_inv; + wire [0:1] mux_right_track_24_undriven_sram_inv; + wire [0:1] mux_right_track_26_undriven_sram_inv; + wire [0:1] mux_right_track_28_undriven_sram_inv; + wire [0:2] mux_right_track_2_undriven_sram_inv; + wire [0:1] mux_right_track_30_undriven_sram_inv; + wire [0:1] mux_right_track_32_undriven_sram_inv; + wire [0:1] mux_right_track_34_undriven_sram_inv; + wire [0:2] mux_right_track_4_undriven_sram_inv; + wire [0:2] mux_right_track_6_undriven_sram_inv; + wire [0:1] mux_right_track_8_undriven_sram_inv; + wire [0:1] mux_top_track_0_undriven_sram_inv; + wire [0:1] mux_top_track_24_undriven_sram_inv; + wire [0:1] mux_top_track_4_undriven_sram_inv; + wire [0:1] mux_top_track_8_undriven_sram_inv; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; @@ -65,13 +69,9 @@ module sb_0__0_ wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; @@ -102,7 +102,7 @@ module sb_0__0_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[1] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:1]), .out(chany_top_out[0]) ); @@ -112,7 +112,7 @@ module sb_0__0_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[3] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:1]), .out(chany_top_out[2]) ); @@ -122,7 +122,7 @@ module sb_0__0_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[5] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), .out(chany_top_out[4]) ); @@ -132,7 +132,7 @@ module sb_0__0_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[13] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), .out(chany_top_out[12]) ); @@ -142,7 +142,7 @@ module sb_0__0_ ( .in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), .out(chanx_right_out[4]) ); @@ -152,7 +152,7 @@ module sb_0__0_ ( .in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), .out(chanx_right_out[5]) ); @@ -162,7 +162,7 @@ module sb_0__0_ ( .in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }), .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), .out(chanx_right_out[6]) ); @@ -172,7 +172,7 @@ module sb_0__0_ ( .in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }), .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), .out(chanx_right_out[7]) ); @@ -182,7 +182,7 @@ module sb_0__0_ ( .in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), .out(chanx_right_out[8]) ); @@ -192,7 +192,7 @@ module sb_0__0_ ( .in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), .out(chanx_right_out[9]) ); @@ -202,7 +202,7 @@ module sb_0__0_ ( .in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), .out(chanx_right_out[12]) ); @@ -212,7 +212,7 @@ module sb_0__0_ ( .in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }), .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), .out(chanx_right_out[13]) ); @@ -222,7 +222,7 @@ module sb_0__0_ ( .in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }), .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), .out(chanx_right_out[14]) ); @@ -232,7 +232,7 @@ module sb_0__0_ ( .in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }), .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), .out(chanx_right_out[15]) ); @@ -242,7 +242,7 @@ module sb_0__0_ ( .in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), .out(chanx_right_out[16]) ); @@ -252,7 +252,7 @@ module sb_0__0_ ( .in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), .out(chanx_right_out[17]) ); @@ -263,8 +263,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -274,8 +273,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -285,8 +283,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -296,8 +293,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -307,8 +303,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -318,8 +313,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); @@ -329,8 +323,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) ); @@ -340,8 +333,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) ); @@ -351,8 +343,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) ); @@ -362,8 +353,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) ); @@ -373,8 +363,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) ); @@ -384,8 +373,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) ); @@ -395,8 +383,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) ); @@ -406,8 +393,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) ); @@ -417,8 +403,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) ); @@ -428,8 +413,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) ); @@ -438,7 +422,7 @@ module sb_0__0_ ( .in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), .out(chanx_right_out[0]) ); @@ -448,7 +432,7 @@ module sb_0__0_ ( .in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), .out(chanx_right_out[1]) ); @@ -458,7 +442,7 @@ module sb_0__0_ ( .in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), .out(chanx_right_out[2]) ); @@ -468,7 +452,7 @@ module sb_0__0_ ( .in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), .out(chanx_right_out[3]) ); @@ -479,8 +463,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -490,8 +473,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -501,8 +483,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) ); @@ -512,8 +493,7 @@ module sb_0__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v index 045ce88..6caa8b1 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v @@ -22,18 +22,45 @@ module sb_0__1_ output [0:19] chany_bottom_out; output [0:0] ccff_tail; + wire [0:2] mux_bottom_track_17_undriven_sram_inv; + wire [0:2] mux_bottom_track_1_undriven_sram_inv; + wire [0:2] mux_bottom_track_25_undriven_sram_inv; + wire [0:1] mux_bottom_track_33_undriven_sram_inv; + wire [0:2] mux_bottom_track_3_undriven_sram_inv; + wire [0:2] mux_bottom_track_5_undriven_sram_inv; + wire [0:2] mux_bottom_track_9_undriven_sram_inv; + wire [0:2] mux_right_track_0_undriven_sram_inv; + wire [0:2] mux_right_track_10_undriven_sram_inv; + wire [0:2] mux_right_track_12_undriven_sram_inv; + wire [0:2] mux_right_track_14_undriven_sram_inv; + wire [0:1] mux_right_track_16_undriven_sram_inv; + wire [0:1] mux_right_track_18_undriven_sram_inv; + wire [0:1] mux_right_track_20_undriven_sram_inv; + wire [0:1] mux_right_track_22_undriven_sram_inv; + wire [0:2] mux_right_track_24_undriven_sram_inv; + wire [0:1] mux_right_track_26_undriven_sram_inv; + wire [0:1] mux_right_track_28_undriven_sram_inv; + wire [0:2] mux_right_track_2_undriven_sram_inv; + wire [0:1] mux_right_track_30_undriven_sram_inv; + wire [0:1] mux_right_track_32_undriven_sram_inv; + wire [0:1] mux_right_track_34_undriven_sram_inv; + wire [0:1] mux_right_track_36_undriven_sram_inv; + wire [0:2] mux_right_track_4_undriven_sram_inv; + wire [0:2] mux_right_track_6_undriven_sram_inv; + wire [0:2] mux_right_track_8_undriven_sram_inv; + wire [0:2] mux_top_track_0_undriven_sram_inv; + wire [0:2] mux_top_track_16_undriven_sram_inv; + wire [0:2] mux_top_track_24_undriven_sram_inv; + wire [0:2] mux_top_track_2_undriven_sram_inv; + wire [0:2] mux_top_track_32_undriven_sram_inv; + wire [0:2] mux_top_track_4_undriven_sram_inv; + wire [0:2] mux_top_track_8_undriven_sram_inv; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; @@ -41,33 +68,21 @@ module sb_0__1_ wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; wire [0:2] mux_tree_tapbuf_size4_4_sram; - wire [0:2] mux_tree_tapbuf_size4_4_sram_inv; wire [0:2] mux_tree_tapbuf_size4_5_sram; - wire [0:2] mux_tree_tapbuf_size4_5_sram_inv; wire [0:2] mux_tree_tapbuf_size4_6_sram; - wire [0:2] mux_tree_tapbuf_size4_6_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; @@ -76,34 +91,22 @@ module sb_0__1_ wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; wire [0:2] mux_tree_tapbuf_size5_2_sram; - wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; wire [0:2] mux_tree_tapbuf_size5_3_sram; - wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; wire [0:2] mux_tree_tapbuf_size5_4_sram; - wire [0:2] mux_tree_tapbuf_size5_4_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; wire [0:2] mux_tree_tapbuf_size6_3_sram; - wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; wire [0:2] mux_tree_tapbuf_size6_4_sram; - wire [0:2] mux_tree_tapbuf_size6_4_sram_inv; wire [0:2] mux_tree_tapbuf_size6_5_sram; - wire [0:2] mux_tree_tapbuf_size6_5_sram_inv; wire [0:2] mux_tree_tapbuf_size6_6_sram; - wire [0:2] mux_tree_tapbuf_size6_6_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; @@ -112,11 +115,8 @@ module sb_0__1_ wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; @@ -153,7 +153,7 @@ module sb_0__1_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), .out(chany_top_out[0]) ); @@ -163,7 +163,7 @@ module sb_0__1_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), .out(chany_top_out[2]) ); @@ -173,7 +173,7 @@ module sb_0__1_ ( .in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }), .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), .out(chany_top_out[4]) ); @@ -183,7 +183,7 @@ module sb_0__1_ ( .in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }), .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), .out(chanx_right_out[0]) ); @@ -193,7 +193,7 @@ module sb_0__1_ ( .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), .out(chany_bottom_out[0]) ); @@ -203,7 +203,7 @@ module sb_0__1_ ( .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), .out(chany_bottom_out[2]) ); @@ -213,7 +213,7 @@ module sb_0__1_ ( .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), .out(chany_bottom_out[4]) ); @@ -224,8 +224,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -235,8 +234,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -246,8 +244,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) ); @@ -257,8 +254,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]) ); @@ -268,8 +264,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]) ); @@ -279,8 +274,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]) ); @@ -290,8 +284,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]) ); @@ -300,7 +293,7 @@ module sb_0__1_ ( .in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), .out(chany_top_out[1]) ); @@ -310,7 +303,7 @@ module sb_0__1_ ( .in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }), .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:2]), .out(chany_top_out[8]) ); @@ -320,7 +313,7 @@ module sb_0__1_ ( .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }), .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), .out(chany_bottom_out[1]) ); @@ -330,7 +323,7 @@ module sb_0__1_ ( .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }), .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]), .out(chany_bottom_out[8]) ); @@ -340,7 +333,7 @@ module sb_0__1_ ( .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }), .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_4_sram_inv[0:2]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), .out(chany_bottom_out[12]) ); @@ -351,8 +344,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -362,8 +354,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) ); @@ -373,8 +364,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]) ); @@ -384,8 +374,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]) ); @@ -395,8 +384,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]) ); @@ -405,7 +393,7 @@ module sb_0__1_ ( .in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:2]), .out(chany_top_out[12]) ); @@ -415,7 +403,7 @@ module sb_0__1_ ( .in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), .out(chany_top_out[16]) ); @@ -425,7 +413,7 @@ module sb_0__1_ ( .in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }), .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), .out(chanx_right_out[4]) ); @@ -435,7 +423,7 @@ module sb_0__1_ ( .in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }), .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:2]), .out(chanx_right_out[5]) ); @@ -445,7 +433,7 @@ module sb_0__1_ ( .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }), .sram(mux_tree_tapbuf_size4_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:2]), .out(chanx_right_out[6]) ); @@ -455,7 +443,7 @@ module sb_0__1_ ( .in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }), .sram(mux_tree_tapbuf_size4_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:2]), .out(chanx_right_out[7]) ); @@ -465,7 +453,7 @@ module sb_0__1_ ( .in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }), .sram(mux_tree_tapbuf_size4_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), .out(chanx_right_out[12]) ); @@ -476,8 +464,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -487,8 +474,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -498,8 +484,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) ); @@ -509,8 +494,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) ); @@ -520,8 +504,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]) ); @@ -531,8 +514,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]) ); @@ -542,8 +524,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]) ); @@ -552,7 +533,7 @@ module sb_0__1_ ( .in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }), .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), .out(chanx_right_out[1]) ); @@ -562,7 +543,7 @@ module sb_0__1_ ( .in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }), .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), .out(chanx_right_out[2]) ); @@ -572,7 +553,7 @@ module sb_0__1_ ( .in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), .out(chanx_right_out[3]) ); @@ -583,8 +564,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) ); @@ -594,8 +574,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) ); @@ -605,8 +584,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) ); @@ -615,7 +593,7 @@ module sb_0__1_ ( .in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), .out(chanx_right_out[8]) ); @@ -625,7 +603,7 @@ module sb_0__1_ ( .in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), .out(chanx_right_out[9]) ); @@ -635,7 +613,7 @@ module sb_0__1_ ( .in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }), .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), .out(chanx_right_out[10]) ); @@ -645,7 +623,7 @@ module sb_0__1_ ( .in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }), .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .sram_inv(mux_right_track_22_undriven_sram_inv[0:1]), .out(chanx_right_out[11]) ); @@ -655,7 +633,7 @@ module sb_0__1_ ( .in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }), .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]), .out(chany_bottom_out[16]) ); @@ -666,8 +644,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -677,8 +654,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -688,8 +664,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) ); @@ -699,8 +674,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) ); @@ -710,8 +684,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) ); @@ -720,7 +693,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), .out(chanx_right_out[13]) ); @@ -730,7 +703,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), .out(chanx_right_out[14]) ); @@ -740,7 +713,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), .out(chanx_right_out[15]) ); @@ -750,7 +723,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), .out(chanx_right_out[16]) ); @@ -760,7 +733,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), .out(chanx_right_out[17]) ); @@ -770,7 +743,7 @@ module sb_0__1_ ( .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:1]), .out(chanx_right_out[18]) ); @@ -781,8 +754,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -792,8 +764,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -803,8 +774,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -814,8 +784,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -825,8 +794,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -836,8 +804,7 @@ module sb_0__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v index 551751f..d1eab74 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v @@ -24,42 +24,48 @@ module sb_0__2_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:1] mux_bottom_track_1_undriven_sram_inv; + wire [0:1] mux_bottom_track_25_undriven_sram_inv; + wire [0:1] mux_bottom_track_5_undriven_sram_inv; + wire [0:1] mux_bottom_track_9_undriven_sram_inv; + wire [0:2] mux_right_track_0_undriven_sram_inv; + wire [0:1] mux_right_track_10_undriven_sram_inv; + wire [0:1] mux_right_track_12_undriven_sram_inv; + wire [0:1] mux_right_track_14_undriven_sram_inv; + wire [0:1] mux_right_track_16_undriven_sram_inv; + wire [0:1] mux_right_track_18_undriven_sram_inv; + wire [0:1] mux_right_track_20_undriven_sram_inv; + wire [0:1] mux_right_track_22_undriven_sram_inv; + wire [0:1] mux_right_track_24_undriven_sram_inv; + wire [0:1] mux_right_track_26_undriven_sram_inv; + wire [0:1] mux_right_track_28_undriven_sram_inv; + wire [0:2] mux_right_track_2_undriven_sram_inv; + wire [0:1] mux_right_track_30_undriven_sram_inv; + wire [0:1] mux_right_track_32_undriven_sram_inv; + wire [0:1] mux_right_track_34_undriven_sram_inv; + wire [0:1] mux_right_track_36_undriven_sram_inv; + wire [0:1] mux_right_track_38_undriven_sram_inv; + wire [0:2] mux_right_track_4_undriven_sram_inv; + wire [0:2] mux_right_track_6_undriven_sram_inv; + wire [0:1] mux_right_track_8_undriven_sram_inv; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; @@ -78,21 +84,15 @@ module sb_0__2_ wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; assign chany_bottom_out[18] = chanx_right_in[0]; @@ -119,7 +119,7 @@ module sb_0__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), .out(chanx_right_out[0]) ); @@ -129,7 +129,7 @@ module sb_0__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), .out(chanx_right_out[2]) ); @@ -140,8 +140,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -151,8 +150,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -161,7 +159,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), .out(chanx_right_out[1]) ); @@ -171,7 +169,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }), .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), .out(chanx_right_out[3]) ); @@ -182,8 +180,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -193,8 +190,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) ); @@ -203,7 +199,7 @@ module sb_0__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), .out(chanx_right_out[4]) ); @@ -213,7 +209,7 @@ module sb_0__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), .out(chanx_right_out[12]) ); @@ -224,8 +220,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -235,8 +230,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -245,7 +239,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), .out(chanx_right_out[5]) ); @@ -255,7 +249,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), .out(chanx_right_out[6]) ); @@ -265,7 +259,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), .out(chanx_right_out[7]) ); @@ -275,7 +269,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), .out(chanx_right_out[8]) ); @@ -285,7 +279,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), .out(chanx_right_out[9]) ); @@ -295,7 +289,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), .out(chanx_right_out[10]) ); @@ -305,7 +299,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }), .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .sram_inv(mux_right_track_22_undriven_sram_inv[0:1]), .out(chanx_right_out[11]) ); @@ -315,7 +309,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }), .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), .out(chanx_right_out[13]) ); @@ -325,7 +319,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }), .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), .out(chanx_right_out[14]) ); @@ -335,7 +329,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }), .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), .out(chanx_right_out[15]) ); @@ -345,7 +339,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }), .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), .out(chanx_right_out[16]) ); @@ -355,7 +349,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }), .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), .out(chanx_right_out[17]) ); @@ -365,7 +359,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }), .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .sram_inv(mux_right_track_36_undriven_sram_inv[0:1]), .out(chanx_right_out[18]) ); @@ -375,7 +369,7 @@ module sb_0__2_ ( .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }), .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .sram_inv(mux_right_track_38_undriven_sram_inv[0:1]), .out(chanx_right_out[19]) ); @@ -385,7 +379,7 @@ module sb_0__2_ ( .in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]), .out(chany_bottom_out[0]) ); @@ -395,7 +389,7 @@ module sb_0__2_ ( .in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]), .out(chany_bottom_out[2]) ); @@ -405,7 +399,7 @@ module sb_0__2_ ( .in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), .out(chany_bottom_out[4]) ); @@ -415,7 +409,7 @@ module sb_0__2_ ( .in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), .out(chany_bottom_out[12]) ); @@ -426,8 +420,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -437,8 +430,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -448,8 +440,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -459,8 +450,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -470,8 +460,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -481,8 +470,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); @@ -492,8 +480,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) ); @@ -503,8 +490,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) ); @@ -514,8 +500,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) ); @@ -525,8 +510,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) ); @@ -536,8 +520,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) ); @@ -547,8 +530,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) ); @@ -558,8 +540,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) ); @@ -569,8 +550,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) ); @@ -580,8 +560,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) ); @@ -591,8 +570,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) ); @@ -602,8 +580,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) ); @@ -613,8 +590,7 @@ module sb_0__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v index 926ad96..bf4569e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v @@ -36,29 +36,47 @@ module sb_1__0_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:2] mux_left_track_17_undriven_sram_inv; + wire [0:3] mux_left_track_1_undriven_sram_inv; + wire [0:2] mux_left_track_25_undriven_sram_inv; + wire [0:2] mux_left_track_33_undriven_sram_inv; + wire [0:2] mux_left_track_3_undriven_sram_inv; + wire [0:3] mux_left_track_5_undriven_sram_inv; + wire [0:2] mux_left_track_9_undriven_sram_inv; + wire [0:2] mux_right_track_0_undriven_sram_inv; + wire [0:2] mux_right_track_16_undriven_sram_inv; + wire [0:2] mux_right_track_24_undriven_sram_inv; + wire [0:3] mux_right_track_2_undriven_sram_inv; + wire [0:2] mux_right_track_32_undriven_sram_inv; + wire [0:3] mux_right_track_4_undriven_sram_inv; + wire [0:2] mux_right_track_8_undriven_sram_inv; + wire [0:3] mux_top_track_0_undriven_sram_inv; + wire [0:2] mux_top_track_10_undriven_sram_inv; + wire [0:1] mux_top_track_12_undriven_sram_inv; + wire [0:1] mux_top_track_14_undriven_sram_inv; + wire [0:1] mux_top_track_16_undriven_sram_inv; + wire [0:1] mux_top_track_18_undriven_sram_inv; + wire [0:1] mux_top_track_20_undriven_sram_inv; + wire [0:1] mux_top_track_22_undriven_sram_inv; + wire [0:1] mux_top_track_24_undriven_sram_inv; + wire [0:2] mux_top_track_2_undriven_sram_inv; + wire [0:1] mux_top_track_38_undriven_sram_inv; + wire [0:2] mux_top_track_4_undriven_sram_inv; + wire [0:2] mux_top_track_6_undriven_sram_inv; + wire [0:2] mux_top_track_8_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size11_0_sram; - wire [0:3] mux_tree_tapbuf_size11_0_sram_inv; wire [0:3] mux_tree_tapbuf_size11_1_sram; - wire [0:3] mux_tree_tapbuf_size11_1_sram_inv; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; wire [0:1] mux_tree_tapbuf_size3_5_sram; - wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; wire [0:1] mux_tree_tapbuf_size3_6_sram; - wire [0:1] mux_tree_tapbuf_size3_6_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; @@ -67,40 +85,25 @@ module sb_1__0_ wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; wire [0:2] mux_tree_tapbuf_size7_7_sram; - wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; wire [0:2] mux_tree_tapbuf_size7_8_sram; - wire [0:2] mux_tree_tapbuf_size7_8_sram_inv; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; @@ -111,11 +114,8 @@ module sb_1__0_ wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; @@ -159,7 +159,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), .out(chany_top_out[0]) ); @@ -169,7 +169,7 @@ module sb_1__0_ ( .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), .out(chanx_right_out[1]) ); @@ -179,7 +179,7 @@ module sb_1__0_ ( .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), .out(chanx_left_out[0]) ); @@ -190,8 +190,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -201,8 +200,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -212,8 +210,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -222,7 +219,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }), .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), .out(chany_top_out[1]) ); @@ -232,7 +229,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }), .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), .out(chany_top_out[2]) ); @@ -242,7 +239,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }), .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), .out(chany_top_out[3]) ); @@ -252,7 +249,7 @@ module sb_1__0_ ( .in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), .out(chanx_right_out[0]) ); @@ -262,7 +259,7 @@ module sb_1__0_ ( .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), .out(chanx_right_out[4]) ); @@ -272,7 +269,7 @@ module sb_1__0_ ( .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:2]), .out(chanx_right_out[8]) ); @@ -282,7 +279,7 @@ module sb_1__0_ ( .in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), .out(chanx_left_out[1]) ); @@ -292,7 +289,7 @@ module sb_1__0_ ( .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size7_7_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), .out(chanx_left_out[4]) ); @@ -302,7 +299,7 @@ module sb_1__0_ ( .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size7_8_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_8_sram_inv[0:2]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:2]), .out(chanx_left_out[8]) ); @@ -313,8 +310,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) ); @@ -324,8 +320,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) ); @@ -335,8 +330,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) ); @@ -346,8 +340,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) ); @@ -357,8 +350,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) ); @@ -368,8 +360,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) ); @@ -379,8 +370,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) ); @@ -390,8 +380,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]) ); @@ -401,8 +390,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_8_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_8_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_8_sram[0:2]) ); @@ -411,7 +399,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), .out(chany_top_out[4]) ); @@ -421,7 +409,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:2]), .out(chany_top_out[5]) ); @@ -432,8 +420,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -443,8 +430,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -453,7 +439,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), .out(chany_top_out[6]) ); @@ -463,7 +449,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), .out(chany_top_out[7]) ); @@ -473,7 +459,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), .out(chany_top_out[8]) ); @@ -483,7 +469,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), .out(chany_top_out[9]) ); @@ -493,7 +479,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), .out(chany_top_out[10]) ); @@ -503,7 +489,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), .out(chany_top_out[11]) ); @@ -513,7 +499,7 @@ module sb_1__0_ ( .in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), .out(chany_top_out[12]) ); @@ -524,8 +510,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -535,8 +520,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -546,8 +530,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) ); @@ -557,8 +540,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) ); @@ -568,8 +550,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) ); @@ -579,8 +560,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]) ); @@ -590,8 +570,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]) ); @@ -600,7 +579,7 @@ module sb_1__0_ ( .in({ chanx_right_in[0], chanx_left_in[1] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_top_track_38_undriven_sram_inv[0:1]), .out(chany_top_out[19]) ); @@ -611,8 +590,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -621,7 +599,7 @@ module sb_1__0_ ( .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size11_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size11_0_sram_inv[0:3]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), .out(chanx_right_out[2]) ); @@ -631,7 +609,7 @@ module sb_1__0_ ( .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size11_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size11_1_sram_inv[0:3]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), .out(chanx_left_out[2]) ); @@ -642,8 +620,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size11_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size11_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size11_0_sram[0:3]) ); @@ -653,8 +630,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size11_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size11_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size11_1_sram[0:3]) ); @@ -663,7 +639,7 @@ module sb_1__0_ ( .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), .out(chanx_right_out[12]) ); @@ -673,7 +649,7 @@ module sb_1__0_ ( .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:2]), .out(chanx_left_out[12]) ); @@ -684,8 +660,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -695,8 +670,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -705,7 +679,7 @@ module sb_1__0_ ( .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), .out(chanx_right_out[16]) ); @@ -715,7 +689,7 @@ module sb_1__0_ ( .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }), .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), .out(chanx_left_out[16]) ); @@ -726,8 +700,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -737,8 +710,7 @@ module sb_1__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v index 5fce9c4..48df5f7 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v @@ -46,30 +46,46 @@ module sb_1__1_ output [0:19] chanx_left_out; output [0:0] ccff_tail; + wire [0:3] mux_bottom_track_17_undriven_sram_inv; + wire [0:3] mux_bottom_track_1_undriven_sram_inv; + wire [0:3] mux_bottom_track_25_undriven_sram_inv; + wire [0:2] mux_bottom_track_33_undriven_sram_inv; + wire [0:3] mux_bottom_track_3_undriven_sram_inv; + wire [0:4] mux_bottom_track_5_undriven_sram_inv; + wire [0:3] mux_bottom_track_9_undriven_sram_inv; + wire [0:3] mux_left_track_17_undriven_sram_inv; + wire [0:3] mux_left_track_1_undriven_sram_inv; + wire [0:3] mux_left_track_25_undriven_sram_inv; + wire [0:2] mux_left_track_33_undriven_sram_inv; + wire [0:3] mux_left_track_3_undriven_sram_inv; + wire [0:4] mux_left_track_5_undriven_sram_inv; + wire [0:3] mux_left_track_9_undriven_sram_inv; + wire [0:3] mux_right_track_0_undriven_sram_inv; + wire [0:3] mux_right_track_16_undriven_sram_inv; + wire [0:3] mux_right_track_24_undriven_sram_inv; + wire [0:3] mux_right_track_2_undriven_sram_inv; + wire [0:2] mux_right_track_32_undriven_sram_inv; + wire [0:4] mux_right_track_4_undriven_sram_inv; + wire [0:3] mux_right_track_8_undriven_sram_inv; + wire [0:3] mux_top_track_0_undriven_sram_inv; + wire [0:3] mux_top_track_16_undriven_sram_inv; + wire [0:3] mux_top_track_24_undriven_sram_inv; + wire [0:3] mux_top_track_2_undriven_sram_inv; + wire [0:2] mux_top_track_32_undriven_sram_inv; + wire [0:4] mux_top_track_4_undriven_sram_inv; + wire [0:3] mux_top_track_8_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_10_sram; - wire [0:3] mux_tree_tapbuf_size10_10_sram_inv; wire [0:3] mux_tree_tapbuf_size10_11_sram; - wire [0:3] mux_tree_tapbuf_size10_11_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram_inv; wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram_inv; wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram_inv; wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram_inv; wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram_inv; wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram_inv; wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram_inv; wire [0:3] mux_tree_tapbuf_size10_9_sram; - wire [0:3] mux_tree_tapbuf_size10_9_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; @@ -83,21 +99,13 @@ module sb_1__1_ wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; wire [0:3] mux_tree_tapbuf_size12_0_sram; - wire [0:3] mux_tree_tapbuf_size12_0_sram_inv; wire [0:3] mux_tree_tapbuf_size12_1_sram; - wire [0:3] mux_tree_tapbuf_size12_1_sram_inv; wire [0:3] mux_tree_tapbuf_size12_2_sram; - wire [0:3] mux_tree_tapbuf_size12_2_sram_inv; wire [0:3] mux_tree_tapbuf_size12_3_sram; - wire [0:3] mux_tree_tapbuf_size12_3_sram_inv; wire [0:3] mux_tree_tapbuf_size12_4_sram; - wire [0:3] mux_tree_tapbuf_size12_4_sram_inv; wire [0:3] mux_tree_tapbuf_size12_5_sram; - wire [0:3] mux_tree_tapbuf_size12_5_sram_inv; wire [0:3] mux_tree_tapbuf_size12_6_sram; - wire [0:3] mux_tree_tapbuf_size12_6_sram_inv; wire [0:3] mux_tree_tapbuf_size12_7_sram; - wire [0:3] mux_tree_tapbuf_size12_7_sram_inv; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; @@ -107,25 +115,17 @@ module sb_1__1_ wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; wire [0:4] mux_tree_tapbuf_size16_0_sram; - wire [0:4] mux_tree_tapbuf_size16_0_sram_inv; wire [0:4] mux_tree_tapbuf_size16_1_sram; - wire [0:4] mux_tree_tapbuf_size16_1_sram_inv; wire [0:4] mux_tree_tapbuf_size16_2_sram; - wire [0:4] mux_tree_tapbuf_size16_2_sram_inv; wire [0:4] mux_tree_tapbuf_size16_3_sram; - wire [0:4] mux_tree_tapbuf_size16_3_sram_inv; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; @@ -187,7 +187,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size12_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_0_sram_inv[0:3]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), .out(chany_top_out[0]) ); @@ -197,7 +197,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }), .sram(mux_tree_tapbuf_size12_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_1_sram_inv[0:3]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), .out(chany_top_out[1]) ); @@ -207,7 +207,7 @@ module sb_1__1_ ( .in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size12_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_2_sram_inv[0:3]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), .out(chanx_right_out[0]) ); @@ -217,7 +217,7 @@ module sb_1__1_ ( .in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size12_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_3_sram_inv[0:3]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), .out(chanx_right_out[1]) ); @@ -227,7 +227,7 @@ module sb_1__1_ ( .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size12_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_4_sram_inv[0:3]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), .out(chany_bottom_out[0]) ); @@ -237,7 +237,7 @@ module sb_1__1_ ( .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size12_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_5_sram_inv[0:3]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), .out(chany_bottom_out[1]) ); @@ -247,7 +247,7 @@ module sb_1__1_ ( .in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size12_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_6_sram_inv[0:3]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), .out(chanx_left_out[0]) ); @@ -257,7 +257,7 @@ module sb_1__1_ ( .in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size12_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size12_7_sram_inv[0:3]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), .out(chanx_left_out[1]) ); @@ -268,8 +268,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]) ); @@ -279,8 +278,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]) ); @@ -290,8 +288,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]) ); @@ -301,8 +298,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]) ); @@ -312,8 +308,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]) ); @@ -323,8 +318,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]) ); @@ -334,8 +328,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]) ); @@ -345,8 +338,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size12_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]) ); @@ -355,7 +347,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }), .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_0_sram_inv[0:4]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:4]), .out(chany_top_out[2]) ); @@ -365,7 +357,7 @@ module sb_1__1_ ( .in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_1_sram_inv[0:4]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:4]), .out(chanx_right_out[2]) ); @@ -375,7 +367,7 @@ module sb_1__1_ ( .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size16_2_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_2_sram_inv[0:4]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:4]), .out(chany_bottom_out[2]) ); @@ -385,7 +377,7 @@ module sb_1__1_ ( .in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size16_3_sram[0:4]), - .sram_inv(mux_tree_tapbuf_size16_3_sram_inv[0:4]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:4]), .out(chanx_left_out[2]) ); @@ -396,8 +388,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_0_sram_inv[0:4]) + .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]) ); @@ -407,8 +398,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_1_sram_inv[0:4]) + .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]) ); @@ -418,8 +408,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_2_sram_inv[0:4]) + .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]) ); @@ -429,8 +418,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]), - .mem_outb(mux_tree_tapbuf_size16_3_sram_inv[0:4]) + .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]) ); @@ -439,7 +427,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:3]), .out(chany_top_out[4]) ); @@ -449,7 +437,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:3]), .out(chany_top_out[8]) ); @@ -459,7 +447,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:3]), .out(chany_top_out[12]) ); @@ -469,7 +457,7 @@ module sb_1__1_ ( .in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:3]), .out(chanx_right_out[4]) ); @@ -479,7 +467,7 @@ module sb_1__1_ ( .in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_4_sram_inv[0:3]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:3]), .out(chanx_right_out[8]) ); @@ -489,7 +477,7 @@ module sb_1__1_ ( .in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_5_sram_inv[0:3]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:3]), .out(chanx_right_out[12]) ); @@ -499,7 +487,7 @@ module sb_1__1_ ( .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_6_sram_inv[0:3]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]), .out(chany_bottom_out[4]) ); @@ -509,7 +497,7 @@ module sb_1__1_ ( .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_7_sram_inv[0:3]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:3]), .out(chany_bottom_out[8]) ); @@ -519,7 +507,7 @@ module sb_1__1_ ( .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }), .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_8_sram_inv[0:3]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:3]), .out(chany_bottom_out[12]) ); @@ -529,7 +517,7 @@ module sb_1__1_ ( .in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_9_sram_inv[0:3]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:3]), .out(chanx_left_out[4]) ); @@ -539,7 +527,7 @@ module sb_1__1_ ( .in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_10_sram_inv[0:3]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:3]), .out(chanx_left_out[8]) ); @@ -549,7 +537,7 @@ module sb_1__1_ ( .in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_11_sram_inv[0:3]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:3]), .out(chanx_left_out[12]) ); @@ -560,8 +548,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -571,8 +558,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -582,8 +568,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) ); @@ -593,8 +578,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) ); @@ -604,8 +588,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) ); @@ -615,8 +598,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) ); @@ -626,8 +608,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) ); @@ -637,8 +618,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) ); @@ -648,8 +628,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_8_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) ); @@ -659,8 +638,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_9_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]) ); @@ -670,8 +648,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_10_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]) ); @@ -681,8 +658,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_11_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]) ); @@ -691,7 +667,7 @@ module sb_1__1_ ( .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), .out(chany_top_out[16]) ); @@ -701,7 +677,7 @@ module sb_1__1_ ( .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), .out(chanx_right_out[16]) ); @@ -711,7 +687,7 @@ module sb_1__1_ ( .in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]), .out(chany_bottom_out[16]) ); @@ -721,7 +697,7 @@ module sb_1__1_ ( .in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), .out(chanx_left_out[16]) ); @@ -732,8 +708,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) ); @@ -743,8 +718,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) ); @@ -754,8 +728,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) ); @@ -765,8 +738,7 @@ module sb_1__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v index 3b3a57a..0b691df 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v @@ -42,30 +42,48 @@ module sb_1__2_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:2] mux_bottom_track_11_undriven_sram_inv; + wire [0:1] mux_bottom_track_13_undriven_sram_inv; + wire [0:1] mux_bottom_track_15_undriven_sram_inv; + wire [0:1] mux_bottom_track_17_undriven_sram_inv; + wire [0:1] mux_bottom_track_19_undriven_sram_inv; + wire [0:2] mux_bottom_track_1_undriven_sram_inv; + wire [0:1] mux_bottom_track_21_undriven_sram_inv; + wire [0:1] mux_bottom_track_23_undriven_sram_inv; + wire [0:2] mux_bottom_track_25_undriven_sram_inv; + wire [0:1] mux_bottom_track_27_undriven_sram_inv; + wire [0:2] mux_bottom_track_3_undriven_sram_inv; + wire [0:2] mux_bottom_track_5_undriven_sram_inv; + wire [0:2] mux_bottom_track_7_undriven_sram_inv; + wire [0:2] mux_bottom_track_9_undriven_sram_inv; + wire [0:2] mux_left_track_17_undriven_sram_inv; + wire [0:3] mux_left_track_1_undriven_sram_inv; + wire [0:2] mux_left_track_25_undriven_sram_inv; + wire [0:2] mux_left_track_33_undriven_sram_inv; + wire [0:3] mux_left_track_3_undriven_sram_inv; + wire [0:3] mux_left_track_5_undriven_sram_inv; + wire [0:3] mux_left_track_9_undriven_sram_inv; + wire [0:3] mux_right_track_0_undriven_sram_inv; + wire [0:2] mux_right_track_16_undriven_sram_inv; + wire [0:2] mux_right_track_24_undriven_sram_inv; + wire [0:3] mux_right_track_2_undriven_sram_inv; + wire [0:2] mux_right_track_32_undriven_sram_inv; + wire [0:3] mux_right_track_4_undriven_sram_inv; + wire [0:3] mux_right_track_8_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:3] mux_tree_tapbuf_size14_0_sram; - wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; wire [0:3] mux_tree_tapbuf_size14_1_sram; - wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; wire [0:1] mux_tree_tapbuf_size3_5_sram; - wire [0:1] mux_tree_tapbuf_size3_5_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; @@ -73,35 +91,22 @@ module sb_1__2_ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; wire [0:2] mux_tree_tapbuf_size7_7_sram; - wire [0:2] mux_tree_tapbuf_size7_7_sram_inv; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; @@ -111,17 +116,12 @@ module sb_1__2_ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:3] mux_tree_tapbuf_size9_0_sram; - wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; wire [0:3] mux_tree_tapbuf_size9_1_sram; - wire [0:3] mux_tree_tapbuf_size9_1_sram_inv; wire [0:3] mux_tree_tapbuf_size9_2_sram; - wire [0:3] mux_tree_tapbuf_size9_2_sram_inv; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; @@ -165,7 +165,7 @@ module sb_1__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), .out(chanx_right_out[0]) ); @@ -176,8 +176,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -186,7 +185,7 @@ module sb_1__2_ ( .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), .out(chanx_right_out[1]) ); @@ -196,7 +195,7 @@ module sb_1__2_ ( .in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size9_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), .out(chanx_left_out[0]) ); @@ -206,7 +205,7 @@ module sb_1__2_ ( .in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size9_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), .out(chanx_left_out[1]) ); @@ -217,8 +216,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]) ); @@ -228,8 +226,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]) ); @@ -239,8 +236,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size9_2_sram[0:3]) ); @@ -249,7 +245,7 @@ module sb_1__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), .out(chanx_right_out[2]) ); @@ -259,7 +255,7 @@ module sb_1__2_ ( .in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), .out(chanx_left_out[2]) ); @@ -270,8 +266,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]) ); @@ -281,8 +276,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]) ); @@ -291,7 +285,7 @@ module sb_1__2_ ( .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_right_track_8_undriven_sram_inv[0:3]), .out(chanx_right_out[4]) ); @@ -301,7 +295,7 @@ module sb_1__2_ ( .in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:3]), .out(chanx_left_out[4]) ); @@ -312,8 +306,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -323,8 +316,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -333,7 +325,7 @@ module sb_1__2_ ( .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .sram_inv(mux_right_track_16_undriven_sram_inv[0:2]), .out(chanx_right_out[8]) ); @@ -343,7 +335,7 @@ module sb_1__2_ ( .in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), .out(chanx_right_out[12]) ); @@ -353,7 +345,7 @@ module sb_1__2_ ( .in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }), .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), .out(chany_bottom_out[0]) ); @@ -363,7 +355,7 @@ module sb_1__2_ ( .in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }), .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), .out(chany_bottom_out[1]) ); @@ -373,7 +365,7 @@ module sb_1__2_ ( .in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }), .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), .out(chany_bottom_out[2]) ); @@ -383,7 +375,7 @@ module sb_1__2_ ( .in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }), .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), .out(chany_bottom_out[3]) ); @@ -393,7 +385,7 @@ module sb_1__2_ ( .in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:2]), .out(chanx_left_out[8]) ); @@ -403,7 +395,7 @@ module sb_1__2_ ( .in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size7_7_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_7_sram_inv[0:2]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:2]), .out(chanx_left_out[12]) ); @@ -414,8 +406,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) ); @@ -425,8 +416,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) ); @@ -436,8 +426,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) ); @@ -447,8 +436,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) ); @@ -458,8 +446,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) ); @@ -469,8 +456,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) ); @@ -480,8 +466,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) ); @@ -491,8 +476,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_7_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]) ); @@ -501,7 +485,7 @@ module sb_1__2_ ( .in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), .out(chanx_right_out[16]) ); @@ -512,8 +496,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -522,7 +505,7 @@ module sb_1__2_ ( .in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), .out(chany_bottom_out[4]) ); @@ -532,7 +515,7 @@ module sb_1__2_ ( .in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]), .out(chany_bottom_out[5]) ); @@ -542,7 +525,7 @@ module sb_1__2_ ( .in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), .out(chany_bottom_out[12]) ); @@ -553,8 +536,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -564,8 +546,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -575,8 +556,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) ); @@ -585,7 +565,7 @@ module sb_1__2_ ( .in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), .out(chany_bottom_out[6]) ); @@ -595,7 +575,7 @@ module sb_1__2_ ( .in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), .out(chany_bottom_out[7]) ); @@ -605,7 +585,7 @@ module sb_1__2_ ( .in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), .out(chany_bottom_out[8]) ); @@ -615,7 +595,7 @@ module sb_1__2_ ( .in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), .out(chany_bottom_out[9]) ); @@ -625,7 +605,7 @@ module sb_1__2_ ( .in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), .out(chany_bottom_out[10]) ); @@ -635,7 +615,7 @@ module sb_1__2_ ( .in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]), + .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), .out(chany_bottom_out[11]) ); @@ -646,8 +626,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -657,8 +636,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -668,8 +646,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) ); @@ -679,8 +656,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) ); @@ -690,8 +666,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) ); @@ -701,8 +676,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]) ); @@ -711,7 +685,7 @@ module sb_1__2_ ( .in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), .out(chany_bottom_out[13]) ); @@ -722,8 +696,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -732,7 +705,7 @@ module sb_1__2_ ( .in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), .out(chanx_left_out[16]) ); @@ -743,8 +716,7 @@ module sb_1__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v index a2f72b6..c8a7319 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v @@ -25,46 +25,56 @@ module sb_2__0_ output [0:19] chanx_left_out; output [0:0] ccff_tail; + wire [0:1] mux_left_track_11_undriven_sram_inv; + wire [0:1] mux_left_track_13_undriven_sram_inv; + wire [0:1] mux_left_track_15_undriven_sram_inv; + wire [0:1] mux_left_track_17_undriven_sram_inv; + wire [0:1] mux_left_track_19_undriven_sram_inv; + wire [0:2] mux_left_track_1_undriven_sram_inv; + wire [0:1] mux_left_track_25_undriven_sram_inv; + wire [0:1] mux_left_track_27_undriven_sram_inv; + wire [0:1] mux_left_track_29_undriven_sram_inv; + wire [0:1] mux_left_track_31_undriven_sram_inv; + wire [0:1] mux_left_track_33_undriven_sram_inv; + wire [0:1] mux_left_track_35_undriven_sram_inv; + wire [0:2] mux_left_track_3_undriven_sram_inv; + wire [0:2] mux_left_track_5_undriven_sram_inv; + wire [0:2] mux_left_track_7_undriven_sram_inv; + wire [0:1] mux_left_track_9_undriven_sram_inv; + wire [0:2] mux_top_track_0_undriven_sram_inv; + wire [0:1] mux_top_track_10_undriven_sram_inv; + wire [0:1] mux_top_track_12_undriven_sram_inv; + wire [0:1] mux_top_track_14_undriven_sram_inv; + wire [0:1] mux_top_track_16_undriven_sram_inv; + wire [0:1] mux_top_track_18_undriven_sram_inv; + wire [0:1] mux_top_track_20_undriven_sram_inv; + wire [0:1] mux_top_track_22_undriven_sram_inv; + wire [0:1] mux_top_track_24_undriven_sram_inv; + wire [0:1] mux_top_track_26_undriven_sram_inv; + wire [0:2] mux_top_track_2_undriven_sram_inv; + wire [0:2] mux_top_track_4_undriven_sram_inv; + wire [0:2] mux_top_track_6_undriven_sram_inv; + wire [0:1] mux_top_track_8_undriven_sram_inv; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; wire [0:1] mux_tree_tapbuf_size2_18_sram; - wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; wire [0:1] mux_tree_tapbuf_size2_19_sram; - wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; @@ -85,33 +95,23 @@ module sb_2__0_ wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; assign chanx_left_out[19] = chany_top_in[1]; @@ -130,7 +130,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), .out(chany_top_out[0]) ); @@ -140,7 +140,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), .out(chany_top_out[2]) ); @@ -151,8 +151,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -162,8 +161,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -172,7 +170,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), .out(chany_top_out[1]) ); @@ -182,7 +180,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), .out(chany_top_out[3]) ); @@ -193,8 +191,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -204,8 +201,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) ); @@ -214,7 +210,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), .out(chany_top_out[4]) ); @@ -224,7 +220,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), .out(chany_top_out[12]) ); @@ -235,8 +231,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -246,8 +241,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -256,7 +250,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_43_[0], chanx_left_in[15] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_top_track_10_undriven_sram_inv[0:1]), .out(chany_top_out[5]) ); @@ -266,7 +260,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_44_[0], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), .out(chany_top_out[6]) ); @@ -276,7 +270,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_45_[0], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), .out(chany_top_out[7]) ); @@ -286,7 +280,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_46_[0], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), .out(chany_top_out[8]) ); @@ -296,7 +290,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_47_[0], chanx_left_in[11] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), .out(chany_top_out[9]) ); @@ -306,7 +300,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_48_[0], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), .out(chany_top_out[10]) ); @@ -316,7 +310,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_49_[0], chanx_left_in[9] }), .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), .out(chany_top_out[11]) ); @@ -326,7 +320,7 @@ module sb_2__0_ ( .in({ top_left_grid_pin_43_[0], chanx_left_in[7] }), .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .sram_inv(mux_top_track_26_undriven_sram_inv[0:1]), .out(chany_top_out[13]) ); @@ -336,7 +330,7 @@ module sb_2__0_ ( .in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), .out(chanx_left_out[4]) ); @@ -346,7 +340,7 @@ module sb_2__0_ ( .in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }), .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), .out(chanx_left_out[5]) ); @@ -356,7 +350,7 @@ module sb_2__0_ ( .in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }), .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), .out(chanx_left_out[6]) ); @@ -366,7 +360,7 @@ module sb_2__0_ ( .in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }), .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), .out(chanx_left_out[7]) ); @@ -376,7 +370,7 @@ module sb_2__0_ ( .in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), .out(chanx_left_out[8]) ); @@ -386,7 +380,7 @@ module sb_2__0_ ( .in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), .out(chanx_left_out[9]) ); @@ -396,7 +390,7 @@ module sb_2__0_ ( .in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }), .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), .out(chanx_left_out[12]) ); @@ -406,7 +400,7 @@ module sb_2__0_ ( .in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }), .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), .out(chanx_left_out[13]) ); @@ -416,7 +410,7 @@ module sb_2__0_ ( .in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }), .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), .out(chanx_left_out[14]) ); @@ -426,7 +420,7 @@ module sb_2__0_ ( .in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }), .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), .out(chanx_left_out[15]) ); @@ -436,7 +430,7 @@ module sb_2__0_ ( .in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), .out(chanx_left_out[16]) ); @@ -446,7 +440,7 @@ module sb_2__0_ ( .in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), .out(chanx_left_out[17]) ); @@ -457,8 +451,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -468,8 +461,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -479,8 +471,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -490,8 +481,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -501,8 +491,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -512,8 +501,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); @@ -523,8 +511,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) ); @@ -534,8 +521,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) ); @@ -545,8 +531,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) ); @@ -556,8 +541,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) ); @@ -567,8 +551,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) ); @@ -578,8 +561,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) ); @@ -589,8 +571,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) ); @@ -600,8 +581,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) ); @@ -611,8 +591,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) ); @@ -622,8 +601,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) ); @@ -633,8 +611,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) ); @@ -644,8 +621,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) ); @@ -655,8 +631,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]) ); @@ -666,8 +641,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]) ); @@ -676,7 +650,7 @@ module sb_2__0_ ( .in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), .out(chanx_left_out[0]) ); @@ -686,7 +660,7 @@ module sb_2__0_ ( .in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), .out(chanx_left_out[1]) ); @@ -696,7 +670,7 @@ module sb_2__0_ ( .in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), .out(chanx_left_out[2]) ); @@ -706,7 +680,7 @@ module sb_2__0_ ( .in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), .out(chanx_left_out[3]) ); @@ -717,8 +691,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -728,8 +701,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -739,8 +711,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) ); @@ -750,8 +721,7 @@ module sb_2__0_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v index 0cbcc4e..2052030 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v @@ -38,85 +38,89 @@ module sb_2__1_ output [0:19] chanx_left_out; output [0:0] ccff_tail; + wire [0:2] mux_bottom_track_17_undriven_sram_inv; + wire [0:3] mux_bottom_track_1_undriven_sram_inv; + wire [0:2] mux_bottom_track_25_undriven_sram_inv; + wire [0:2] mux_bottom_track_33_undriven_sram_inv; + wire [0:3] mux_bottom_track_3_undriven_sram_inv; + wire [0:3] mux_bottom_track_5_undriven_sram_inv; + wire [0:3] mux_bottom_track_9_undriven_sram_inv; + wire [0:2] mux_left_track_11_undriven_sram_inv; + wire [0:2] mux_left_track_13_undriven_sram_inv; + wire [0:2] mux_left_track_15_undriven_sram_inv; + wire [0:1] mux_left_track_17_undriven_sram_inv; + wire [0:1] mux_left_track_19_undriven_sram_inv; + wire [0:2] mux_left_track_1_undriven_sram_inv; + wire [0:1] mux_left_track_21_undriven_sram_inv; + wire [0:1] mux_left_track_23_undriven_sram_inv; + wire [0:1] mux_left_track_25_undriven_sram_inv; + wire [0:1] mux_left_track_29_undriven_sram_inv; + wire [0:1] mux_left_track_31_undriven_sram_inv; + wire [0:1] mux_left_track_33_undriven_sram_inv; + wire [0:1] mux_left_track_35_undriven_sram_inv; + wire [0:1] mux_left_track_37_undriven_sram_inv; + wire [0:1] mux_left_track_39_undriven_sram_inv; + wire [0:2] mux_left_track_3_undriven_sram_inv; + wire [0:2] mux_left_track_5_undriven_sram_inv; + wire [0:2] mux_left_track_7_undriven_sram_inv; + wire [0:2] mux_left_track_9_undriven_sram_inv; + wire [0:3] mux_top_track_0_undriven_sram_inv; + wire [0:2] mux_top_track_16_undriven_sram_inv; + wire [0:2] mux_top_track_24_undriven_sram_inv; + wire [0:3] mux_top_track_2_undriven_sram_inv; + wire [0:2] mux_top_track_32_undriven_sram_inv; + wire [0:3] mux_top_track_4_undriven_sram_inv; + wire [0:3] mux_top_track_8_undriven_sram_inv; wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram_inv; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; wire [0:3] mux_tree_tapbuf_size14_0_sram; - wire [0:3] mux_tree_tapbuf_size14_0_sram_inv; wire [0:3] mux_tree_tapbuf_size14_1_sram; - wire [0:3] mux_tree_tapbuf_size14_1_sram_inv; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram_inv; wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_0_sram_inv; wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram_inv; wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram_inv; wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram_inv; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram_inv; wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram_inv; wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram_inv; wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram_inv; wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram_inv; wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram_inv; wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram_inv; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; @@ -125,16 +129,12 @@ module sb_2__1_ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_0_sram_inv; wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram_inv; wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram_inv; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; wire [0:3] mux_tree_tapbuf_size9_0_sram; - wire [0:3] mux_tree_tapbuf_size9_0_sram_inv; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; assign chany_bottom_out[3] = chany_top_in[2]; assign chany_bottom_out[5] = chany_top_in[4]; @@ -169,7 +169,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]), + .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), .out(chany_top_out[0]) ); @@ -179,7 +179,7 @@ module sb_2__1_ ( .in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), .out(chany_bottom_out[0]) ); @@ -190,8 +190,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) ); @@ -201,8 +200,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) ); @@ -211,7 +209,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]), + .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), .out(chany_top_out[1]) ); @@ -221,7 +219,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]), + .sram_inv(mux_top_track_8_undriven_sram_inv[0:3]), .out(chany_top_out[4]) ); @@ -231,7 +229,7 @@ module sb_2__1_ ( .in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]), .out(chany_bottom_out[4]) ); @@ -242,8 +240,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) ); @@ -253,8 +250,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) ); @@ -264,8 +260,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) ); @@ -274,7 +269,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_0_sram_inv[0:3]), + .sram_inv(mux_top_track_4_undriven_sram_inv[0:3]), .out(chany_top_out[2]) ); @@ -284,7 +279,7 @@ module sb_2__1_ ( .in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size14_1_sram_inv[0:3]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]), .out(chany_bottom_out[2]) ); @@ -295,8 +290,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]) ); @@ -306,8 +300,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size14_1_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]) ); @@ -316,7 +309,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_0_sram_inv[0:2]), + .sram_inv(mux_top_track_16_undriven_sram_inv[0:2]), .out(chany_top_out[8]) ); @@ -326,7 +319,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_1_sram_inv[0:2]), + .sram_inv(mux_top_track_24_undriven_sram_inv[0:2]), .out(chany_top_out[12]) ); @@ -336,7 +329,7 @@ module sb_2__1_ ( .in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]), .out(chany_bottom_out[8]) ); @@ -346,7 +339,7 @@ module sb_2__1_ ( .in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_3_sram_inv[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), .out(chanx_left_out[0]) ); @@ -356,7 +349,7 @@ module sb_2__1_ ( .in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_4_sram_inv[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), .out(chanx_left_out[1]) ); @@ -366,7 +359,7 @@ module sb_2__1_ ( .in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_5_sram_inv[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), .out(chanx_left_out[2]) ); @@ -376,7 +369,7 @@ module sb_2__1_ ( .in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size7_6_sram_inv[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), .out(chanx_left_out[3]) ); @@ -387,8 +380,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) ); @@ -398,8 +390,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) ); @@ -409,8 +400,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) ); @@ -420,8 +410,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) ); @@ -431,8 +420,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_4_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) ); @@ -442,8 +430,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_5_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) ); @@ -453,8 +440,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size7_6_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) ); @@ -463,7 +449,7 @@ module sb_2__1_ ( .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), .out(chany_top_out[16]) ); @@ -473,7 +459,7 @@ module sb_2__1_ ( .in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), .out(chany_bottom_out[12]) ); @@ -483,7 +469,7 @@ module sb_2__1_ ( .in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]), .out(chany_bottom_out[16]) ); @@ -494,8 +480,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -505,8 +490,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -516,8 +500,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) ); @@ -526,7 +509,7 @@ module sb_2__1_ ( .in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), .out(chany_bottom_out[1]) ); @@ -537,8 +520,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]), - .mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]) + .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]) ); @@ -547,7 +529,7 @@ module sb_2__1_ ( .in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }), .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), .out(chanx_left_out[4]) ); @@ -557,7 +539,7 @@ module sb_2__1_ ( .in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }), .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:2]), .out(chanx_left_out[5]) ); @@ -567,7 +549,7 @@ module sb_2__1_ ( .in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }), .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:2]), .out(chanx_left_out[6]) ); @@ -577,7 +559,7 @@ module sb_2__1_ ( .in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }), .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:2]), .out(chanx_left_out[7]) ); @@ -588,8 +570,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) ); @@ -599,8 +580,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) ); @@ -610,8 +590,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) ); @@ -621,8 +600,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) ); @@ -631,7 +609,7 @@ module sb_2__1_ ( .in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), .out(chanx_left_out[8]) ); @@ -641,7 +619,7 @@ module sb_2__1_ ( .in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), .out(chanx_left_out[9]) ); @@ -651,7 +629,7 @@ module sb_2__1_ ( .in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), .out(chanx_left_out[10]) ); @@ -661,7 +639,7 @@ module sb_2__1_ ( .in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]), + .sram_inv(mux_left_track_23_undriven_sram_inv[0:1]), .out(chanx_left_out[11]) ); @@ -671,7 +649,7 @@ module sb_2__1_ ( .in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }), .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), .out(chanx_left_out[12]) ); @@ -682,8 +660,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -693,8 +670,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -704,8 +680,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) ); @@ -715,8 +690,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) ); @@ -726,8 +700,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) ); @@ -736,7 +709,7 @@ module sb_2__1_ ( .in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), .out(chanx_left_out[14]) ); @@ -746,7 +719,7 @@ module sb_2__1_ ( .in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), .out(chanx_left_out[15]) ); @@ -756,7 +729,7 @@ module sb_2__1_ ( .in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), .out(chanx_left_out[16]) ); @@ -766,7 +739,7 @@ module sb_2__1_ ( .in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), .out(chanx_left_out[17]) ); @@ -776,7 +749,7 @@ module sb_2__1_ ( .in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), .out(chanx_left_out[18]) ); @@ -786,7 +759,7 @@ module sb_2__1_ ( .in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_left_track_39_undriven_sram_inv[0:1]), .out(chanx_left_out[19]) ); @@ -797,8 +770,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -808,8 +780,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -819,8 +790,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -830,8 +800,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -841,8 +810,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -852,8 +820,7 @@ module sb_2__1_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v index 61785a3..3c0b2d6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v @@ -32,54 +32,65 @@ module sb_2__2_ output SC_OUT_TOP; output SC_OUT_BOT; + wire [0:1] mux_bottom_track_11_undriven_sram_inv; + wire [0:1] mux_bottom_track_13_undriven_sram_inv; + wire [0:1] mux_bottom_track_15_undriven_sram_inv; + wire [0:1] mux_bottom_track_17_undriven_sram_inv; + wire [0:1] mux_bottom_track_19_undriven_sram_inv; + wire [0:2] mux_bottom_track_1_undriven_sram_inv; + wire [0:1] mux_bottom_track_21_undriven_sram_inv; + wire [0:1] mux_bottom_track_23_undriven_sram_inv; + wire [0:1] mux_bottom_track_25_undriven_sram_inv; + wire [0:1] mux_bottom_track_27_undriven_sram_inv; + wire [0:1] mux_bottom_track_29_undriven_sram_inv; + wire [0:2] mux_bottom_track_3_undriven_sram_inv; + wire [0:2] mux_bottom_track_5_undriven_sram_inv; + wire [0:2] mux_bottom_track_7_undriven_sram_inv; + wire [0:1] mux_bottom_track_9_undriven_sram_inv; + wire [0:1] mux_left_track_11_undriven_sram_inv; + wire [0:1] mux_left_track_13_undriven_sram_inv; + wire [0:1] mux_left_track_15_undriven_sram_inv; + wire [0:1] mux_left_track_17_undriven_sram_inv; + wire [0:1] mux_left_track_19_undriven_sram_inv; + wire [0:2] mux_left_track_1_undriven_sram_inv; + wire [0:1] mux_left_track_21_undriven_sram_inv; + wire [0:1] mux_left_track_23_undriven_sram_inv; + wire [0:1] mux_left_track_25_undriven_sram_inv; + wire [0:1] mux_left_track_27_undriven_sram_inv; + wire [0:1] mux_left_track_29_undriven_sram_inv; + wire [0:1] mux_left_track_31_undriven_sram_inv; + wire [0:1] mux_left_track_33_undriven_sram_inv; + wire [0:1] mux_left_track_35_undriven_sram_inv; + wire [0:1] mux_left_track_37_undriven_sram_inv; + wire [0:1] mux_left_track_39_undriven_sram_inv; + wire [0:2] mux_left_track_3_undriven_sram_inv; + wire [0:2] mux_left_track_5_undriven_sram_inv; + wire [0:2] mux_left_track_7_undriven_sram_inv; + wire [0:1] mux_left_track_9_undriven_sram_inv; wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram_inv; wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram_inv; wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram_inv; wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram_inv; wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram_inv; wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram_inv; wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram_inv; wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram_inv; wire [0:1] mux_tree_tapbuf_size2_18_sram; - wire [0:1] mux_tree_tapbuf_size2_18_sram_inv; wire [0:1] mux_tree_tapbuf_size2_19_sram; - wire [0:1] mux_tree_tapbuf_size2_19_sram_inv; wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram_inv; wire [0:1] mux_tree_tapbuf_size2_20_sram; - wire [0:1] mux_tree_tapbuf_size2_20_sram_inv; wire [0:1] mux_tree_tapbuf_size2_21_sram; - wire [0:1] mux_tree_tapbuf_size2_21_sram_inv; wire [0:1] mux_tree_tapbuf_size2_22_sram; - wire [0:1] mux_tree_tapbuf_size2_22_sram_inv; wire [0:1] mux_tree_tapbuf_size2_23_sram; - wire [0:1] mux_tree_tapbuf_size2_23_sram_inv; wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram_inv; wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram_inv; wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram_inv; wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram_inv; wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram_inv; wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram_inv; wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram_inv; wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram_inv; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; @@ -104,34 +115,23 @@ module sb_2__2_ wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_0_sram_inv; wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram_inv; wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram_inv; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_0_sram_inv; wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram_inv; wire [0:2] mux_tree_tapbuf_size5_2_sram; - wire [0:2] mux_tree_tapbuf_size5_2_sram_inv; wire [0:2] mux_tree_tapbuf_size5_3_sram; - wire [0:2] mux_tree_tapbuf_size5_3_sram_inv; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_0_sram_inv; wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram_inv; wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram_inv; wire [0:2] mux_tree_tapbuf_size6_3_sram; - wire [0:2] mux_tree_tapbuf_size6_3_sram_inv; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; @@ -149,7 +149,7 @@ module sb_2__2_ ( .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }), .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]), + .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), .out(chany_bottom_out[0]) ); @@ -159,7 +159,7 @@ module sb_2__2_ ( .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }), .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]), + .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), .out(chany_bottom_out[2]) ); @@ -169,7 +169,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]), + .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), .out(chanx_left_out[0]) ); @@ -179,7 +179,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]), + .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), .out(chanx_left_out[2]) ); @@ -190,8 +190,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) ); @@ -201,8 +200,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) ); @@ -212,8 +210,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) ); @@ -223,8 +220,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]) ); @@ -233,7 +229,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }), .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]), + .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), .out(chany_bottom_out[1]) ); @@ -243,7 +239,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }), .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_1_sram_inv[0:2]), + .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), .out(chany_bottom_out[3]) ); @@ -253,7 +249,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_2_sram_inv[0:2]), + .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), .out(chanx_left_out[1]) ); @@ -263,7 +259,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_tree_tapbuf_size5_3_sram_inv[0:2]), + .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), .out(chanx_left_out[3]) ); @@ -274,8 +270,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) ); @@ -285,8 +280,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_1_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) ); @@ -296,8 +290,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_2_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]) ); @@ -307,8 +300,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]), - .mem_outb(mux_tree_tapbuf_size5_3_sram_inv[0:2]) + .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]) ); @@ -317,7 +309,7 @@ module sb_2__2_ ( .in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }), .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]), + .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), .out(chany_bottom_out[4]) ); @@ -327,7 +319,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }), .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]), + .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]), .out(chany_bottom_out[5]) ); @@ -337,7 +329,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }), .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]), + .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), .out(chany_bottom_out[6]) ); @@ -347,7 +339,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }), .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]), + .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), .out(chany_bottom_out[7]) ); @@ -357,7 +349,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }), .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]), + .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), .out(chany_bottom_out[8]) ); @@ -367,7 +359,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }), .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]), + .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), .out(chany_bottom_out[9]) ); @@ -377,7 +369,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }), .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]), + .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), .out(chany_bottom_out[10]) ); @@ -387,7 +379,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }), .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]), + .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), .out(chany_bottom_out[11]) ); @@ -397,7 +389,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }), .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]), + .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), .out(chany_bottom_out[13]) ); @@ -407,7 +399,7 @@ module sb_2__2_ ( .in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }), .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]), + .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]), .out(chany_bottom_out[14]) ); @@ -417,7 +409,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }), .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]), + .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), .out(chanx_left_out[5]) ); @@ -427,7 +419,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }), .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]), + .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), .out(chanx_left_out[6]) ); @@ -437,7 +429,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }), .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]), + .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), .out(chanx_left_out[7]) ); @@ -447,7 +439,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }), .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]), + .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), .out(chanx_left_out[8]) ); @@ -457,7 +449,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]), + .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), .out(chanx_left_out[9]) ); @@ -467,7 +459,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]), + .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), .out(chanx_left_out[10]) ); @@ -477,7 +469,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]), + .sram_inv(mux_left_track_23_undriven_sram_inv[0:1]), .out(chanx_left_out[11]) ); @@ -487,7 +479,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }), .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]), + .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), .out(chanx_left_out[13]) ); @@ -497,7 +489,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }), .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_18_sram_inv[0:1]), + .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), .out(chanx_left_out[14]) ); @@ -507,7 +499,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }), .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_19_sram_inv[0:1]), + .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), .out(chanx_left_out[15]) ); @@ -517,7 +509,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }), .sram(mux_tree_tapbuf_size2_20_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_20_sram_inv[0:1]), + .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), .out(chanx_left_out[16]) ); @@ -527,7 +519,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }), .sram(mux_tree_tapbuf_size2_21_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_21_sram_inv[0:1]), + .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), .out(chanx_left_out[17]) ); @@ -537,7 +529,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }), .sram(mux_tree_tapbuf_size2_22_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_22_sram_inv[0:1]), + .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), .out(chanx_left_out[18]) ); @@ -547,7 +539,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }), .sram(mux_tree_tapbuf_size2_23_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size2_23_sram_inv[0:1]), + .sram_inv(mux_left_track_39_undriven_sram_inv[0:1]), .out(chanx_left_out[19]) ); @@ -558,8 +550,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) ); @@ -569,8 +560,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) ); @@ -580,8 +570,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) ); @@ -591,8 +580,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) ); @@ -602,8 +590,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) ); @@ -613,8 +600,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) ); @@ -624,8 +610,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) ); @@ -635,8 +620,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) ); @@ -646,8 +630,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) ); @@ -657,8 +640,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) ); @@ -668,8 +650,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) ); @@ -679,8 +660,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) ); @@ -690,8 +670,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) ); @@ -701,8 +680,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) ); @@ -712,8 +690,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) ); @@ -723,8 +700,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) ); @@ -734,8 +710,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) ); @@ -745,8 +720,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) ); @@ -756,8 +730,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_18_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]) ); @@ -767,8 +740,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_19_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]) ); @@ -778,8 +750,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_20_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]) ); @@ -789,8 +760,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_21_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]) ); @@ -800,8 +770,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_22_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_22_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_22_sram[0:1]) ); @@ -811,8 +780,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_23_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size2_23_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size2_23_sram[0:1]) ); @@ -821,7 +789,7 @@ module sb_2__2_ ( .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }), .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]), + .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), .out(chany_bottom_out[12]) ); @@ -831,7 +799,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]), + .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), .out(chanx_left_out[4]) ); @@ -841,7 +809,7 @@ module sb_2__2_ ( .in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]), + .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), .out(chanx_left_out[12]) ); @@ -852,8 +820,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) ); @@ -863,8 +830,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) ); @@ -874,8 +840,7 @@ module sb_2__2_ .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]), - .mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]) + .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v index ad8b2cc..3febf86 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v @@ -12,8 +12,7 @@ module mux_tree_tapbuf_size10_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -22,8 +21,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -40,29 +37,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -73,8 +66,7 @@ endmodule module mux_tree_tapbuf_size8_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -83,8 +75,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -101,29 +91,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -134,8 +120,7 @@ endmodule module mux_tree_tapbuf_size4_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -144,8 +129,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:2] mem_out; -// -output [0:2] mem_outb; // // @@ -162,23 +145,20 @@ output [0:2] mem_outb; assign ccff_tail[0] = mem_out[2]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); endmodule // @@ -189,8 +169,7 @@ endmodule module mux_tree_tapbuf_size7_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -199,8 +178,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:2] mem_out; -// -output [0:2] mem_outb; // // @@ -217,23 +194,20 @@ output [0:2] mem_outb; assign ccff_tail[0] = mem_out[2]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); endmodule // @@ -244,8 +218,7 @@ endmodule module mux_tree_tapbuf_size11_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -254,8 +227,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -272,29 +243,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -305,8 +272,7 @@ endmodule module mux_tree_tapbuf_size2_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -315,8 +281,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:1] mem_out; -// -output [0:1] mem_outb; // // @@ -333,17 +297,15 @@ output [0:1] mem_outb; assign ccff_tail[0] = mem_out[1]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); endmodule // @@ -354,8 +316,7 @@ endmodule module mux_tree_tapbuf_size6_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -364,8 +325,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:2] mem_out; -// -output [0:2] mem_outb; // // @@ -382,23 +341,20 @@ output [0:2] mem_outb; assign ccff_tail[0] = mem_out[2]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); endmodule // @@ -409,8 +365,7 @@ endmodule module mux_tree_tapbuf_size5_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -419,8 +374,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:2] mem_out; -// -output [0:2] mem_outb; // // @@ -437,23 +390,20 @@ output [0:2] mem_outb; assign ccff_tail[0] = mem_out[2]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); endmodule // @@ -464,8 +414,7 @@ endmodule module mux_tree_tapbuf_size12_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -474,8 +423,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -492,29 +439,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -525,8 +468,7 @@ endmodule module mux_tree_tapbuf_size16_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -535,8 +477,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:4] mem_out; -// -output [0:4] mem_outb; // // @@ -553,35 +493,30 @@ output [0:4] mem_outb; assign ccff_tail[0] = mem_out[4]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .CLK(prog_clk[0]), .D(mem_out[3]), - .Q(mem_out[4]), - .Q_N(mem_outb[4])); + .Q(mem_out[4])); endmodule // @@ -592,8 +527,7 @@ endmodule module mux_tree_tapbuf_size3_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -602,8 +536,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:1] mem_out; -// -output [0:1] mem_outb; // // @@ -620,17 +552,15 @@ output [0:1] mem_outb; assign ccff_tail[0] = mem_out[1]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); endmodule // @@ -641,8 +571,7 @@ endmodule module mux_tree_tapbuf_size9_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -651,8 +580,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -669,29 +596,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -702,8 +625,7 @@ endmodule module mux_tree_tapbuf_size14_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -712,8 +634,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:3] mem_out; -// -output [0:3] mem_outb; // // @@ -730,29 +650,25 @@ output [0:3] mem_outb; assign ccff_tail[0] = mem_out[3]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); endmodule // @@ -763,8 +679,7 @@ endmodule module mux_tree_size2_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -773,8 +688,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:1] mem_out; -// -output [0:1] mem_outb; // // @@ -791,17 +704,15 @@ output [0:1] mem_outb; assign ccff_tail[0] = mem_out[1]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); endmodule // @@ -809,11 +720,10 @@ endmodule // -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, +module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -822,8 +732,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:16] mem_out; -// -output [0:16] mem_outb; // // @@ -840,107 +748,90 @@ output [0:16] mem_outb; assign ccff_tail[0] = mem_out[16]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .CLK(prog_clk[0]), .D(mem_out[0]), - .Q(mem_out[1]), - .Q_N(mem_outb[1])); + .Q(mem_out[1])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .CLK(prog_clk[0]), .D(mem_out[1]), - .Q(mem_out[2]), - .Q_N(mem_outb[2])); + .Q(mem_out[2])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .CLK(prog_clk[0]), .D(mem_out[2]), - .Q(mem_out[3]), - .Q_N(mem_outb[3])); + .Q(mem_out[3])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .CLK(prog_clk[0]), .D(mem_out[3]), - .Q(mem_out[4]), - .Q_N(mem_outb[4])); + .Q(mem_out[4])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .CLK(prog_clk[0]), .D(mem_out[4]), - .Q(mem_out[5]), - .Q_N(mem_outb[5])); + .Q(mem_out[5])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .CLK(prog_clk[0]), .D(mem_out[5]), - .Q(mem_out[6]), - .Q_N(mem_outb[6])); + .Q(mem_out[6])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .CLK(prog_clk[0]), .D(mem_out[6]), - .Q(mem_out[7]), - .Q_N(mem_outb[7])); + .Q(mem_out[7])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .CLK(prog_clk[0]), .D(mem_out[7]), - .Q(mem_out[8]), - .Q_N(mem_outb[8])); + .Q(mem_out[8])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .CLK(prog_clk[0]), .D(mem_out[8]), - .Q(mem_out[9]), - .Q_N(mem_outb[9])); + .Q(mem_out[9])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .CLK(prog_clk[0]), .D(mem_out[9]), - .Q(mem_out[10]), - .Q_N(mem_outb[10])); + .Q(mem_out[10])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .CLK(prog_clk[0]), .D(mem_out[10]), - .Q(mem_out[11]), - .Q_N(mem_outb[11])); + .Q(mem_out[11])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .CLK(prog_clk[0]), .D(mem_out[11]), - .Q(mem_out[12]), - .Q_N(mem_outb[12])); + .Q(mem_out[12])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .CLK(prog_clk[0]), .D(mem_out[12]), - .Q(mem_out[13]), - .Q_N(mem_outb[13])); + .Q(mem_out[13])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .CLK(prog_clk[0]), .D(mem_out[13]), - .Q(mem_out[14]), - .Q_N(mem_outb[14])); + .Q(mem_out[14])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .CLK(prog_clk[0]), .D(mem_out[14]), - .Q(mem_out[15]), - .Q_N(mem_outb[15])); + .Q(mem_out[15])); - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .CLK(prog_clk[0]), .D(mem_out[15]), - .Q(mem_out[16]), - .Q_N(mem_outb[16])); + .Q(mem_out[16])); endmodule // @@ -948,11 +839,10 @@ endmodule // -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem(prog_clk, +module EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk, ccff_head, ccff_tail, - mem_out, - mem_outb); + mem_out); // input [0:0] prog_clk; // @@ -961,8 +851,6 @@ input [0:0] ccff_head; output [0:0] ccff_tail; // output [0:0] mem_out; -// -output [0:0] mem_outb; // // @@ -979,11 +867,10 @@ output [0:0] mem_outb; assign ccff_tail[0] = mem_out[0]; // - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( + sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .CLK(prog_clk[0]), .D(ccff_head[0]), - .Q(mem_out[0]), - .Q_N(mem_outb[0])); + .Q(mem_out[0])); endmodule // diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v index b710461..631f9c3 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_autocheck_top_tb.v @@ -813,10 +813,10 @@ initial prog_cycle_task(1'b0); prog_cycle_task(1'b0); prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); prog_cycle_task(1'b1); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); - prog_cycle_task(1'b0); prog_cycle_task(1'b1); prog_cycle_task(1'b0); prog_cycle_task(1'b0); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v index e4ba114..28aecd5 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v @@ -88,184 +88,184 @@ wire [0:0] ccff_tail; // `ifdef ICARUS_SIMULATOR // - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = 17'b00000000100010001; + assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = 17'b00000000110000001; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16] = {17{1'b0}}; + assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b0; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b0; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; + assign U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; assign U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b1}}; @@ -671,1761 +671,593 @@ wire [0:0] ccff_tail; assign U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; assign U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; -initial begin - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = 17'b11111111011101110; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = 2'b10; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16] = {17{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b1; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2] = 3'b110; - force U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_16.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2] = 3'b011; - force U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2] = 3'b001; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3] = 4'b1101; - force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_4.mem_outb[0:4] = {5{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_24.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_4.mem_outb[0:4] = {5{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3] = 4'b1001; - force U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4] = {5{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:4] = {5{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2] = 3'b110; - force U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_4.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_6.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_14.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_20.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_24.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_top_track_32.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_11.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_13.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_15.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3] = 4'b0010; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3] = 4'b1000; - force U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_outb[0:3] = {4{1'b1}}; -end // `else // initial begin - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_outb[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0:16], {17{1'b1}}); + $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); 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$deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem.mem_outb[0], 1'b0); + $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b0); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); + $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b001); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_outb[0:2], 3'b110); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], 3'b100); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_outb[0:2], 3'b011); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_10.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], 3'b110); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_outb[0:2], 3'b001); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], 4'b0010); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:3], 4'b1101); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_14.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_outb[0:1], {2{1'b0}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_4.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_4.mem_outb[0:4], {5{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_16.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_24.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_24.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_4.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_4.mem_outb[0:4], {5{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_16.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], 4'b0110); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_outb[0:3], 4'b1001); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_outb[0:4], {5{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:4], {5{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], 3'b001); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_outb[0:2], 3'b110); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_33.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_0.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_2.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_4.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_6.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_8.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_10.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_12.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_14.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_16.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_18.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_20.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_22.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_11.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_13.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_15.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_16.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_24.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_32.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_9.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_11.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_13.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_13.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_15.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_15.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_outb[0:2], {3{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_outb[0:1], {2{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3], 4'b1101); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_outb[0:3], 4'b0010); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b0}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], 4'b0111); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_outb[0:3], 4'b1000); $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_outb[0:3], {4{1'b1}}); $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_outb[0:3], {4{1'b1}}); end // `endif diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit index 3763705..cd6e31f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit @@ -1 +1 @@ -000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000 +000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000001100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000001000001000000000000000000000000000000000000000000000000001111000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111100100000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000000000110111111000001100001000000000001100000000000000000000 diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml index c8f2ad8..6b3467f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,7 +2,7 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Sun Nov 8 17:53:57 2020 + - Date: Mon Nov 9 18:01:58 2020 --> @@ -298,7 +298,7 @@ - + @@ -606,7 +606,7 @@ - + @@ -720,41 +720,41 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -772,39 +772,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -822,39 +822,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -872,39 +872,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -922,39 +922,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -972,39 +972,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1022,39 +1022,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1072,39 +1072,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1250,39 +1250,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1300,39 +1300,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1350,39 +1350,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1400,39 +1400,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1450,39 +1450,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1500,39 +1500,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1550,39 +1550,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1600,39 +1600,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -1786,7 +1786,7 @@ - + @@ -2644,41 +2644,41 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2696,39 +2696,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2746,39 +2746,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2796,39 +2796,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2846,39 +2846,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2896,39 +2896,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2946,39 +2946,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -2996,39 +2996,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3174,39 +3174,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3224,39 +3224,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3274,39 +3274,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3324,39 +3324,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3374,39 +3374,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3424,39 +3424,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3474,39 +3474,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3524,39 +3524,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3710,7 +3710,7 @@ - + @@ -3896,17 +3896,17 @@ - + - + - + - + - + - + @@ -4118,17 +4118,17 @@ - + - + - + - + - + - + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml index e9c2512..0eafa26 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Sun Nov 8 17:53:56 2020 + - Date: Mon Nov 9 18:01:58 2020 --> @@ -12,7 +12,7 @@ - + @@ -21,7 +21,7 @@ - + @@ -120,7 +120,7 @@ - + @@ -129,7 +129,7 @@ - + @@ -228,7 +228,7 @@ - + @@ -237,7 +237,7 @@ - + @@ -336,7 +336,7 @@ - + @@ -345,7 +345,7 @@ - + @@ -444,7 +444,7 @@ - + @@ -453,7 +453,7 @@ - + @@ -552,7 +552,7 @@ - + @@ -561,7 +561,7 @@ - + @@ -660,7 +660,7 @@ - + @@ -669,7 +669,7 @@ - + @@ -768,7 +768,7 @@ - + @@ -777,7 +777,7 @@ - + @@ -789,10 +789,10 @@ - + - + @@ -884,7 +884,7 @@ - + @@ -893,7 +893,7 @@ - + @@ -992,7 +992,7 @@ - + @@ -1001,7 +1001,7 @@ - + @@ -1100,7 +1100,7 @@ - + @@ -1109,7 +1109,7 @@ - + @@ -1208,7 +1208,7 @@ - + @@ -1217,7 +1217,7 @@ - + @@ -1316,7 +1316,7 @@ - + @@ -1325,7 +1325,7 @@ - + @@ -1424,7 +1424,7 @@ - + @@ -1433,7 +1433,7 @@ - + @@ -1532,7 +1532,7 @@ - + @@ -1541,7 +1541,7 @@ - + @@ -1640,7 +1640,7 @@ - + @@ -1649,7 +1649,7 @@ - + @@ -1752,7 +1752,7 @@ - + @@ -1761,7 +1761,7 @@ - + @@ -1860,7 +1860,7 @@ - + @@ -1869,7 +1869,7 @@ - + @@ -1968,7 +1968,7 @@ - + @@ -1977,7 +1977,7 @@ - + @@ -2076,7 +2076,7 @@ - + @@ -2085,7 +2085,7 @@ - + @@ -2184,7 +2184,7 @@ - + @@ -2193,7 +2193,7 @@ - + @@ -2292,7 +2292,7 @@ - + @@ -2301,7 +2301,7 @@ - + @@ -2400,7 +2400,7 @@ - + @@ -2409,7 +2409,7 @@ - + @@ -2508,7 +2508,7 @@ - + @@ -2517,7 +2517,7 @@ - + @@ -2620,7 +2620,7 @@ - + @@ -2629,7 +2629,7 @@ - + @@ -2728,7 +2728,7 @@ - + @@ -2737,7 +2737,7 @@ - + @@ -2836,7 +2836,7 @@ - + @@ -2845,7 +2845,7 @@ - + @@ -2944,7 +2944,7 @@ - + @@ -2953,7 +2953,7 @@ - + @@ -3052,7 +3052,7 @@ - + @@ -3061,7 +3061,7 @@ - + @@ -3160,7 +3160,7 @@ - + @@ -3169,7 +3169,7 @@ - + @@ -3268,7 +3268,7 @@ - + @@ -3277,7 +3277,7 @@ - + @@ -3376,7 +3376,7 @@ - + @@ -3385,7 +3385,7 @@ - + @@ -3485,13 +3485,13 @@ - + - + @@ -3503,13 +3503,13 @@ - + - + @@ -3521,13 +3521,13 @@ - + - + @@ -3539,13 +3539,13 @@ - + - + @@ -3557,13 +3557,13 @@ - + - + @@ -3573,13 +3573,13 @@ - + - + @@ -3589,13 +3589,13 @@ - + - + @@ -3605,13 +3605,13 @@ - + - + @@ -3621,13 +3621,13 @@ - + - + @@ -3637,13 +3637,13 @@ - + - + @@ -3655,13 +3655,13 @@ - + - + @@ -3671,13 +3671,13 @@ - + - + @@ -3687,13 +3687,13 @@ - + - + @@ -3703,13 +3703,13 @@ - + - + @@ -3719,13 +3719,13 @@ - + - + @@ -3735,13 +3735,13 @@ - + - + @@ -3753,13 +3753,13 @@ - + - + @@ -3771,13 +3771,13 @@ - + - + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log index 2eed1b2..c8e7269 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log @@ -41,9 +41,9 @@ THE SOFTWARE. Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off VPR FPGA Placement and Routing. -Version: 0.0.0+55f7a2c1 -Revision: 55f7a2c1 -Compiled: 2020-11-05T12:41:40 +Version: 0.0.0+520e54d7 +Revision: 520e54d7 +Compiled: 2020-11-09T18:01:05 Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 Build Info: release VTR_ASSERT_LEVEL=2 @@ -65,25 +65,25 @@ Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -# Loading Architecture Description took 0.00 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB) +# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB) # Building complex block graph -Warning 6: [LINE 582] false logically-equivalent pin clb[0].I0[1]. -Warning 7: [LINE 582] false logically-equivalent pin clb[0].I0[2]. -Warning 8: [LINE 588] false logically-equivalent pin clb[0].I1[1]. -Warning 9: [LINE 588] false logically-equivalent pin clb[0].I1[2]. -Warning 10: [LINE 594] false logically-equivalent pin clb[0].I2[1]. -Warning 11: [LINE 594] false logically-equivalent pin clb[0].I2[2]. -Warning 12: [LINE 600] false logically-equivalent pin clb[0].I3[1]. -Warning 13: [LINE 600] false logically-equivalent pin clb[0].I3[2]. -Warning 14: [LINE 606] false logically-equivalent pin clb[0].I4[1]. -Warning 15: [LINE 606] false logically-equivalent pin clb[0].I4[2]. -Warning 16: [LINE 612] false logically-equivalent pin clb[0].I5[1]. -Warning 17: [LINE 612] false logically-equivalent pin clb[0].I5[2]. -Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1]. -Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2]. -Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1]. -Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2]. -# Building complex block graph took 0.00 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) +Warning 6: [LINE 586] false logically-equivalent pin clb[0].I0[1]. +Warning 7: [LINE 586] false logically-equivalent pin clb[0].I0[2]. +Warning 8: [LINE 592] false logically-equivalent pin clb[0].I1[1]. +Warning 9: [LINE 592] false logically-equivalent pin clb[0].I1[2]. +Warning 10: [LINE 598] false logically-equivalent pin clb[0].I2[1]. +Warning 11: [LINE 598] false logically-equivalent pin clb[0].I2[2]. +Warning 12: [LINE 604] false logically-equivalent pin clb[0].I3[1]. +Warning 13: [LINE 604] false logically-equivalent pin clb[0].I3[2]. +Warning 14: [LINE 610] false logically-equivalent pin clb[0].I4[1]. +Warning 15: [LINE 610] false logically-equivalent pin clb[0].I4[2]. +Warning 16: [LINE 616] false logically-equivalent pin clb[0].I5[1]. +Warning 17: [LINE 616] false logically-equivalent pin clb[0].I5[2]. +Warning 18: [LINE 622] false logically-equivalent pin clb[0].I6[1]. +Warning 19: [LINE 622] false logically-equivalent pin clb[0].I6[2]. +Warning 20: [LINE 628] false logically-equivalent pin clb[0].I7[1]. +Warning 21: [LINE 628] false logically-equivalent pin clb[0].I7[2]. +# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) # Load circuit # Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) # Clean circuit @@ -250,12 +250,12 @@ Device Utilization: 0.25 (target 1.00) Netlist conversion complete. -# Packing took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) +# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0 seconds). +Finished loading packed FPGA netlist file (took 0.01 seconds). Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) Warning 35: Netlist contains 0 global net to non-global architecture pin connections @@ -301,7 +301,7 @@ Device Utilization: 0.25 (target 1.00) Physical Tile clb: Block Utilization: 0.25 Logical Block: clb -## Build Device Grid took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB) ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 @@ -309,10 +309,10 @@ Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) RR Graph Nodes: 756 RR Graph Edges: 2930 -# Create Device took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) # Placement ## Computing placement delta delay look-up @@ -321,12 +321,12 @@ Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pi Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -### Build routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB) RR Graph Nodes: 756 RR Graph Edges: 2428 ### Computing delta delays -### Computing delta delays took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) -## Computing placement delta delay look-up took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB) +## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB) There are 3 point to point connections in this circuit. @@ -440,7 +440,7 @@ Placement total # of swap attempts: 292 Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB) # Routing ## Build tileable routing resource graph @@ -450,7 +450,7 @@ Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB) RR Graph Nodes: 756 RR Graph Edges: 2930 Confirming router algorithm: TIMING_DRIVEN. @@ -464,7 +464,7 @@ Restoring best routing Critical path: 0.86731 ns Successfully routed after 2 routing iterations. Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187 -# Routing took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. @@ -562,9 +562,9 @@ Setup slack histogram: [ -8.7e-10: -8.7e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -Timing analysis took 0.000351611 seconds (0.000312774 STA, 3.8837e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). +Timing analysis took 0.000405567 seconds (0.000363868 STA, 4.1699e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). VPR suceeded -The entire flow of VPR took 0.07 seconds (max_rss 12.7 MiB) +The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -574,14 +574,14 @@ Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/IC Read OpenFPGA architecture Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type. Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type. -Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type. -Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') -Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') -Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') -Read OpenFPGA architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxtp_1' to be default in its type. +Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree_tapbuf' port 'sram') +Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'frac_lut4' port 'sram') +Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB) Check circuit library Checking circuit library passed. -Check circuit library took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Found 0 errors when checking configurable memory circuit models! Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml @@ -590,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Read OpenFPGA simulation settings -Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges @@ -633,7 +633,7 @@ Done with 18 nodes mapping [88%] Backannotated GSB[2][1] [100%] Backannotated GSB[2][2] Backannotated 9 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [11%] Sorted edges for GSB[0][0] [22%] Sorted edges for GSB[0][1] @@ -645,14 +645,14 @@ Backannotated 9 General Switch Blocks (GSBs). [88%] Sorted edges for GSB[2][1] [100%] Sorted edges for GSB[2][2] Sorted edges for 9 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) # Build a library of physical multiplexers Built a multiplexer library of 15 physical multiplexers. Maximum multiplexer size is 17. -# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) # Build the annotation about direct connection between tiles Built 6 tile-to-tile direct connections -# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) Building annotation for mapped blocks on grid locations...Done User specified the operating clock frequency to use VPR results Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA. @@ -662,7 +662,7 @@ Average net density: 0.42 Median net density: 0.00 Average net density after weighting: 0.42 Will apply 2 operating clock cycles to simulations -Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB) Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml @@ -676,7 +676,7 @@ Confirm selected options when call command 'build_fabric': --verbose: off Identify unique General Switch Blocks (GSBs) Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%) -Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) Read Fabric Key Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) @@ -691,7 +691,7 @@ Build fabric module graph # Build local encoder (for multiplexers) modules # Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Building multiplexer modules -# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.2 MiB) +# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) # Build Look-Up Table (LUT) modules # Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB) # Build wire modules @@ -703,41 +703,41 @@ Building logical tiles...Done Building physical tiles...Done # Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB) # Build unique routing modules... -# Build unique routing modules... took 0.01 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB) +# Build unique routing modules... took 0.02 seconds (max_rss 15.8 MiB, delta_rss +2.1 MiB) # Build FPGA fabric module ## Add grid instances to top module -## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) +## Add grid instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) ## Add switch block instances to top module -## Add switch block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) +## Add switch block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 16.0 MiB, delta_rss +0.3 MiB) ## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.5 MiB) +## Add module nets between grids and GSBs took 0.01 seconds (max_rss 16.5 MiB, delta_rss +0.5 MiB) ## Add module nets for inter-tile connections -## Add module nets for inter-tile connections took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) +## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) ## Add module nets for configuration buses -## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) -# Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB) -Build fabric module graph took 0.02 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB) +## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.3 MiB) +# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +1.0 MiB) +Build fabric module graph took 0.03 seconds (max_rss 16.8 MiB, delta_rss +4.1 MiB) Create I/O location mapping for top module -Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) +Create I/O location mapping for top module took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.0 MiB) Command line to execute: repack Confirm selected options when call command 'repack': --verbose: off Build routing resource graph for the physical implementation of logical tile -Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB) +Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.3 MiB) Repack clustered blocks to physical implementation of logical tile Repack clustered block 'c'...Done Repack clustered block 'out:c'...Done Repack clustered block 'a'...Done Repack clustered block 'b'...Done -Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB) +Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) Build truth tables for physical LUTs -Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.3 MiB) +Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml @@ -753,10 +753,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) + took 0.01 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) Warning 56: Directory path is empty and nothing will be created. Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) Command line to execute: build_fabric_bitstream @@ -767,7 +767,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.3 MiB) + took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -777,7 +777,7 @@ Confirm selected options when call command 'write_fabric_bitstream': --verbose: off Warning 57: Directory path is empty and nothing will be created. Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml @@ -787,7 +787,7 @@ Confirm selected options when call command 'write_fabric_bitstream': --verbose: off Warning 58: Directory path is empty and nothing will be created. Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) +Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose @@ -849,7 +849,7 @@ Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Written 73 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.17 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB) + took 0.19 seconds (max_rss 17.7 MiB, delta_rss +0.4 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping @@ -869,17 +869,17 @@ Write Verilog testbenches for FPGA fabric Warning 60: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' Will use 2107 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 0.03 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) + took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB) Command line to execute: exit @@ -887,6 +887,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 0.19 seconds +The entire OpenFPGA flow took 0.25 seconds Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml index 5b8d71e..1d3208c 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml @@ -171,16 +171,15 @@ - + - + - @@ -192,11 +191,11 @@ - + - + diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml index 843bc0f..62a7869 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml @@ -579,49 +579,53 @@ - + + - + - + - + - + - + - + - + diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png index 3ffeb3c..410b7dc 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png index c65d9cd..239f024 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png index b83058e..c1ea5e4 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png index d462a17..bba0820 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/clockTree.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png index b81da41..2273b42 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met1_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png index 939dc56..f967644 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met2_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png index 7cedf4b..ab4d433 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met3_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png index 1db309e..0bddda4 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/met4_utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png index ec010c9..ce2f53a 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png index fae9f14..e370106 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v index 2e6c6ec..eec69c9 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v @@ -60,19 +60,20 @@ output [0:0] out ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -87,21 +88,12 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -wire aps_rename_1_ ; - assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -127,10 +119,9 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -166,168 +157,160 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -454,12 +437,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -479,10 +459,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -742,189 +721,180 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1470,8 +1440,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - prog_clk__FEEDTHRU_1 ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1502,26 +1471,34 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1531,21 +1508,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1561,229 +1530,212 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -1791,280 +1743,275 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2088,12 +2035,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2113,10 +2057,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -2190,12 +2133,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2215,10 +2155,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -2394,9 +2333,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2416,9 +2358,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -2474,171 +2417,163 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3122,9 +3057,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3150,25 +3083,31 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -3177,21 +3116,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -3201,350 +3132,335 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) ) ; endmodule @@ -3556,19 +3472,18 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3592,9 +3507,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -3622,10 +3540,9 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -3661,21 +3578,20 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3706,6 +3622,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -3735,8 +3653,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -3745,7 +3661,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3760,11 +3676,10 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , @@ -3772,230 +3687,222 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) ) ; endmodule @@ -4013,19 +3920,18 @@ output [0:0] out ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4040,12 +3946,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_1_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -4071,10 +3981,9 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -4110,169 +4019,161 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4602,9 +4503,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -4624,9 +4528,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -4682,190 +4587,181 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5249,6 +5145,65 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -5283,61 +5238,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module cbx_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule @@ -5408,7 +5308,7 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -5443,26 +5343,36 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -5472,21 +5382,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -5504,541 +5406,530 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) ) ; + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6165,9 +6056,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -6187,9 +6081,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -6420,6 +6315,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -6443,174 +6340,166 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6932,9 +6821,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6960,9 +6852,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -7050,6 +6943,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -7079,8 +6974,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7122,22 +7015,30 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -7146,21 +7047,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -7178,399 +7071,374 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) ) ; + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) ) ; endmodule -module cbx_1__0__direct_interc_5 ( in , out ) ; +module cbx_1__0__direct_interc_3 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7588,11 +7456,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -7618,10 +7484,9 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7647,7 +7512,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__io .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_5 direct_interc_0_ ( +cbx_1__0__direct_interc_3 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( @@ -7656,24 +7521,23 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__direct_interc_4 ( in , out ) ; +module cbx_1__0__direct_interc_2 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7690,8 +7554,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -7717,11 +7582,9 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7745,36 +7608,34 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_4 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_3 ( in , out ) ; +module cbx_1__0__direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7788,11 +7649,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_3_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) ) ; endmodule @@ -7818,11 +7684,9 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7846,41 +7710,33 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7888,19 +7744,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7910,6 +7768,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -7918,12 +7777,11 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7947,36 +7805,34 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7993,9 +7849,8 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -8021,11 +7876,9 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -8049,14 +7902,13 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_0 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule @@ -8069,29 +7921,22 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -8099,19 +7944,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -8121,6 +7968,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -8129,12 +7977,11 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -8158,139 +8005,132 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8317,12 +8157,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -8348,10 +8185,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -8661,7 +8497,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -8701,34 +8537,37 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -8736,437 +8575,448 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , + .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , + .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , + .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , + .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , + .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9266,408 +9116,386 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10199,13 +10027,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -10303,87 +10135,87 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10444,12 +10276,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10460,10 +10289,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -10483,12 +10311,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10499,10 +10324,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -10526,6 +10350,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10540,84 +10366,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10769,9 +10587,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10785,9 +10606,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule @@ -10832,54 +10654,65 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -10904,34 +10737,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -10944,546 +10766,502 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11560,13 +11338,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11641,96 +11419,91 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11886,82 +11659,78 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12021,8 +11790,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12034,6 +11801,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) ) ; endmodule @@ -12091,6 +11862,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12102,27 +11875,24 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12152,8 +11922,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sb_2__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12180,61 +11948,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12347,6 +12114,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12364,139 +12133,130 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12524,6 +12284,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12544,8 +12306,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12571,6 +12331,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12591,8 +12353,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12665,6 +12425,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12685,8 +12447,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12755,9 +12515,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12774,9 +12537,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -12828,42 +12592,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13020,63 +12782,60 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13105,6 +12864,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_2__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -13128,8 +12889,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13236,42 +12995,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13302,6 +13059,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -13331,8 +13090,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13408,7 +13165,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -13446,86 +13204,92 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -13534,86 +13298,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -13622,8 +13377,8 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -13632,587 +13387,538 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) ) ; + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) ) ; + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) ) ; + .X ( ropt_net_144 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14342,6 +14048,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -14353,348 +14061,328 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14713,17 +14401,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -14740,13 +14424,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -14767,13 +14455,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -14794,13 +14482,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -14817,17 +14505,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -14848,13 +14532,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -14871,17 +14555,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -14925,13 +14605,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -14948,13 +14628,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -14975,13 +14659,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15002,13 +14686,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15229,34 +14913,32 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15325,38 +15007,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15441,38 +15121,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15595,46 +15273,56 @@ output [0:19] chany_top_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -15655,33 +15343,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; @@ -15690,465 +15368,399 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16197,18 +15809,17 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16230,114 +15841,108 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_1__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16360,6 +15965,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -16368,8 +15975,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16449,20 +16054,16 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -16480,20 +16081,16 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -16529,58 +16126,55 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16604,8 +16198,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -16617,6 +16209,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16674,8 +16268,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -16687,24 +16279,25 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16749,153 +16342,145 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17059,6 +16644,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; @@ -17080,7 +16666,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -17196,12 +16785,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17218,10 +16804,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -17273,43 +16858,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17417,43 +17000,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17609,64 +17190,61 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17837,22 +17415,21 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17931,9 +17508,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , + clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -17973,33 +17550,55 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -18007,35 +17606,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -18045,22 +17631,19 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -18069,55 +17652,51 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -18127,8 +17706,8 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -18137,545 +17716,528 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18840,9 +18402,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18859,259 +18424,248 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19826,92 +19380,88 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -19935,7 +19485,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -19991,12 +19540,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; endmodule @@ -20078,8 +19624,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) ) ; endmodule @@ -20197,6 +19745,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -20244,174 +19794,164 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20511,8 +20051,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20548,6 +20086,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -20970,7 +20510,8 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -21019,33 +20560,51 @@ output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -21059,21 +20618,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -21083,29 +20634,23 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -21113,7 +20658,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , @@ -21122,8 +20667,8 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -21131,8 +20676,8 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -21140,8 +20685,8 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -21149,8 +20694,8 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -21158,8 +20703,8 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -21167,8 +20712,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -21176,54 +20722,46 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -21233,9 +20771,8 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -21245,8 +20782,8 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -21256,9 +20793,8 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -21268,39 +20804,34 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , @@ -21308,508 +20839,488 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21893,39 +21404,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22017,43 +21526,41 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22147,6 +21654,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22179,24 +21688,21 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22229,120 +21735,113 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22565,39 +22064,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22673,172 +22170,163 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23002,12 +22490,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -23024,10 +22509,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -23267,64 +22751,61 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23493,11 +22974,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -23533,38 +23010,48 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -23573,40 +23060,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -23617,19 +23089,14 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , @@ -23637,271 +23104,249 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -23909,9 +23354,8 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -23919,565 +23363,508 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24604,13 +23991,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -24658,13 +24049,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24681,17 +24072,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -24735,17 +24122,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -24874,13 +24257,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24966,34 +24349,32 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25062,38 +24443,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25178,38 +24557,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25330,42 +24707,48 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -25384,21 +24767,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; @@ -25409,474 +24786,427 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25972,13 +25302,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -26026,98 +25360,93 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26279,57 +25608,54 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26477,133 +25803,126 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26628,6 +25947,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26639,8 +25960,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26663,8 +25982,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26676,6 +25993,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26768,8 +26087,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26781,6 +26098,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26838,8 +26157,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26851,99 +26168,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27125,8 +26439,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27141,137 +26453,134 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27341,8 +26650,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27360,6 +26667,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; endmodule @@ -27427,6 +26738,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27444,10 +26757,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) ) ; endmodule @@ -27468,12 +26777,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27487,10 +26793,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -27608,18 +26913,45 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -27627,33 +26959,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -27662,34 +26982,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -27698,11 +27006,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -27711,613 +27016,556 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28443,9 +27691,12 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -28453,281 +27704,266 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28750,13 +27986,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28777,13 +28013,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28804,13 +28040,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28827,17 +28063,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -28939,13 +28171,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28966,13 +28198,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28993,13 +28225,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -29047,13 +28279,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -29185,38 +28417,42 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:0] ccff_tail ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -29233,13 +28469,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -29248,378 +28480,283 @@ wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) ) ; -endmodule - - -module grid_clb_direct_interc_17 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_16 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_15 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_14 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_13 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_12 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) ) ; endmodule @@ -29647,53 +28784,70 @@ output [0:0] out ; endmodule +module grid_clb_direct_interc_7 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_6 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , + .X ( net_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29727,12 +28881,13 @@ endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -29742,11 +28897,9 @@ grid_clb_const1_30 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , - .X ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , - .X ( p_abuf0 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -29771,8 +28924,8 @@ grid_clb_const1_29 const1_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -29792,12 +28945,9 @@ output p_abuf2 ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , - .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; endmodule @@ -29817,18 +28967,17 @@ endmodule module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29856,49 +29005,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29939,7 +29087,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -30024,13 +29172,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , @@ -30053,16 +29201,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -30070,16 +29219,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -30095,8 +29235,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -30113,12 +29253,11 @@ grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -30140,7 +29279,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30157,19 +29297,20 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -30192,7 +29333,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( fabric_regout[0] ) , + .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { @@ -30200,36 +29341,34 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; @@ -30271,7 +29410,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p_abuf4 , p0 ) ; + p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30288,7 +29427,8 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -30298,20 +29438,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , - .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , + .p_abuf6 ( p_abuf6 ) , .p0 ( p0 ) ) ; +grid_clb_direct_interc_5 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc_8 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[0] ) ) ; @@ -30336,59 +29476,56 @@ grid_clb_direct_interc direct_interc_10_ ( endmodule -module grid_clb_direct_interc_7 ( in , out ) ; +module grid_clb_direct_interc_4 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30398,12 +29535,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30411,7 +29548,7 @@ grid_clb_const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -30422,6 +29559,35 @@ endmodule module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , + .X ( BUF_net_89 ) ) ; +endmodule + + +module grid_clb_const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -30433,40 +29599,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -grid_clb_const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - grid_clb_const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -30501,17 +29641,16 @@ endmodule module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30522,12 +29661,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -30535,54 +29674,53 @@ grid_clb_const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30620,10 +29758,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -30712,9 +29850,9 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , @@ -30737,16 +29875,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -30754,33 +29893,24 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -30797,12 +29927,11 @@ grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -30824,7 +29953,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30838,20 +29967,21 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -30862,7 +29992,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -30880,36 +30010,34 @@ grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -30950,7 +30078,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30964,9 +30093,10 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -30974,14 +30104,14 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_direct_interc_7 direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf3 } ) ) ; + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc_4 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_regout ) ) ; @@ -31012,64 +30142,55 @@ grid_clb_direct_interc direct_interc_10_ ( endmodule -module grid_clb_direct_interc_6 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_5 ( in , out ) ; +module grid_clb_direct_interc_3 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31118,9 +30239,9 @@ grid_clb_const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -31130,12 +30251,13 @@ endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31144,9 +30266,10 @@ grid_clb_const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -31181,17 +30304,16 @@ endmodule module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31220,48 +30342,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31296,17 +30417,17 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( @@ -31417,16 +30538,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -31434,16 +30556,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -31459,8 +30572,8 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -31477,12 +30590,11 @@ grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -31504,7 +30616,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31518,19 +30630,20 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -31559,36 +30672,34 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -31629,7 +30740,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31643,6 +30754,7 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; @@ -31652,97 +30764,94 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p3 ( p3 ) ) ; -grid_clb_direct_interc_5 direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc_6 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule -module grid_clb_direct_interc_4 ( in , out ) ; +module grid_clb_direct_interc_2 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31752,12 +30861,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -31765,7 +30874,7 @@ grid_clb_const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -31793,8 +30902,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -31820,7 +30929,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -31855,17 +30964,16 @@ endmodule module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31894,49 +31002,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32062,13 +31169,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -32091,16 +31198,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -32108,16 +31216,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -32133,8 +31232,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -32151,12 +31250,11 @@ grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -32200,13 +31298,13 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -32235,36 +31333,34 @@ grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -32333,7 +31429,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc_4 direct_interc_0_ ( +grid_clb_direct_interc_2 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( @@ -32369,59 +31465,56 @@ grid_clb_direct_interc direct_interc_10_ ( endmodule -module grid_clb_direct_interc_3 ( in , out ) ; +module grid_clb_direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32455,32 +31548,6 @@ endmodule module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; @@ -32492,14 +31559,39 @@ input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -grid_clb_const1_13 const1_0_ ( +grid_clb_const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -32534,17 +31626,16 @@ endmodule module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32573,48 +31664,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -32647,22 +31737,22 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -32745,7 +31835,7 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -32770,16 +31860,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -32787,16 +31878,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -32812,8 +31894,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -32830,12 +31912,11 @@ grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -32857,7 +31938,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32871,20 +31952,20 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -32913,36 +31994,34 @@ grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -32983,7 +32062,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32997,8 +32076,8 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -33007,14 +32086,14 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc_1 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc_3 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_regout ) ) ; @@ -33045,59 +32124,50 @@ grid_clb_direct_interc direct_interc_10_ ( endmodule -module grid_clb_direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -33130,13 +32200,15 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +output p_abuf1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -33144,9 +32216,10 @@ grid_clb_const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -33156,14 +32229,14 @@ endmodule module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; + p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -33171,10 +32244,10 @@ grid_clb_const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -33209,17 +32282,16 @@ endmodule module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -33230,12 +32302,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -33243,53 +32315,52 @@ grid_clb_const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -33322,11 +32393,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -33416,13 +32487,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , @@ -33445,16 +32516,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -33462,33 +32534,24 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -33505,12 +32568,11 @@ grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -33532,7 +32594,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33548,19 +32610,19 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -33571,7 +32633,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -33589,36 +32651,35 @@ grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -33659,8 +32720,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p2 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33676,7 +32737,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -33686,49 +32747,43 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc_2 direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule -module grid_clb_direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - module grid_clb_direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -33736,52 +32791,49 @@ endmodule module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -33830,7 +32882,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -33839,12 +32891,14 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -33853,9 +32907,10 @@ grid_clb_const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -33890,17 +32945,16 @@ endmodule module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -33929,49 +32983,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34005,7 +33058,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; @@ -34126,16 +33179,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -34143,16 +33197,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -34168,8 +33213,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -34186,12 +33231,11 @@ grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -34213,7 +33257,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -34227,6 +33271,7 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -34234,13 +33279,13 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -34269,36 +33314,34 @@ grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -34339,7 +33382,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -34353,6 +33397,7 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -34363,90 +33408,87 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc_0 direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc_0 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34457,12 +33499,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -34470,7 +33512,7 @@ grid_clb_const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -34480,13 +33522,15 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +output p_abuf1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -34494,9 +33538,10 @@ grid_clb_const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -34506,14 +33551,14 @@ endmodule module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p4 ) ; + p_abuf1 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; output p_abuf1 ; -input p4 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -34521,10 +33566,13 @@ grid_clb_const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , + .X ( p_abuf0 ) ) ; endmodule @@ -34567,17 +33615,16 @@ endmodule module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34606,49 +33653,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34689,7 +33735,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -34803,16 +33849,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -34820,16 +33867,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -34845,8 +33883,8 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -34863,12 +33901,11 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -34890,7 +33927,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -34906,19 +33943,20 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -34947,36 +33985,35 @@ grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -35017,8 +34054,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , - p4 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -35034,8 +34071,9 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -35044,13 +34082,13 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; @@ -35086,9 +34124,9 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , - p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , p_abuf18 , - p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , p_abuf30 , - p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; + p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , p_abuf19 , + p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , p_abuf31 , + p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -35119,26 +34157,25 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf3 ; output p_abuf5 ; -output p_abuf6 ; -output p_abuf8 ; -output p_abuf10 ; -output p_abuf12 ; -output p_abuf14 ; -output p_abuf16 ; -output p_abuf18 ; -output p_abuf20 ; -output p_abuf22 ; -output p_abuf24 ; -output p_abuf26 ; -output p_abuf28 ; -output p_abuf30 ; +output p_abuf7 ; +output p_abuf9 ; +output p_abuf11 ; +output p_abuf13 ; +output p_abuf15 ; +output p_abuf17 ; +output p_abuf19 ; +output p_abuf21 ; +output p_abuf23 ; +output p_abuf25 ; +output p_abuf27 ; +output p_abuf29 ; output p_abuf31 ; +output p_abuf33 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; -input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -35164,7 +34201,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , @@ -35172,10 +34209,10 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , - .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf3 ( p_abuf6 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35184,10 +34221,11 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf6 ) , .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , + .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35196,11 +34234,11 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , - .p0 ( p0 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , + .p_abuf3 ( p_abuf14 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35209,11 +34247,11 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf14 ) , .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , + .p_abuf0 ( p_abuf15 ) , .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35222,11 +34260,11 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf18 ) , .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , + .p_abuf0 ( p_abuf19 ) , .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35235,10 +34273,11 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf22 ) , .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf23 ) , .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , + .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35247,11 +34286,11 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf26 ) , .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , - .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf27 ) , .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , + .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -35259,229 +34298,229 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , - .p0 ( p1 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , + .p_abuf6 ( p_abuf34 ) , .p0 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf5 } ) ) ; + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc_9 direct_interc_2_ ( +grid_clb_direct_interc_6 direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; -grid_clb_direct_interc_10 direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { SYNOPSYS_UNCONNECTED_6 } ) ) ; -grid_clb_direct_interc_11 direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; + .out ( { p_abuf8 } ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf14 } ) ) ; grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( { p_abuf12 } ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( { p_abuf18 } ) ) ; +grid_clb_direct_interc_7 direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { p_abuf11 } ) ) ; -grid_clb_direct_interc_12 direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( { SYNOPSYS_UNCONNECTED_11 } ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { p_abuf15 } ) ) ; + .out ( { SYNOPSYS_UNCONNECTED_10 } ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( { p_abuf21 } ) ) ; -grid_clb_direct_interc_13 direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( { p_abuf22 } ) ) ; +grid_clb_direct_interc_8 direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; +grid_clb_direct_interc_9 direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_14 } ) , .out ( { SYNOPSYS_UNCONNECTED_15 } ) ) ; -grid_clb_direct_interc_14 direct_interc_10_ ( +grid_clb_direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { SYNOPSYS_UNCONNECTED_17 } ) ) ; -grid_clb_direct_interc_15 direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( { SYNOPSYS_UNCONNECTED_19 } ) ) ; -grid_clb_direct_interc direct_interc_12_ ( + .out ( { p_abuf24 } ) ) ; +grid_clb_direct_interc_10 direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , + .out ( { SYNOPSYS_UNCONNECTED_18 } ) ) ; +grid_clb_direct_interc direct_interc_13_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , + .out ( { p_abuf28 } ) ) ; +grid_clb_direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_20 } ) , - .out ( { p_abuf29 } ) ) ; -grid_clb_direct_interc_16 direct_interc_13_ ( + .out ( { p_abuf34 } ) ) ; +grid_clb_direct_interc_11 direct_interc_15_ ( .in ( { SYNOPSYS_UNCONNECTED_21 } ) , .out ( { SYNOPSYS_UNCONNECTED_22 } ) ) ; -grid_clb_direct_interc_17 direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , - .out ( { SYNOPSYS_UNCONNECTED_24 } ) ) ; -grid_clb_direct_interc direct_interc_15_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , - .out ( { p_abuf30 } ) ) ; grid_clb_direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , + .out ( { p_abuf2 } ) ) ; grid_clb_direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I0[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .out ( clb_I0[0] ) ) ; grid_clb_direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , .out ( clb_I0[1] ) ) ; grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , - .out ( clb_I0[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I0[2] ) ) ; grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , .out ( clb_I0i ) ) ; grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , .out ( clb_regin ) ) ; grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( clb_sc_in ) ) ; grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I1[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .out ( clb_I1[0] ) ) ; grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , .out ( clb_I1[1] ) ) ; grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , - .out ( clb_I1[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I1[2] ) ) ; grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , .out ( clb_I1i ) ) ; grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I2[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .out ( clb_I2[0] ) ) ; grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , .out ( clb_I2[1] ) ) ; grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , - .out ( clb_I2[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I2[2] ) ) ; grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , .out ( clb_I2i ) ) ; grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I3[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .out ( clb_I3[0] ) ) ; grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , .out ( clb_I3[1] ) ) ; grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , - .out ( clb_I3[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I3[2] ) ) ; grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , .out ( clb_I3i ) ) ; grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I4[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .out ( clb_I4[0] ) ) ; grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , .out ( clb_I4[1] ) ) ; grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( clb_I4[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I4[2] ) ) ; grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , .out ( clb_I4i ) ) ; grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I5[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .out ( clb_I5[0] ) ) ; grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , .out ( clb_I5[1] ) ) ; grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , - .out ( clb_I5[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I5[2] ) ) ; grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , .out ( clb_I5i ) ) ; grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_69 } ) , + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I6[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , + .out ( clb_I6[0] ) ) ; grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_71 } ) , + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , .out ( clb_I6[1] ) ) ; grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_72 } ) , - .out ( clb_I6[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_69 } ) , + .out ( clb_I6[2] ) ) ; grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_73 } ) , + .in ( { SYNOPSYS_UNCONNECTED_70 } ) , .out ( clb_I6i ) ) ; grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .in ( { SYNOPSYS_UNCONNECTED_71 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_75 } ) , + .in ( { SYNOPSYS_UNCONNECTED_72 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_76 } ) , + .in ( { SYNOPSYS_UNCONNECTED_73 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_77 } ) , - .out ( clb_I7[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .out ( clb_I7[0] ) ) ; grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_78 } ) , + .in ( { SYNOPSYS_UNCONNECTED_75 } ) , .out ( clb_I7[1] ) ) ; grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_79 } ) , - .out ( clb_I7[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_76 } ) , + .out ( clb_I7[2] ) ) ; grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_80 } ) , + .in ( { SYNOPSYS_UNCONNECTED_77 } ) , .out ( clb_I7i ) ) ; grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_81 } ) , + .in ( { SYNOPSYS_UNCONNECTED_78 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_82 } ) , + .in ( { SYNOPSYS_UNCONNECTED_79 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_83 } ) , + .in ( { SYNOPSYS_UNCONNECTED_80 } ) , .out ( clb_clk ) ) ; endmodule @@ -35531,7 +34570,8 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -35613,21 +34653,24 @@ output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] prog_clk__FEEDTHRU_4 ; output [0:0] Test_en__FEEDTHRU_1 ; output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf2 ; +wire ropt_net_156 ; +wire ropt_net_153 ; +wire ropt_net_151 ; wire ropt_net_150 ; -wire ropt_net_141 ; -wire ropt_net_139 ; -wire ropt_net_144 ; -wire ropt_net_140 ; -wire p_abuf15 ; -wire ropt_net_147 ; +wire ropt_net_167 ; +wire ropt_net_154 ; +wire ropt_net_168 ; +wire ropt_net_152 ; +wire ropt_net_163 ; +wire ropt_net_162 ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; +assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -35662,142 +34705,147 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , aps_rename_136_ , - top_width_0_height_0__pin_36_lower[0] , - top_width_0_height_0__pin_37_lower[0] , - top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , - top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , - aps_rename_144_ , aps_rename_145_ , - right_width_0_height_0__pin_44_lower[0] , - right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , - .clb_regout ( { ropt_net_153 } ) , - .clb_sc_out ( { aps_rename_155_ } ) , - .ccff_tail ( { ropt_net_149 } ) , - .p_abuf0 ( ropt_net_147 ) , .p_abuf3 ( ropt_net_150 ) , - .p_abuf5 ( p_abuf2 ) , - .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , - .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf10 ( ropt_net_141 ) , - .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , - .p_abuf14 ( ropt_net_139 ) , - .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf18 ( ropt_net_144 ) , - .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , - .p_abuf26 ( ropt_net_140 ) , - .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf30 ( p_abuf15 ) , - .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , - .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , - .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; + .clb_O ( { aps_rename_138_ , aps_rename_139_ , + top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , + aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , + top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , + aps_rename_158_ } ) , + .clb_regout ( { ropt_net_161 } ) , + .clb_sc_out ( { aps_rename_160_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_162 ) , + .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , + .p_abuf7 ( ropt_net_156 ) , + .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , + .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , + .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , + .p_abuf27 ( ropt_net_152 ) , + .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , + .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , + .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , + .p4 ( optlc_net_141 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , - .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1134 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_5138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , - .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , - .X ( aps_rename_154_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , - .X ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , - .X ( clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , - .X ( BUF_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , - .X ( prog_clk__FEEDTHRU_3[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , + .X ( aps_rename_143_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_6147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , + .X ( aps_rename_155_ ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , + .X ( clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , - .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , + .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , + .X ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , + .X ( prog_clk__FEEDTHRU_4[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; endmodule @@ -36229,7 +35277,6 @@ wire [0:0] prog_clk__FEEDTHRU_16 ; wire [0:0] prog_clk__FEEDTHRU_17 ; wire [0:0] prog_clk__FEEDTHRU_18 ; wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] prog_clk__FEEDTHRU_20 ; wire [0:0] Test_en__FEEDTHRU_1 ; wire [0:0] Test_en__FEEDTHRU_2 ; wire [0:0] Test_en__FEEDTHRU_3 ; @@ -36240,15 +35287,14 @@ wire [0:0] clk__FEEDTHRU_1 ; wire [0:0] clk__FEEDTHRU_2 ; wire [0:0] clk__FEEDTHRU_3 ; wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] clk__FEEDTHRU_5 ; +wire [0:0] clk__FEEDTHRU_6 ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1921 } ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -36322,13 +35368,15 @@ grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1113 } ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -36346,7 +35394,7 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -36398,18 +35446,18 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; -grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; +grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -36427,7 +35475,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -36479,18 +35527,19 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; grid_clb grid_clb_2__2_ ( .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -36508,7 +35557,7 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -36560,16 +35609,18 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; -sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -36583,7 +35634,7 @@ sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -36602,8 +35653,8 @@ sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -36620,8 +35671,8 @@ sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , @@ -36651,18 +35702,12 @@ sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_2123 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -36705,13 +35750,14 @@ sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; -sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -36746,14 +35792,17 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -36775,7 +35824,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -36811,8 +35860,10 @@ sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -36837,10 +35888,10 @@ sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_3032 } ) , + .prog_clk ( { ctsbuf_net_2426 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -36874,12 +35925,11 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -36913,11 +35963,10 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -36940,10 +35989,10 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -36966,10 +36015,10 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -36999,10 +36048,11 @@ cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; -cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_57 } ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -37032,9 +36082,12 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; -cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -37047,9 +36100,8 @@ cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -37062,9 +36114,9 @@ cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; -cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_2325 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -37087,11 +36139,9 @@ cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -37114,11 +36164,9 @@ cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -37147,9 +36195,9 @@ cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_24 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -37178,8 +36226,7 @@ cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; @@ -37187,41 +36234,53 @@ direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , .out ( direct_interc_2_out ) ) ; direct_interc_3 direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , - .out ( { SYNOPSYS_UNCONNECTED_54 } ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .out ( { SYNOPSYS_UNCONNECTED_57 } ) ) ; direct_interc_4 direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , - .out ( { SYNOPSYS_UNCONNECTED_56 } ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .out ( { SYNOPSYS_UNCONNECTED_59 } ) ) ; direct_interc direct_interc_5_ ( .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( { SYNOPSYS_UNCONNECTED_57 } ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , - .Y ( ctsbuf_net_57 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( - .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , + .out ( { SYNOPSYS_UNCONNECTED_60 } ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , + .Y ( ctsbuf_net_24 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , + .Y ( ctsbuf_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , + .Y ( ctsbuf_net_1113 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , .Y ( ctsbuf_net_1214 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , +sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( - .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , - .Y ( ctsbuf_net_1517 ) ) ; -sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , +sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , + .Y ( ctsbuf_net_1416 ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , + .Y ( ctsbuf_net_1719 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_1820 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , + .Y ( ctsbuf_net_1921 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_2022 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , + .Y ( ctsbuf_net_2123 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , + .Y ( ctsbuf_net_2224 ) ) ; +sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , + .Y ( ctsbuf_net_2325 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , + .Y ( ctsbuf_net_2426 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , + .Y ( ctsbuf_net_2527 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , + .Y ( ctsbuf_net_2628 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , .Y ( ctsbuf_net_2729 ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( - .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , - .Y ( ctsbuf_net_3032 ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( - .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , - .Y ( ctsbuf_net_3436 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_3537 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2830 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds index f1f5d0c..16796f9 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b89f1ad33da0b82f8dd361e1e49734a9327449f1e4dd3d5349393798782ab4e9 -size 11003904 +oid sha256:e07067ec52fe561df32514f51de2fef88738014e681727e37dbcc04785c82ec0 +size 11020288 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v index 0d4b698..ffa37f1 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v @@ -54,25 +54,25 @@ assign out[0] = in[0] ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -90,23 +90,16 @@ input VDD ; input VSS ; supply1 VDD ; -wire aps_rename_1_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -137,11 +130,10 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -179,240 +171,200 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -543,13 +495,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -573,10 +521,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -851,270 +799,225 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1697,7 +1600,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS , prog_clk__FEEDTHRU_1 ) ; + VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1730,26 +1633,34 @@ output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1759,21 +1670,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1791,263 +1694,229 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -2055,122 +1924,122 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1553 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1668 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1554 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1669 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1555 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1670 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1556 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1671 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1557 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1672 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1558 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1673 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1559 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1674 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1560 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1675 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1561 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1676 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1562 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1677 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1563 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1678 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1564 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1679 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1565 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1680 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1566 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1681 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1567 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1682 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( @@ -2179,45 +2048,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -2232,331 +2106,363 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x41400y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( +sky130_fd_sc_hd__fill_2 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2572,16 +2478,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( @@ -2596,251 +2502,209 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2862,13 +2726,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2892,10 +2752,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2970,13 +2830,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3000,10 +2856,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3186,9 +3042,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3212,10 +3072,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -3274,243 +3134,203 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4026,9 +3846,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -4056,25 +3874,31 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -4083,21 +3907,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -4109,440 +3925,409 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1537 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1652 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1538 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1653 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1539 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1654 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1540 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1655 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1541 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1656 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1542 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1657 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1543 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1658 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1544 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1659 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1545 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1660 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1546 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1661 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1547 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1662 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1548 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1663 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1549 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1664 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1550 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1665 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1551 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1666 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( @@ -4555,389 +4340,409 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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, .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_1!x542800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4953,16 +4758,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( @@ -4977,11 +4782,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4994,25 +4797,23 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5042,10 +4843,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5077,11 +4880,10 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -5122,30 +4924,25 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -5174,6 +4971,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5208,9 +5008,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -5219,7 +5016,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -5236,11 +5033,10 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -5250,252 +5046,235 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1521 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1636 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1522 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1637 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1523 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1638 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1524 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1639 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1525 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1640 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1526 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1641 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1527 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1642 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1528 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1643 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1529 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1644 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1530 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1645 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1531 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1646 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1532 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1647 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1533 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1648 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1534 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1649 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1535 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1650 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -5510,18 +5289,18 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -5534,59 +5313,63 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5596,13 +5379,19 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5614,21 +5403,17 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5646,29 +5431,25 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5684,70 +5465,68 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( @@ -5762,35 +5541,29 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5806,111 +5579,109 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5926,30 +5697,24 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( @@ -5970,23 +5735,23 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6002,36 +5767,28 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( @@ -6052,12 +5809,14 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( @@ -6068,8 +5827,6 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( @@ -6084,34 +5841,30 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( @@ -6136,20 +5889,24 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( @@ -6164,31 +5921,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6210,21 +5967,27 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6240,35 +6003,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6276,141 +6035,129 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6426,16 +6173,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( @@ -6450,11 +6197,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6467,25 +6212,23 @@ assign out[0] = in[0] ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6503,15 +6246,18 @@ input VDD ; input VSS ; supply1 VDD ; +wire aps_rename_1_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -6543,11 +6289,10 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -6585,241 +6330,201 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7165,9 +6870,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7191,10 +6900,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7253,271 +6962,226 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7923,6 +7587,69 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7963,65 +7690,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -8096,7 +7764,8 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -8133,26 +7802,36 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -8162,21 +7841,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -8196,451 +7867,431 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1618 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1619 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1620 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1621 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1622 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1623 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1509 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1624 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1510 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1625 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1511 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1626 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1512 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1627 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1513 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1628 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1514 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1629 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1515 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1630 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1516 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1631 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1517 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1632 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1518 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1633 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1519 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1634 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( @@ -8649,16 +8300,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -8673,227 +8324,261 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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, .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y108800 ( .VGND ( VSS ) , .VPWR ( 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( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y190400 ( +sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -8903,329 +8588,313 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y625600 ( + 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\xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9233,21 +8902,11 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -9263,16 +8922,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( @@ -9287,250 +8946,208 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9661,9 +9278,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -9687,10 +9308,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -9931,6 +9552,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -9958,247 +9582,206 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10538,9 +10121,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -10571,10 +10158,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10664,6 +10251,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -10698,9 +10288,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -10744,22 +10331,30 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -10768,21 +10363,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -10802,441 +10389,403 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1600 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1601 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1602 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1603 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1604 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1605 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1606 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1607 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1493 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1608 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1609 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1610 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1611 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1612 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1613 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1499 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1614 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1615 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1616 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -11251,16 +10800,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -11275,647 +10824,683 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y54400 ( 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x404800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_1!x349600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -11931,16 +11516,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( @@ -11955,34 +11540,30 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12006,12 +11587,10 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12042,11 +11621,10 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -12083,24 +11661,22 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12123,9 +11699,9 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12157,12 +11733,10 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -12191,33 +11765,30 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12234,16 +11805,19 @@ input VDD ; input VSS ; supply1 VDD ; +wire aps_rename_3_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12274,12 +11848,10 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -12308,38 +11880,35 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -12347,6 +11916,7 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; input VDD ; input VSS ; @@ -12355,11 +11925,13 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12367,7 +11939,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -12379,6 +11951,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; @@ -12389,14 +11962,12 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -12425,33 +11996,33 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12474,9 +12045,9 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12508,12 +12079,10 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -12542,11 +12111,10 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule @@ -12559,29 +12127,27 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -12589,6 +12155,7 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; input VDD ; input VSS ; @@ -12597,11 +12164,13 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12609,7 +12178,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -12621,6 +12190,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; @@ -12631,14 +12201,12 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -12667,9 +12235,11 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; @@ -12677,180 +12247,150 @@ endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12875,13 +12415,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -12912,10 +12448,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13245,7 +12781,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -13287,36 +12823,39 @@ output SC_OUT_BOT ; input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -13324,446 +12863,454 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_184 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_182 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_182 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1582 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1583 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1584 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1585 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1586 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1587 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1588 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1589 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1590 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1591 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1477 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1592 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1593 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1594 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1595 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1596 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1597 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1598 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -13778,16 +13325,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -13802,822 +13349,780 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( .VGND ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( +sky130_fd_sc_hd__fill_2 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) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y544000 ( +sky130_fd_sc_hd__fill_8 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) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 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) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( @@ -14632,18 +14137,12 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( @@ -14658,16 +14157,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( @@ -14682,82 +14181,71 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14860,576 +14348,506 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15959,15 +15377,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16063,121 +15485,109 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16238,13 +15648,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16258,10 +15664,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16279,13 +15685,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16299,10 +15701,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16324,6 +15726,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16341,117 +15746,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16607,9 +15991,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -16626,10 +16014,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -16676,54 +16064,65 @@ output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -16748,34 +16147,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -16790,7 +16178,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( @@ -16798,73 +16186,65 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( @@ -16872,586 +16252,544 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1543 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1544 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1545 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1433 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1546 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1547 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1548 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1549 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1550 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1551 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1552 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1553 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1554 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1555 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1556 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1557 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1558 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1559 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1447 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1560 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1561 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1562 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1563 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1564 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1565 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1566 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1567 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1568 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1569 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1570 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1571 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1572 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1460 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1573 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1461 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1574 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1575 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1576 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1577 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1578 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1579 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1580 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -17459,22 +16797,36 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( @@ -17489,985 +16841,1017 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y163200 ( +sky130_fd_sc_hd__fill_8 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, .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x207000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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.VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( +sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x64400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x124200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x726800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x906200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( 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VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18475,59 +17859,59 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18537,43 +17921,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18587,39 +17961,43 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18635,36 +18013,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( @@ -18673,59 +18055,53 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18741,49 +18117,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18805,43 +18181,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18857,49 +18231,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -18915,16 +18289,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( @@ -18945,168 +18319,146 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19181,15 +18533,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -19262,133 +18614,118 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19548,115 +18885,99 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19715,9 +19036,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19731,6 +19049,11 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19787,6 +19110,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19800,37 +19126,29 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19858,9 +19176,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -19892,85 +19207,76 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20085,6 +19391,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20105,196 +19414,165 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20320,6 +19598,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20344,9 +19625,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -20370,6 +19648,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20394,9 +19675,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -20470,6 +19748,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20494,9 +19775,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -20566,9 +19844,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -20589,10 +19871,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20647,60 +19929,50 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20869,90 +20141,75 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20979,6 +20236,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21006,9 +20266,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -21121,60 +20378,50 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21203,6 +20450,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21237,9 +20487,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -21320,7 +20567,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 ) ; + Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -21360,86 +20607,92 @@ input VDD ; input VSS ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -21448,96 +20701,84 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -21546,9 +20787,9 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -21557,726 +20798,668 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1391 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1392 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1393 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1502 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1394 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1395 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1396 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1397 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1398 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1399 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1400 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1509 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1401 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1510 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1402 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1511 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1512 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1513 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1514 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1515 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1516 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1517 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1518 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1519 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1520 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1521 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1522 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1523 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1524 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1525 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1526 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1527 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1419 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1528 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1529 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1530 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1531 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1532 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1533 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1534 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1535 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1536 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1537 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1538 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1539 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1540 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1541 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -22292,453 +21475,481 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x565800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x584200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x777400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y299200 ( +sky130_fd_sc_hd__fill_2 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( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -22746,745 +21957,833 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_8!x161000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y544000 ( - .VGND ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y598400 ( +sky130_fd_sc_hd__fill_2 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( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x630200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23500,25 +22799,19 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23526,206 +22819,204 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y979200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1006400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1006400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1006400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1033600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1060800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23856,6 +23147,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -23869,489 +23163,428 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24368,73 +23601,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -24461,7 +23640,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -24482,12 +23688,35 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -24503,15 +23732,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -24526,19 +23755,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24580,15 +23805,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -24603,15 +23828,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24630,15 +23859,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -24657,15 +23886,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -24886,48 +24115,42 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24998,54 +24221,46 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25134,54 +24349,46 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25310,46 +24517,56 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -25370,33 +24587,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; @@ -25407,567 +24614,485 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1461 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1466 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1365 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1366 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1367 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1368 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1369 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1370 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1477 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1371 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1372 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1373 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1374 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1375 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1376 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1377 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1484 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1378 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1379 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1380 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1381 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1382 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1493 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -25982,16 +25107,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -26012,21 +25137,19 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26048,43 +25171,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26100,53 +25221,53 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26164,47 +25285,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26216,66 +25335,76 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( @@ -26296,9 +25425,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26306,365 +25433,367 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y217600 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x533600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x584200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x289800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26674,41 +25803,47 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -26718,78 +25853,94 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y435200 ( @@ -26798,587 +25949,603 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -27394,176 +26561,192 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27614,25 +26797,22 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27652,158 +26832,140 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27824,6 +26986,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27834,9 +26999,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -27916,23 +27078,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27948,23 +27106,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28001,82 +27155,70 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28098,9 +27240,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28114,6 +27253,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -28170,9 +27312,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28186,32 +27325,31 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28258,217 +27396,185 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28639,6 +27745,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; @@ -28664,8 +27771,11 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -28785,13 +27895,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28812,10 +27918,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28870,61 +27976,51 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29038,61 +28134,51 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29260,91 +28346,76 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29527,31 +28598,26 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -29634,9 +28700,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , Test_en__FEEDTHRU_0 , + Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -29678,33 +28744,55 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -29712,35 +28800,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -29750,17 +28825,12 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; @@ -29768,6 +28838,8 @@ supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -29776,63 +28848,55 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -29842,9 +28906,9 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -29853,705 +28917,655 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1429 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1433 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1335 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1336 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1337 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1338 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1339 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1340 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1341 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1342 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1447 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1343 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1344 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1345 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1346 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1347 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1348 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1349 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1350 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1351 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1352 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -30567,1430 +29581,1346 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y136000 ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1039600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y217600 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x671600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y272000 ( 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) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1076400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x754400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1094800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x432400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1094800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y598400 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x1062600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1154600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1163800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1209800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1081000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1159200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( @@ -32003,64 +30933,60 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( @@ -32075,67 +31001,63 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -32157,32 +31079,32 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( @@ -32203,13 +31125,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -32225,42 +31143,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y924800 ( @@ -32275,13 +31191,11 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -32297,16 +31211,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( @@ -32327,148 +31241,126 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32640,9 +31532,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -32663,368 +31559,308 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33787,132 +32623,108 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33934,7 +32746,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -33998,13 +32809,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34092,9 +32900,11 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34217,6 +33027,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -34272,247 +33085,204 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34615,9 +33385,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -34659,6 +33426,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -35112,6 +33882,7 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -35162,33 +33933,51 @@ input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -35202,21 +33991,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -35226,31 +34007,25 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -35258,7 +34033,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( @@ -35268,9 +34043,9 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -35278,9 +34053,9 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -35288,9 +34063,9 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -35298,9 +34073,9 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -35308,9 +34083,9 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -35318,9 +34093,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -35328,63 +34103,47 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -35394,9 +34153,9 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -35406,9 +34165,9 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -35418,9 +34177,9 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -35430,43 +34189,35 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( @@ -35475,188 +34226,166 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( @@ -35664,469 +34393,464 @@ sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1379 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1380 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1381 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1382 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1390 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1392 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1393 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1394 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1395 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1396 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1397 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1398 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1399 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1402 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1302 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1303 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1304 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1305 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1306 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1307 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1308 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1309 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1310 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1311 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1312 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1313 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1314 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1315 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1419 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 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) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x1145400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y190400 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1104000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y217600 ( 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y326400 ( 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( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x1025800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_4!x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_2!x1223600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 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\xofiller!sky130_fd_sc_hd__fill_1!x777400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y734400 ( + .VGND ( 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VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y816000 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x584200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( @@ -37657,20 +36367,18 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( @@ -37683,145 +36391,149 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y979200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y1006400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1006400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1033600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1060800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37909,55 +36621,47 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38053,61 +36757,51 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38204,6 +36898,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -38242,32 +36939,26 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38300,169 +36991,148 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38692,55 +37362,47 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38818,244 +37480,208 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39226,13 +37852,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -39253,10 +37875,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39511,91 +38133,76 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39773,11 +38380,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -39815,38 +38418,48 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -39855,40 +38468,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -39899,11 +38497,8 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -39912,8 +38507,6 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , @@ -39921,315 +38514,271 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_133 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_133 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -40237,9 +38786,9 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -40247,342 +38796,301 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1340 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1341 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1342 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1343 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1344 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1345 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1346 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1347 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1348 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1349 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1350 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1353 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1255 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1263 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1365 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1366 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1367 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1368 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1369 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1370 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1272 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1371 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1273 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1372 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1274 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1373 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1275 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1374 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1276 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1375 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1376 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1377 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -40597,16 +39105,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -40627,37 +39135,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -40679,65 +39183,57 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -40749,64 +39245,60 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( @@ -40827,32 +39319,32 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( @@ -40873,13 +39365,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -40891,73 +39379,69 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -40975,32 +39459,32 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( @@ -41021,13 +39505,9 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -41043,65 +39523,57 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -41123,1255 +39595,1251 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_8!x984400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y299200 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_1!x1053400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1127000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1145400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x975200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1030400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1127000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1145400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y625600 ( +sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_4!x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y652800 ( 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) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1071800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y707200 ( 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) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y707200 ( +sky130_fd_sc_hd__fill_4 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, .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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, .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -42387,37 +40855,29 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -42431,530 +40891,478 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43079,15 +41487,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43133,15 +41545,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -43156,19 +41568,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43210,19 +41618,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43349,15 +41753,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -43443,48 +41847,42 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43555,54 +41953,46 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43691,54 +42081,46 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43865,42 +42247,48 @@ output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -43919,21 +42307,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; @@ -43946,522 +42328,458 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1304 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1305 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1306 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1307 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1308 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1309 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1310 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1311 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1312 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1313 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1316 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1218 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1235 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1335 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1337 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1338 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( @@ -44470,53 +42788,59 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -44524,230 +42848,224 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y190400 ( 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\xofiller!sky130_fd_sc_hd__fill_4!x832600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y217600 ( 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\xofiller!sky130_fd_sc_hd__fill_2!x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( @@ -44756,203 +43074,221 @@ sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -44964,97 +43300,97 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45064,33 +43400,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45106,9 +43450,13 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45116,33 +43464,21 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45154,45 +43490,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45202,50 +43534,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( @@ -45258,42 +43584,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( @@ -45306,37 +43640,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45352,42 +43688,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( @@ -45402,46 +43740,38 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( @@ -45456,43 +43786,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45514,14 +43846,24 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y680000 ( @@ -45532,18 +43874,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( @@ -45558,45 +43898,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45618,46 +43954,42 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( @@ -45672,52 +44004,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( @@ -45738,41 +44068,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45788,50 +44118,46 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( @@ -45852,44 +44178,42 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( @@ -45904,49 +44228,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45968,43 +44292,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -46020,49 +44342,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -46078,16 +44400,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( @@ -46108,164 +44430,144 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46359,15 +44661,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46413,135 +44719,120 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46708,81 +44999,69 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46939,189 +45218,161 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47144,42 +45395,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -47199,6 +45414,42 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:3] in ; @@ -47288,9 +45539,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -47304,6 +45552,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -47360,9 +45611,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -47376,139 +45624,122 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47696,9 +45927,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -47716,193 +45944,170 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47972,9 +46177,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -47995,6 +46197,11 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48062,53 +46269,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -48135,6 +46295,47 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; @@ -48255,18 +46456,45 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -48274,33 +46502,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -48309,34 +46525,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -48345,11 +46549,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -48360,684 +46561,594 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1165 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1166 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1167 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1168 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1169 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1170 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1171 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1172 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1173 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1272 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1174 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1175 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1274 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1176 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1177 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1178 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1277 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1179 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1180 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1181 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1182 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1183 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1184 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1185 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1186 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1187 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( @@ -49050,16 +47161,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -49074,43 +47185,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49118,45 +47235,79 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49166,45 +47317,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49216,36 +47359,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( @@ -49254,138 +47405,126 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( @@ -49394,43 +47533,51 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49438,41 +47585,55 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49482,49 +47643,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49532,47 +47683,47 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49580,131 +47731,149 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49716,121 +47885,145 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y462400 ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49842,107 +48035,95 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y571200 ( 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) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -49950,347 +48131,381 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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-sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50298,46 +48513,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( @@ -50346,29 +48559,25 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50376,13 +48585,13 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50392,39 +48601,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50432,48 +48641,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( @@ -50482,77 +48683,93 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50560,65 +48777,69 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y979200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y979200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y1006400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y1006400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y1006400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y1033600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y1033600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -50634,16 +48855,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y1060800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y1060800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( @@ -50658,118 +48879,100 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y1060800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50896,9 +49099,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -50908,394 +49115,346 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51316,87 +49475,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -51409,6 +49487,83 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -51505,15 +49660,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -51532,33 +49687,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -51571,6 +49699,33 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -51613,15 +49768,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -51755,38 +49910,42 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -51803,13 +49962,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -51820,449 +49975,373 @@ supply0 VSS ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1128 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1129 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1130 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1131 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1132 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1133 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1134 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1135 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1136 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1235 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1137 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1138 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1139 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1140 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1141 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1240 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1142 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1143 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1144 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1145 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1146 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1147 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1148 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1149 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1150 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1151 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1152 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1153 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1154 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1155 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1156 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1255 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1157 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1158 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1159 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1160 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1161 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1162 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1163 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -52277,16 +50356,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -52307,21 +50386,19 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52335,47 +50412,47 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52391,49 +50468,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52455,43 +50532,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52507,46 +50582,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( @@ -52567,40 +50646,42 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( @@ -52615,49 +50696,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52679,41 +50760,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52729,47 +50810,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52791,43 +50874,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -52843,44 +50924,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( @@ -52901,42 +50988,42 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( @@ -52951,42 +51038,50 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( @@ -53007,29 +51102,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53045,36 +51148,46 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( @@ -53095,35 +51208,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53139,22 +51248,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( @@ -53167,33 +51294,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53203,46 +51334,34 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( @@ -53251,35 +51370,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53295,42 +51416,38 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( @@ -53339,41 +51456,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53387,87 +51508,79 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53479,81 +51592,73 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53563,42 +51668,34 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( @@ -53607,102 +51704,88 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( @@ -53713,52 +51796,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( @@ -53771,53 +51846,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53827,65 +51886,73 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53893,35 +51960,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -53937,16 +52014,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( @@ -53961,83 +52038,74 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , + .X ( net_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54066,7 +52134,7 @@ endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; + p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -54074,6 +52142,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -54084,12 +52153,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , - .X ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54112,9 +52181,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54140,14 +52209,12 @@ supply0 VSS ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , - .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , - .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54172,25 +52239,22 @@ endmodule module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54217,71 +52281,60 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54330,7 +52383,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -54428,13 +52481,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , @@ -54460,19 +52513,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -54481,15 +52535,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -54509,8 +52554,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -54530,12 +52575,12 @@ grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -54557,8 +52602,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , - p0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , + p_abuf6 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -54577,19 +52622,20 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -54615,44 +52661,43 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( fabric_regout[0] ) , .p_abuf2 ( p_abuf2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( fabric_regout[0] ) , + .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; @@ -54694,7 +52739,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; + p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -54713,7 +52758,8 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; supply1 VDD ; @@ -54727,16 +52773,17 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( + .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , .p_abuf6 ( p_abuf6 ) , + .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; @@ -54762,85 +52809,100 @@ endmodule module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -54853,10 +52915,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , + .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -54878,35 +52944,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54952,38 +52992,35 @@ endmodule module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -54992,77 +53029,66 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55108,10 +53134,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -55213,9 +53239,9 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , @@ -55241,19 +53267,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -55262,22 +53289,13 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -55285,13 +53303,13 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -55311,12 +53329,12 @@ grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -55338,7 +53356,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -55354,20 +53372,21 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -55380,7 +53399,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -55400,37 +53419,35 @@ grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , - .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -55471,8 +53488,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , - p_abuf3 , p0 ) ; + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -55488,9 +53505,10 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; supply1 VDD ; supply0 VSS ; @@ -55502,11 +53520,11 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , - .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p0 ( p0 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; + .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; @@ -55538,72 +53556,63 @@ endmodule module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55650,16 +53659,16 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -55667,6 +53676,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -55676,10 +53686,12 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55725,24 +53737,21 @@ endmodule module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55771,70 +53780,59 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -55875,19 +53873,19 @@ supply0 VSS ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( @@ -56014,19 +54012,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -56035,15 +54034,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -56063,8 +54053,8 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -56084,12 +54074,12 @@ grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -56111,7 +54101,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -56127,19 +54117,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -56172,36 +54163,35 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -56242,7 +54232,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p3 ) ; + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -56258,6 +54249,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; @@ -56271,118 +54263,113 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_2_ ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -56391,7 +54378,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56419,9 +54406,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56447,7 +54434,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56493,24 +54480,21 @@ endmodule module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56539,71 +54523,60 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -56750,13 +54723,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -56782,19 +54755,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -56803,15 +54777,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -56831,8 +54796,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -56852,12 +54817,12 @@ grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -56903,13 +54868,13 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -56942,37 +54907,35 @@ grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , - .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -57081,73 +55044,64 @@ endmodule module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57176,32 +55130,6 @@ endmodule module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; @@ -57223,9 +55151,35 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57271,24 +55225,21 @@ endmodule module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57317,70 +55268,59 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57418,25 +55358,25 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -57532,7 +55472,7 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -57560,19 +55500,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -57581,15 +55522,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -57609,8 +55541,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -57630,12 +55562,12 @@ grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -57657,7 +55589,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -57673,20 +55605,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -57719,37 +55651,35 @@ grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -57790,8 +55720,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p2 ) ; + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , + p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -57807,8 +55737,8 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; supply1 VDD ; @@ -57821,11 +55751,11 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; @@ -57857,73 +55787,64 @@ endmodule module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -57952,33 +55873,7 @@ endmodule module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; + p_abuf0 , p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -57987,7 +55882,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -57996,12 +55891,41 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58047,38 +55971,35 @@ endmodule module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -58087,76 +56008,65 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58194,13 +56104,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( @@ -58304,13 +56214,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , @@ -58336,19 +56246,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -58357,22 +56268,13 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -58380,13 +56282,13 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -58406,12 +56308,12 @@ grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -58433,7 +56335,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -58451,19 +56353,19 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -58476,7 +56378,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -58496,37 +56398,35 @@ grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -58568,7 +56468,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p0 , p2 ) ; + p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -58586,7 +56486,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; supply1 VDD ; @@ -58600,108 +56500,102 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58750,13 +56644,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; + p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -58764,6 +56658,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -58773,10 +56668,12 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58822,24 +56719,21 @@ endmodule module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58868,71 +56762,60 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -58972,7 +56855,7 @@ supply0 VSS ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( @@ -59111,19 +56994,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -59132,15 +57016,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -59160,8 +57035,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -59181,12 +57056,12 @@ grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -59208,7 +57083,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p0 , p1 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -59224,6 +57099,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -59231,13 +57107,13 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -59270,36 +57146,35 @@ grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -59340,8 +57215,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p0 , - p1 ) ; + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -59357,6 +57232,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -59371,118 +57247,113 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_2_ ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -59491,40 +57362,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p4 ) ; + p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -59533,7 +57378,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p4 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -59542,13 +57387,44 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , + .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59601,24 +57477,21 @@ endmodule module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59647,71 +57520,60 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -59760,7 +57622,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -59890,19 +57752,20 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -59911,15 +57774,6 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -59939,8 +57793,8 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; @@ -59960,12 +57814,12 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -59987,7 +57841,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -60005,19 +57859,20 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; supply1 VDD ; @@ -60050,37 +57905,35 @@ grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -60122,7 +57975,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p1 , p4 ) ; + p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -60140,8 +57993,9 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; supply1 VDD ; supply0 VSS ; @@ -60154,13 +58008,13 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p1 ( p1 ) , .p4 ( p4 ) ) ; + .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; @@ -60196,9 +58050,9 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , clb_regout , clb_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf3 , - p_abuf5 , p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , - p_abuf18 , p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , - p_abuf30 , p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; + p_abuf5 , p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , + p_abuf19 , p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , + p_abuf31 , p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -60231,26 +58085,25 @@ input VSS ; output p_abuf0 ; output p_abuf3 ; output p_abuf5 ; -output p_abuf6 ; -output p_abuf8 ; -output p_abuf10 ; -output p_abuf12 ; -output p_abuf14 ; -output p_abuf16 ; -output p_abuf18 ; -output p_abuf20 ; -output p_abuf22 ; -output p_abuf24 ; -output p_abuf26 ; -output p_abuf28 ; -output p_abuf30 ; +output p_abuf7 ; +output p_abuf9 ; +output p_abuf11 ; +output p_abuf13 ; +output p_abuf15 ; +output p_abuf17 ; +output p_abuf19 ; +output p_abuf21 ; +output p_abuf23 ; +output p_abuf25 ; +output p_abuf27 ; +output p_abuf29 ; output p_abuf31 ; +output p_abuf33 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; -input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -60278,7 +58131,7 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , @@ -60286,10 +58139,11 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , - .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , .p_abuf3 ( p_abuf6 ) , + .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60298,11 +58152,11 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf6 ) , - .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , + .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60311,11 +58165,12 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf10 ) , - .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , + .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , .p_abuf3 ( p_abuf14 ) , + .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60324,11 +58179,11 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf14 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p2 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf15 ) , + .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60337,11 +58192,11 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf18 ) , - .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf19 ) , + .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60350,11 +58205,11 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf22 ) , - .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf23 ) , + .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60363,11 +58218,11 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf26 ) , - .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf27 ) , + .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -60376,201 +58231,211 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , .p0 ( p1 ) ) ; + .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , .p_abuf6 ( p_abuf34 ) , + .p0 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf5 } ) ) ; + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf11 } ) ) ; -grid_clb_direct_interc direct_interc_7_ ( + .out ( { p_abuf8 } ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf15 } ) ) ; -grid_clb_direct_interc direct_interc_8_ ( + .out ( { p_abuf14 } ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf21 } ) ) ; -grid_clb_direct_interc direct_interc_12_ ( + .out ( { p_abuf12 } ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf29 } ) ) ; -grid_clb_direct_interc direct_interc_15_ ( + .out ( { p_abuf18 } ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { p_abuf30 } ) ) ; -grid_clb_direct_interc direct_interc_16_ ( + .out ( { p_abuf22 } ) ) ; +grid_clb_direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( + .out ( { p_abuf24 } ) ) ; +grid_clb_direct_interc direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_18_ ( + .out ( { p_abuf28 } ) ) ; +grid_clb_direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( clb_I0[2] ) ) ; -grid_clb_direct_interc direct_interc_19_ ( + .out ( { p_abuf34 } ) ) ; +grid_clb_direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( clb_I0[0] ) ) ; +grid_clb_direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , .out ( clb_I0[1] ) ) ; grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( clb_I0[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .out ( clb_I0[2] ) ) ; grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , .out ( clb_I0i ) ) ; grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , .out ( clb_regin ) ) ; grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , .out ( clb_sc_in ) ) ; grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( clb_I1[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .out ( clb_I1[0] ) ) ; grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , .out ( clb_I1[1] ) ) ; grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I1[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .out ( clb_I1[2] ) ) ; grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_I1i ) ) ; grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_I2[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I2[0] ) ) ; grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , .out ( clb_I2[1] ) ) ; grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I2[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .out ( clb_I2[2] ) ) ; grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( clb_I2i ) ) ; grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( clb_I3[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I3[0] ) ) ; grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , .out ( clb_I3[1] ) ) ; grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I3[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .out ( clb_I3[2] ) ) ; grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( clb_I3i ) ) ; grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( clb_I4[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I4[0] ) ) ; grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , .out ( clb_I4[1] ) ) ; grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I4[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .out ( clb_I4[2] ) ) ; grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( clb_I4i ) ) ; grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( clb_I5[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I5[0] ) ) ; grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , .out ( clb_I5[1] ) ) ; grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I5[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .out ( clb_I5[2] ) ) ; grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( clb_I5i ) ) ; grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( clb_I6[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I6[0] ) ) ; grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , .out ( clb_I6[1] ) ) ; grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I6[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .out ( clb_I6[2] ) ) ; grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( clb_I6i ) ) ; grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( clb_I7[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I7[0] ) ) ; grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , .out ( clb_I7[1] ) ) ; grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I7[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .out ( clb_I7[2] ) ) ; grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( clb_I7i ) ) ; grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , .out ( clb_clk ) ) ; endmodule @@ -60620,8 +58485,8 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_2 , prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , + Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -60705,23 +58570,26 @@ input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] prog_clk__FEEDTHRU_4 ; output [0:0] Test_en__FEEDTHRU_1 ; output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf2 ; +wire ropt_net_156 ; +wire ropt_net_153 ; +wire ropt_net_151 ; wire ropt_net_150 ; -wire ropt_net_141 ; -wire ropt_net_139 ; -wire ropt_net_144 ; -wire ropt_net_140 ; -wire p_abuf15 ; -wire ropt_net_147 ; +wire ropt_net_167 ; +wire ropt_net_154 ; +wire ropt_net_168 ; +wire ropt_net_152 ; +wire ropt_net_163 ; +wire ropt_net_162 ; supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; +assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -60756,236 +58624,248 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , aps_rename_136_ , - top_width_0_height_0__pin_36_lower[0] , - top_width_0_height_0__pin_37_lower[0] , - top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , - top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , - aps_rename_144_ , aps_rename_145_ , - right_width_0_height_0__pin_44_lower[0] , - right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , - .clb_regout ( { ropt_net_153 } ) , - .clb_sc_out ( { aps_rename_155_ } ) , - .ccff_tail ( { ropt_net_149 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_147 ) , - .p_abuf3 ( ropt_net_150 ) , .p_abuf5 ( p_abuf2 ) , - .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , - .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf10 ( ropt_net_141 ) , - .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , - .p_abuf14 ( ropt_net_139 ) , - .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf18 ( ropt_net_144 ) , - .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , - .p_abuf26 ( ropt_net_140 ) , - .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf30 ( p_abuf15 ) , - .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , - .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , - .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1089 ( .VNB ( VSS ) , + .clb_O ( { aps_rename_138_ , aps_rename_139_ , + top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , + aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , + top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , + aps_rename_158_ } ) , + .clb_regout ( { ropt_net_161 } ) , + .clb_sc_out ( { aps_rename_160_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_162 ) , + .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , + .p_abuf7 ( ropt_net_156 ) , + .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , + .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , + .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , + .p_abuf27 ( ropt_net_152 ) , + .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , + .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , + .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , + .p4 ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1090 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1091 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1092 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1093 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1094 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1095 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1096 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1097 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1098 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1099 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1100 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1101 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1102 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1103 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1104 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1203 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1105 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1106 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1107 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1108 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1109 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1110 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1111 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1112 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1113 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1114 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1115 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1116 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1117 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1118 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1119 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1218 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1120 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1121 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1122 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1123 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1124 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1125 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1126 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , - .X ( aps_rename_135_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_5138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , - .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , - .X ( aps_rename_154_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , - .X ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , - .X ( clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , - .X ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , + .X ( aps_rename_143_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_6147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , - .X ( prog_clk__FEEDTHRU_3[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , + .X ( aps_rename_155_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , + .X ( clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , .X ( top_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , + .X ( right_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , + .X ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , + .X ( prog_clk__FEEDTHRU_4[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , .X ( right_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , .X ( right_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -61000,16 +58880,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( @@ -61030,307 +58910,275 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y81600 ( +sky130_fd_sc_hd__fill_4 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) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1044200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x860200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61340,781 +59188,817 @@ sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y272000 ( 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-sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1094800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1113200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 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VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1182200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x874000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x901600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x515200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x611800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x938400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x1090200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y571200 ( +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_1!x1058000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y598400 ( +sky130_fd_sc_hd__fill_2 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) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x105800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x335800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1053400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x947600y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62130,16 +60014,16 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( @@ -62160,37 +60044,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -62627,7 +60507,6 @@ wire [0:0] prog_clk__FEEDTHRU_16 ; wire [0:0] prog_clk__FEEDTHRU_17 ; wire [0:0] prog_clk__FEEDTHRU_18 ; wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] prog_clk__FEEDTHRU_20 ; wire [0:0] Test_en__FEEDTHRU_1 ; wire [0:0] Test_en__FEEDTHRU_2 ; wire [0:0] Test_en__FEEDTHRU_3 ; @@ -62638,15 +60517,14 @@ wire [0:0] clk__FEEDTHRU_1 ; wire [0:0] clk__FEEDTHRU_2 ; wire [0:0] clk__FEEDTHRU_3 ; wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] clk__FEEDTHRU_5 ; +wire [0:0] clk__FEEDTHRU_6 ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1921 } ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -62721,13 +60599,15 @@ grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1113 } ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -62745,7 +60625,7 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -62797,19 +60677,19 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; -grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; +grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -62827,7 +60707,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -62879,19 +60759,20 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; grid_clb grid_clb_2__2_ ( .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -62909,7 +60790,7 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -62961,17 +60842,19 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; -sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -62985,7 +60868,7 @@ sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -63004,8 +60887,8 @@ sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -63022,8 +60905,8 @@ sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , @@ -63054,19 +60937,13 @@ sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_2123 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -63109,13 +60986,14 @@ sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; -sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -63150,14 +61028,17 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , .VDD ( VDD ) , .VSS ( VSS ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , .VDD ( VDD ) , .VSS ( VSS ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -63179,7 +61060,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -63215,8 +61096,10 @@ sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -63241,10 +61124,10 @@ sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_3032 } ) , + .prog_clk ( { ctsbuf_net_2426 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -63278,13 +61161,12 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -63318,12 +61200,11 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -63346,11 +61227,11 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -63373,11 +61254,11 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -63407,11 +61288,12 @@ cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_57 } ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -63441,10 +61323,13 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -63458,9 +61343,8 @@ cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -63474,9 +61358,9 @@ cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; -cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_2325 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -63499,11 +61383,9 @@ cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -63526,11 +61408,9 @@ cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -63560,9 +61440,9 @@ cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_24 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -63592,8 +61472,7 @@ cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -63601,7 +61480,7 @@ direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , .out ( direct_interc_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_0 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65779,44 +63658,264 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1086 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1087 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1088 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1089 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1090 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1091 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1092 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1093 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1094 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1095 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1096 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1097 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1098 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1099 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1100 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1101 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1102 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1103 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1104 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1105 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1106 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1107 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1108 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1109 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1110 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1111 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1112 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1113 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1114 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1115 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1116 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1117 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1118 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1119 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1120 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1121 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1122 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1123 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1124 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1125 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1126 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1127 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1128 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1129 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1130 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1131 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1132 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1133 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1134 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1135 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1136 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1137 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1138 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1139 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1140 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1141 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1142 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1143 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1144 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1145 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1146 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1147 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1148 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1149 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1150 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1151 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1152 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1153 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1154 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1155 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1156 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1157 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1158 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1159 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1160 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1161 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1162 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1163 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1164 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1165 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1166 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1167 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1168 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1169 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1170 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1171 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1172 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1175 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1176 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1177 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1178 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1179 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1180 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1181 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1182 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1183 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1184 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1185 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1186 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , + .Y ( ctsbuf_net_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , + .Y ( ctsbuf_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , - .Y ( ctsbuf_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( - .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , + .Y ( ctsbuf_net_1113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , + .Y ( ctsbuf_net_1214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , + .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , + .Y ( ctsbuf_net_1416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , - .Y ( ctsbuf_net_1214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , - .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( - .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , - .Y ( ctsbuf_net_1517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , + .Y ( ctsbuf_net_1719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_1820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , + .Y ( ctsbuf_net_1921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_2022 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , + .Y ( ctsbuf_net_2123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , + .Y ( ctsbuf_net_2224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , + .Y ( ctsbuf_net_2325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , + .Y ( ctsbuf_net_2426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , + .Y ( ctsbuf_net_2527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , + .Y ( ctsbuf_net_2628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , + .Y ( ctsbuf_net_2729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -65827,33 +63926,17 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , - .Y ( ctsbuf_net_2729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( - .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , - .Y ( ctsbuf_net_3032 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( - .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , - .Y ( ctsbuf_net_3436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_3537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65885,7 +63968,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65909,9 +63994,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65941,7 +64024,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65967,9 +64052,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65997,62 +64080,68 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3371800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4324000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4342400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y0 ( @@ -66081,9 +64170,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66107,7 +64194,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66139,9 +64228,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66163,7 +64250,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66191,15 +64280,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66225,32 +64314,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( @@ -66335,7 +64424,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66361,9 +64452,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66445,7 +64534,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66475,9 +64566,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66555,7 +64644,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66589,9 +64680,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66611,70 +64700,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y54400 ( @@ -66697,9 +64786,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66783,7 +64870,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66811,9 +64900,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66893,7 +64980,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66925,9 +65014,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66977,13 +65064,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67009,32 +65098,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( @@ -67119,7 +65208,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67145,9 +65236,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67229,7 +65318,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67259,9 +65350,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67339,7 +65428,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67373,9 +65464,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67395,70 +65484,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y108800 ( @@ -67481,9 +65570,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67567,7 +65654,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67595,9 +65684,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67677,7 +65764,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67709,9 +65798,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67761,13 +65848,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67793,32 +65882,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( @@ -67903,7 +65992,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67929,9 +66020,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68013,7 +66102,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68043,9 +66134,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68123,7 +66212,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68157,9 +66248,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68179,70 +66268,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y163200 ( @@ -68265,9 +66354,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68351,7 +66438,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68379,9 +66468,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68461,7 +66548,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68493,9 +66582,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68545,13 +66632,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68577,32 +66666,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( @@ -68687,7 +66776,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68713,9 +66804,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68797,7 +66886,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68827,9 +66918,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68907,7 +66996,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68941,9 +67032,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68963,70 +67052,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y217600 ( @@ -69049,9 +67138,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69135,7 +67222,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69163,9 +67252,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69245,7 +67332,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69277,9 +67366,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69329,13 +67416,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69361,32 +67450,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( @@ -69471,7 +67560,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69497,9 +67588,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69581,7 +67670,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69611,9 +67702,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69691,7 +67780,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69725,9 +67816,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69747,70 +67836,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y272000 ( @@ -69833,9 +67922,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69919,7 +68006,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69947,9 +68036,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70029,7 +68116,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70061,9 +68150,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70113,13 +68200,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70145,32 +68234,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( @@ -70255,7 +68344,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70281,9 +68372,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70365,7 +68454,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70395,9 +68486,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70475,7 +68564,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70509,9 +68600,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70531,70 +68620,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y326400 ( @@ -70617,9 +68706,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70703,7 +68790,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70731,9 +68820,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70813,7 +68900,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70845,9 +68934,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70897,13 +68984,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70929,32 +69018,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( @@ -71039,7 +69128,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71065,9 +69156,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71149,7 +69238,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71179,9 +69270,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71259,7 +69348,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71293,9 +69384,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71315,70 +69404,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y380800 ( @@ -71401,9 +69490,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71487,7 +69574,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71515,9 +69604,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71597,7 +69684,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71629,9 +69718,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71681,13 +69768,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71713,32 +69802,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( @@ -71823,7 +69912,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71849,9 +69940,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71933,7 +70022,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71963,9 +70054,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72043,7 +70132,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72077,9 +70168,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72099,70 +70188,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y435200 ( @@ -72185,9 +70274,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72271,7 +70358,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72299,9 +70388,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72381,7 +70468,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72413,9 +70502,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72465,13 +70552,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72497,32 +70586,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( @@ -72607,7 +70696,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72633,9 +70724,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72717,7 +70806,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72747,9 +70838,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72827,7 +70916,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72861,9 +70952,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -72883,70 +70972,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y489600 ( @@ -72969,9 +71058,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73055,7 +71142,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73083,9 +71172,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73165,7 +71252,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73197,9 +71286,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73249,13 +71336,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73281,32 +71370,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( @@ -73391,7 +71480,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73417,9 +71508,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73501,7 +71590,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73531,9 +71622,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73611,7 +71700,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73645,9 +71736,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73667,70 +71756,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y544000 ( @@ -73753,9 +71842,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73839,7 +71926,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73867,9 +71956,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73949,7 +72036,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -73981,9 +72070,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74033,13 +72120,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74065,32 +72154,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( @@ -74175,7 +72264,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74201,9 +72292,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74285,7 +72374,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74315,9 +72406,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74395,7 +72484,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74429,9 +72520,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74451,70 +72540,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y598400 ( @@ -74537,9 +72626,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74623,7 +72710,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74651,9 +72740,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74733,7 +72820,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74765,9 +72854,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74817,13 +72904,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74849,32 +72938,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( @@ -74959,7 +73048,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -74985,9 +73076,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75069,7 +73158,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75099,9 +73190,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75179,7 +73268,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75213,9 +73304,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75235,70 +73324,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y652800 ( @@ -75321,9 +73410,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75407,7 +73494,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75435,9 +73524,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75517,7 +73604,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75549,9 +73638,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75601,13 +73688,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75633,32 +73722,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( @@ -75743,7 +73832,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75769,9 +73860,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75853,7 +73942,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75883,9 +73974,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75963,7 +74052,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -75997,9 +74088,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76019,70 +74108,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y707200 ( @@ -76105,9 +74194,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76191,7 +74278,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76219,9 +74308,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76301,7 +74388,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76333,9 +74422,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76385,13 +74472,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76417,32 +74506,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( @@ -76527,7 +74616,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76553,9 +74644,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76637,7 +74726,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76667,9 +74758,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76747,7 +74836,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76781,9 +74872,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76803,70 +74892,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y761600 ( @@ -76889,9 +74978,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -76975,7 +75062,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77003,9 +75092,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77085,7 +75172,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77117,9 +75206,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77169,13 +75256,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77201,32 +75290,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( @@ -77311,7 +75400,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77337,9 +75428,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77421,7 +75510,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77451,9 +75542,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77531,7 +75620,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77565,9 +75656,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77587,70 +75676,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y816000 ( @@ -77673,9 +75762,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77759,7 +75846,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77787,9 +75876,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77869,7 +75956,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77901,9 +75990,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77953,13 +76040,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -77985,32 +76074,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( @@ -78095,7 +76184,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78121,9 +76212,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78205,7 +76294,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78235,9 +76326,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78315,7 +76404,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78349,9 +76440,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78371,70 +76460,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y870400 ( @@ -78457,9 +76546,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78517,34 +76604,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2879600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2916400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2953200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2990000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3026800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3063600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3100400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3137200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3174000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3210800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3247600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3284400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3321200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y870400 ( @@ -78571,9 +76660,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78653,7 +76740,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78685,9 +76774,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78737,13 +76824,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78769,32 +76858,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( @@ -78825,7 +76914,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78849,9 +76940,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78881,7 +76970,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78907,38 +76998,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2888800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2925600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2962400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y897600 ( @@ -78965,9 +77058,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -78993,7 +77084,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79023,9 +77116,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79049,7 +77140,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79103,7 +77196,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79137,9 +77232,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79159,141 +77252,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79319,32 +77424,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( @@ -79355,96 +77460,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2723200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2792200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y952000 ( @@ -79463,143 +77572,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79625,32 +77744,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1006400 ( @@ -79661,94 +77780,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1006400 ( @@ -79767,143 +77892,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -79929,32 +78064,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( @@ -79965,94 +78100,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1060800 ( @@ -80071,143 +78212,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1088000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80233,32 +78384,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1115200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1115200 ( @@ -80269,94 +78420,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1115200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1115200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1115200 ( @@ -80375,143 +78532,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80537,32 +78704,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1169600 ( @@ -80573,94 +78740,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1169600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1169600 ( @@ -80679,143 +78852,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80841,32 +79024,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1224000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1224000 ( @@ -80877,94 +79060,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1224000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1224000 ( @@ -80983,143 +79172,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -81145,32 +79344,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1278400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1278400 ( @@ -81181,94 +79380,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1278400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1278400 ( @@ -81287,143 +79492,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -81449,32 +79664,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1332800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1332800 ( @@ -81485,94 +79700,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1332800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1332800 ( @@ -81591,143 +79812,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -81753,32 +79984,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1387200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1387200 ( @@ -81789,94 +80020,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1387200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1387200 ( @@ -81895,143 +80132,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82057,32 +80304,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1441600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1441600 ( @@ -82093,94 +80340,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1441600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1441600 ( @@ -82199,143 +80452,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82361,32 +80624,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1496000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1496000 ( @@ -82397,94 +80660,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1496000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1496000 ( @@ -82503,143 +80772,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82665,32 +80944,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1550400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1550400 ( @@ -82701,94 +80980,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1550400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1550400 ( @@ -82807,143 +81092,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -82969,32 +81264,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1604800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1604800 ( @@ -83005,94 +81300,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1604800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1604800 ( @@ -83111,143 +81412,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83273,32 +81584,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1659200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1659200 ( @@ -83309,94 +81620,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1659200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1659200 ( @@ -83415,143 +81732,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83577,32 +81904,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1713600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1713600 ( @@ -83613,94 +81940,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1713600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1713600 ( @@ -83719,143 +82052,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -83881,32 +82224,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1768000 ( @@ -83917,102 +82260,108 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1768000 ( @@ -84031,94 +82380,96 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2042400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2079200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2116000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2152800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2162000y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2180400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2217200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2254000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2290800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2327600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y1795200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1795200 ( @@ -84143,61 +82494,59 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84225,93 +82574,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84337,32 +82686,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1822400 ( @@ -84373,51 +82722,43 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2143600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2162000y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2185000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2221800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2258600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2295400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2332200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84443,9 +82784,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84457,48 +82796,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1822400 ( @@ -84527,9 +82864,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84539,80 +82874,78 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1822400 ( @@ -84631,143 +82964,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -84793,138 +83136,146 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1876800 ( @@ -84943,72 +83294,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1904000 ( @@ -85029,84 +83378,86 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3371800y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3436200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3473000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3808800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3509800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3546600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3583400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3620200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3657000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3693800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3730600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3767400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3804200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y1904000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1904000 ( @@ -85133,9 +83484,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85185,13 +83534,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85217,32 +83568,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1931200 ( @@ -85273,7 +83624,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85295,80 +83648,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3698400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3749000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3785800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3371800y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3795000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1931200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y1931200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1931200 ( @@ -85417,7 +83778,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85451,9 +83814,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85473,143 +83834,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85635,32 +84006,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1985600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1985600 ( @@ -85671,94 +84042,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1985600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1985600 ( @@ -85777,143 +84154,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85939,32 +84326,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2040000 ( @@ -85975,94 +84362,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2040000 ( @@ -86081,143 +84474,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86243,32 +84646,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2094400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2094400 ( @@ -86279,94 +84682,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2094400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2094400 ( @@ -86385,143 +84794,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86547,32 +84966,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2148800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2148800 ( @@ -86583,94 +85002,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2148800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2148800 ( @@ -86689,143 +85114,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -86851,32 +85286,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2203200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2203200 ( @@ -86887,94 +85322,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2203200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2203200 ( @@ -86993,143 +85434,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87155,32 +85606,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2257600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2257600 ( @@ -87191,94 +85642,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2257600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2257600 ( @@ -87297,143 +85754,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87459,32 +85926,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2312000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2312000 ( @@ -87495,94 +85962,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2312000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2312000 ( @@ -87601,143 +86074,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -87763,32 +86246,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2366400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2366400 ( @@ -87799,94 +86282,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2366400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2366400 ( @@ -87905,143 +86394,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88067,32 +86566,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2420800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2420800 ( @@ -88103,94 +86602,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2420800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2420800 ( @@ -88209,143 +86714,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88371,32 +86886,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2475200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2475200 ( @@ -88407,94 +86922,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2475200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2475200 ( @@ -88513,143 +87034,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88675,32 +87206,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2529600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2529600 ( @@ -88711,94 +87242,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2529600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2529600 ( @@ -88817,143 +87354,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -88979,32 +87526,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2584000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2584000 ( @@ -89015,94 +87562,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2584000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2584000 ( @@ -89121,143 +87674,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89283,32 +87846,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2638400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2638400 ( @@ -89319,94 +87882,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2638400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2638400 ( @@ -89425,143 +87994,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89587,138 +88166,146 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2692800 ( @@ -89737,72 +88324,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2720000 ( @@ -89823,33 +88408,27 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3229200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89875,34 +88454,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2720000 ( @@ -89929,9 +88508,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -89981,13 +88558,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90013,32 +88592,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2747200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2747200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2747200 ( @@ -90069,7 +88648,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90091,80 +88672,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3229200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3808800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y2747200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2747200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2747200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2747200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2747200 ( @@ -90213,7 +88802,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90247,9 +88838,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90269,143 +88858,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90431,32 +89030,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2801600 ( @@ -90467,102 +89066,108 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2801600 ( @@ -90581,93 +89186,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90693,61 +89298,59 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90775,93 +89378,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2828800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -90887,32 +89490,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2856000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2856000 ( @@ -90923,52 +89526,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2856000 ( @@ -90993,9 +89594,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91007,48 +89606,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2856000 ( @@ -91077,9 +89674,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91089,80 +89684,78 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2856000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2856000 ( @@ -91181,143 +89774,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91343,32 +89946,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2910400 ( @@ -91379,94 +89982,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2910400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2910400 ( @@ -91485,143 +90094,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91647,32 +90266,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2964800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2964800 ( @@ -91683,94 +90302,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2964800 ( @@ -91789,143 +90414,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -91951,32 +90586,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3019200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3019200 ( @@ -91987,94 +90622,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3019200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3019200 ( @@ -92093,143 +90734,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92255,32 +90906,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3073600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3073600 ( @@ -92291,94 +90942,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3073600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3073600 ( @@ -92397,143 +91054,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92559,32 +91226,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3128000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3128000 ( @@ -92595,94 +91262,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3128000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3128000 ( @@ -92701,143 +91374,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92863,32 +91546,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3182400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3182400 ( @@ -92899,94 +91582,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3182400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3182400 ( @@ -93005,143 +91694,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93167,32 +91866,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3236800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3236800 ( @@ -93203,94 +91902,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3236800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3236800 ( @@ -93309,143 +92014,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93471,32 +92186,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3291200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3291200 ( @@ -93507,94 +92222,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3291200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3291200 ( @@ -93613,143 +92334,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -93775,32 +92506,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3345600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3345600 ( @@ -93811,94 +92542,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3345600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3345600 ( @@ -93917,143 +92654,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94079,32 +92826,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3400000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3400000 ( @@ -94115,94 +92862,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3400000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3400000 ( @@ -94221,143 +92974,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94383,32 +93146,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3454400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3454400 ( @@ -94419,94 +93182,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3454400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3454400 ( @@ -94525,143 +93294,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94687,32 +93466,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3508800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3508800 ( @@ -94723,94 +93502,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3508800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3508800 ( @@ -94829,143 +93614,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94991,32 +93786,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3563200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3563200 ( @@ -95027,94 +93822,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3563200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3563200 ( @@ -95133,143 +93934,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95295,32 +94106,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3617600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3617600 ( @@ -95331,94 +94142,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3617600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3617600 ( @@ -95437,143 +94254,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95599,32 +94426,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3672000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3672000 ( @@ -95635,94 +94462,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3672000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3672000 ( @@ -95741,143 +94574,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -95903,32 +94746,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3726400 ( @@ -95939,102 +94782,108 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3726400 ( @@ -96053,94 +94902,96 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2042400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2079200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2116000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2152800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2189600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2226400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2263200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2300000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2336800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2355200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y3753600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3753600 ( @@ -96165,61 +95016,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3781200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3799600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3808800y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3850200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96247,93 +95098,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96359,32 +95210,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3780800 ( @@ -96395,52 +95246,48 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1978000y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y3780800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3780800 ( @@ -96465,59 +95312,53 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2856600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2875000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2884200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2925600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2962400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4002000y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4337800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96547,90 +95388,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4917400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4935800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4945000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3780800 ( @@ -96649,143 +95488,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -96811,138 +95660,146 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3835200 ( @@ -96961,72 +95818,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3862400 ( @@ -97047,31 +95902,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97093,40 +95948,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3730600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3767400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3804200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3862400 ( @@ -97153,9 +96008,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97205,13 +96058,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97237,32 +96092,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3889600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3889600 ( @@ -97293,7 +96148,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97315,74 +96172,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3698400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y3889600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3889600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3795000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3889600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3889600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3889600 ( @@ -97431,7 +96302,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3889600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97465,9 +96338,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97487,143 +96358,151 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97649,32 +96528,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3944000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3944000 ( @@ -97685,94 +96564,102 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3944000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3944000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3944000 ( @@ -97791,143 +96678,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -97953,32 +96850,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3998400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3998400 ( @@ -97989,94 +96886,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3998400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3998400 ( @@ -98095,143 +96998,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98257,32 +97170,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4052800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4052800 ( @@ -98293,94 +97206,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4052800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4052800 ( @@ -98399,143 +97318,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98561,32 +97490,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4107200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4107200 ( @@ -98597,94 +97526,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4107200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4107200 ( @@ -98703,143 +97638,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -98865,32 +97810,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4161600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4161600 ( @@ -98901,94 +97846,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4161600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4161600 ( @@ -99007,143 +97958,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99169,32 +98130,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4216000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4216000 ( @@ -99205,94 +98166,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4216000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4216000 ( @@ -99311,143 +98278,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99473,32 +98450,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4270400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4270400 ( @@ -99509,94 +98486,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4270400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4270400 ( @@ -99615,143 +98598,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99777,32 +98770,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4324800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4324800 ( @@ -99813,94 +98806,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4324800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4324800 ( @@ -99919,143 +98918,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100081,32 +99090,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4379200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4379200 ( @@ -100117,94 +99126,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4379200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4379200 ( @@ -100223,143 +99238,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100385,32 +99410,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4433600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4433600 ( @@ -100421,94 +99446,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4433600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4433600 ( @@ -100527,143 +99558,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100689,32 +99730,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4488000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4488000 ( @@ -100725,94 +99766,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4488000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4488000 ( @@ -100831,143 +99878,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -100993,32 +100050,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4542400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4542400 ( @@ -101029,94 +100086,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4542400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4542400 ( @@ -101135,143 +100198,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101297,32 +100370,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4596800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4596800 ( @@ -101333,94 +100406,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4596800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4596800 ( @@ -101439,143 +100518,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101601,138 +100690,146 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4651200 ( @@ -101751,72 +100848,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4678400 ( @@ -101837,34 +100932,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3220000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3238400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3270600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3307400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3344200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4678400 ( @@ -101889,34 +100984,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4678400 ( @@ -101943,9 +101038,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -101995,13 +101088,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102027,32 +101122,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4705600 ( @@ -102083,7 +101178,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102105,32 +101202,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3256800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3275200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4705600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4705600 ( @@ -102155,34 +101254,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4705600 ( @@ -102231,7 +101330,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102265,9 +101366,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102287,143 +101386,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102449,32 +101558,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4760000 ( @@ -102485,102 +101594,108 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4760000 ( @@ -102599,93 +101714,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102711,61 +101826,59 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102783,105 +101896,103 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4659800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4678200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4701200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4848400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4885200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4903600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -102907,32 +102018,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4814400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4814400 ( @@ -102943,52 +102054,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4814400 ( @@ -103013,9 +102122,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103027,48 +102134,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4814400 ( @@ -103085,24 +102190,20 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4659800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4678200y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4894400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4903600y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y4814400 ( @@ -103111,80 +102212,78 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4814400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4814400 ( @@ -103203,143 +102302,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103365,32 +102474,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4868800 ( @@ -103401,92 +102510,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4868800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4868800 ( @@ -103505,143 +102622,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103667,32 +102794,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4923200 ( @@ -103703,94 +102830,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4923200 ( @@ -103809,143 +102942,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -103971,32 +103114,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4977600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4977600 ( @@ -104007,94 +103150,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4977600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4977600 ( @@ -104113,143 +103262,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104275,32 +103434,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5032000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5032000 ( @@ -104311,94 +103470,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5032000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5032000 ( @@ -104417,143 +103582,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104579,32 +103754,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5086400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5086400 ( @@ -104615,94 +103790,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5086400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5086400 ( @@ -104721,143 +103902,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -104883,32 +104074,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5140800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5140800 ( @@ -104919,94 +104110,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5140800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5140800 ( @@ -105025,143 +104222,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -105187,32 +104394,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5195200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5195200 ( @@ -105223,94 +104430,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5195200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5195200 ( @@ -105329,143 +104542,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -105491,32 +104714,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5249600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5249600 ( @@ -105527,94 +104750,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5249600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5249600 ( @@ -105633,143 +104862,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -105795,32 +105034,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5304000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5304000 ( @@ -105831,94 +105070,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5304000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5304000 ( @@ -105937,143 +105182,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106099,32 +105354,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5358400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5358400 ( @@ -106135,94 +105390,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5358400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5358400 ( @@ -106241,143 +105502,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106403,32 +105674,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5412800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5412800 ( @@ -106439,94 +105710,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5412800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5412800 ( @@ -106545,143 +105822,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106707,32 +105994,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5467200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5467200 ( @@ -106743,94 +106030,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5467200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5467200 ( @@ -106849,143 +106142,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107011,32 +106314,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5521600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5521600 ( @@ -107047,94 +106350,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5521600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5521600 ( @@ -107153,143 +106462,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107315,32 +106634,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5576000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5576000 ( @@ -107351,94 +106670,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5576000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5576000 ( @@ -107457,143 +106782,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107619,32 +106954,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5630400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5630400 ( @@ -107655,94 +106990,100 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5630400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5630400 ( @@ -107761,143 +107102,153 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107923,138 +107274,146 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5684800 ( @@ -108073,70 +107432,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5712000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5712000 ( @@ -108159,9 +107518,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108191,7 +107548,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108217,9 +107576,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108247,7 +107604,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108275,9 +107634,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108303,7 +107660,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108333,9 +107692,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108359,7 +107716,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108391,9 +107750,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108443,13 +107800,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108475,32 +107834,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5739200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5739200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5739200 ( @@ -108585,7 +107944,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108611,9 +107972,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108695,7 +108054,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108725,9 +108086,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108805,7 +108164,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108839,9 +108200,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108861,70 +108220,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5766400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5766400 ( @@ -108947,9 +108306,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109033,7 +108390,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109061,9 +108420,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109143,7 +108500,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109175,9 +108534,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109227,13 +108584,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109259,32 +108618,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5793600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5793600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5793600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5793600 ( @@ -109369,7 +108728,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109395,9 +108756,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109479,7 +108838,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109509,9 +108870,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109589,7 +108948,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109623,9 +108984,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109645,70 +109004,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5820800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5820800 ( @@ -109731,9 +109090,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109817,7 +109174,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109845,9 +109204,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109927,7 +109284,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109959,9 +109318,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110011,13 +109368,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110043,32 +109402,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5848000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5848000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5848000 ( @@ -110153,7 +109512,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110179,9 +109540,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110263,7 +109622,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110293,9 +109654,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110373,7 +109732,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110407,9 +109768,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110429,70 +109788,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5875200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5875200 ( @@ -110515,9 +109874,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110601,7 +109958,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5875200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110629,9 +109988,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110711,7 +110068,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5875200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110743,9 +110102,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110795,13 +110152,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5875200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110827,32 +110186,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5902400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5902400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5902400 ( @@ -110937,7 +110296,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110963,9 +110324,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111047,7 +110406,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111077,9 +110438,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111157,7 +110516,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111191,9 +110552,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111213,70 +110572,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5929600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5929600 ( @@ -111299,9 +110658,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111385,7 +110742,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111413,9 +110772,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111495,7 +110852,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111527,9 +110886,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111579,13 +110936,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111611,32 +110970,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5956800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5956800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5956800 ( @@ -111721,7 +111080,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111747,9 +111108,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111831,7 +111190,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111861,9 +111222,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111941,7 +111300,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111975,9 +111336,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111997,70 +111356,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5984000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5984000 ( @@ -112083,9 +111442,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112169,7 +111526,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112197,9 +111556,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112279,7 +111636,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112311,9 +111670,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112363,13 +111720,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5984000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112395,32 +111754,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6011200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6011200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6011200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6011200 ( @@ -112505,7 +111864,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112531,9 +111892,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112615,7 +111974,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112645,9 +112006,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112725,7 +112084,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112759,9 +112120,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112781,70 +112140,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6038400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6038400 ( @@ -112867,9 +112226,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112953,7 +112310,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112981,9 +112340,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113063,7 +112420,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113095,9 +112454,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113147,13 +112504,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113179,32 +112538,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6065600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6065600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6065600 ( @@ -113289,7 +112648,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113315,9 +112676,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113399,7 +112758,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113429,9 +112790,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113509,7 +112868,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113543,9 +112904,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113565,70 +112924,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6092800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6092800 ( @@ -113651,9 +113010,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113737,7 +113094,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113765,9 +113124,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113847,7 +113204,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113879,9 +113238,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113931,13 +113288,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113963,32 +113322,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6120000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6120000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6120000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6120000 ( @@ -114073,7 +113432,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114099,9 +113460,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114183,7 +113542,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114213,9 +113574,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114293,7 +113652,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114327,9 +113688,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114349,70 +113708,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6147200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6147200 ( @@ -114435,9 +113794,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114521,7 +113878,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114549,9 +113908,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114631,7 +113988,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114663,9 +114022,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114715,13 +114072,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114747,32 +114106,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6174400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6174400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6174400 ( @@ -114857,7 +114216,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114883,9 +114244,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114967,7 +114326,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114997,9 +114358,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115077,7 +114436,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115111,9 +114472,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115133,70 +114492,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6201600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6201600 ( @@ -115219,9 +114578,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115305,7 +114662,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6201600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115333,9 +114692,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115415,7 +114772,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6201600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115447,9 +114806,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115499,13 +114856,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6201600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115531,32 +114890,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6228800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6228800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6228800 ( @@ -115641,7 +115000,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115667,9 +115028,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115751,7 +115110,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115781,9 +115142,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115861,7 +115220,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115895,9 +115256,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115917,70 +115276,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6256000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6256000 ( @@ -116003,9 +115362,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116089,7 +115446,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116117,9 +115476,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116199,7 +115556,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116231,9 +115590,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116283,13 +115640,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116315,32 +115674,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6283200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6283200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6283200 ( @@ -116425,7 +115784,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116451,9 +115812,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116535,7 +115894,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116565,9 +115926,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116645,7 +116004,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116679,9 +116040,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116701,70 +116060,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6310400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6310400 ( @@ -116787,9 +116146,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116873,7 +116230,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116901,9 +116260,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116983,7 +116340,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117015,9 +116374,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117067,13 +116424,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6310400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117099,32 +116458,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6337600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6337600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6337600 ( @@ -117209,7 +116568,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117235,9 +116596,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117319,7 +116678,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117349,9 +116710,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117429,7 +116788,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117463,9 +116824,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117485,70 +116844,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6364800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6364800 ( @@ -117571,9 +116930,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117657,7 +117014,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117685,9 +117044,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117767,7 +117124,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117799,9 +117158,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117851,13 +117208,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117883,32 +117242,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6392000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6392000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6392000 ( @@ -117993,7 +117352,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118019,9 +117380,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118103,7 +117462,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118133,9 +117494,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118213,7 +117572,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118247,9 +117608,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118269,70 +117628,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6419200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6419200 ( @@ -118355,9 +117714,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118441,7 +117798,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118469,9 +117828,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118551,7 +117908,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118583,9 +117942,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118635,13 +117992,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118667,32 +118026,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6446400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6446400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6446400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6446400 ( @@ -118777,7 +118136,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118803,9 +118164,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118887,7 +118246,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118917,9 +118278,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118997,7 +118356,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119031,9 +118392,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119053,70 +118412,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6473600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6473600 ( @@ -119139,9 +118498,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119225,7 +118582,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119253,9 +118612,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119335,7 +118692,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119367,9 +118726,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119419,13 +118776,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6473600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119451,32 +118810,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6500800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6500800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6500800 ( @@ -119561,7 +118920,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119587,9 +118948,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119671,7 +119030,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119701,9 +119062,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119781,7 +119140,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119815,9 +119176,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119837,70 +119196,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6528000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6528000 ( @@ -119923,9 +119282,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120009,7 +119366,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120037,9 +119396,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120119,7 +119476,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120151,9 +119510,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120203,13 +119560,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6528000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120235,32 +119594,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6555200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6555200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6555200 ( @@ -120345,7 +119704,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120371,9 +119732,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120455,7 +119814,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120485,9 +119846,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120565,7 +119924,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120599,9 +119960,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120621,70 +119980,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6582400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6582400 ( @@ -120707,9 +120066,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120793,7 +120150,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120821,9 +120180,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120903,7 +120260,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120935,9 +120294,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120987,13 +120344,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121019,32 +120378,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6609600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6609600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6609600 ( @@ -121129,7 +120488,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121155,9 +120516,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121239,7 +120598,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121269,9 +120630,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121349,7 +120708,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121383,9 +120744,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121405,70 +120764,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6636800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6636800 ( @@ -121491,9 +120850,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121577,7 +120934,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121605,9 +120964,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121687,7 +121044,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121719,9 +121078,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121771,13 +121128,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121803,32 +121162,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6664000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6664000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6664000 ( @@ -121913,7 +121272,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121939,9 +121300,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122023,7 +121382,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122053,9 +121414,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122133,7 +121492,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122167,9 +121528,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122189,70 +121548,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6691200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6691200 ( @@ -122275,9 +121634,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122361,7 +121718,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122389,9 +121748,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122471,7 +121828,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122503,9 +121862,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122555,13 +121912,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122587,32 +121946,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6718400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6718400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6718400 ( @@ -122697,7 +122056,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122723,9 +122084,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122807,7 +122166,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122837,9 +122198,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122917,7 +122276,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122951,9 +122312,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122973,70 +122332,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6745600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6745600 ( @@ -123059,9 +122418,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123145,7 +122502,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123173,9 +122532,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123255,7 +122612,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123287,9 +122646,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123339,13 +122696,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6745600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123371,32 +122730,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6772800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6772800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6772800 ( @@ -123481,7 +122840,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123507,9 +122868,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123591,7 +122950,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123621,9 +122982,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123701,7 +123060,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123735,9 +123096,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123757,70 +123116,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6800000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6800000 ( @@ -123843,9 +123202,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123929,7 +123286,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123957,9 +123316,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124039,7 +123396,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124071,9 +123430,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124123,13 +123480,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124155,32 +123514,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6827200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6827200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6827200 ( @@ -124265,7 +123624,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124291,9 +123652,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124375,7 +123734,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124405,9 +123766,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124485,7 +123844,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124519,9 +123880,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124541,70 +123900,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6854400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6854400 ( @@ -124627,9 +123986,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124713,7 +124070,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124741,9 +124100,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124823,7 +124180,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124855,9 +124214,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124907,13 +124264,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124939,32 +124298,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6881600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6881600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6881600 ( @@ -125049,7 +124408,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125075,9 +124436,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125159,7 +124518,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125189,9 +124550,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125269,7 +124628,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125303,9 +124664,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125325,70 +124684,70 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6908800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6908800 ( @@ -125411,9 +124770,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125497,7 +124854,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125525,9 +124884,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125607,7 +124964,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125639,9 +124998,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125691,13 +125048,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125717,16 +125076,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6936000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6936000 ( @@ -125747,9 +125106,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125781,7 +125138,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125805,9 +125164,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125837,7 +125194,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125863,9 +125222,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125893,7 +125250,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125921,9 +125280,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125949,7 +125306,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -125979,9 +125338,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126005,7 +125362,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126037,9 +125396,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126061,7 +125418,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -126089,15 +125448,15 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef index f8a4092..eab5854 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:704815829c6833cb52fc685dd119fcf6b96477b477ad8f8280fb7a55bd85dd6f -size 1055555 +oid sha256:ad7028f4236a5f0252023af986dabc7c8277ce1ce99e713a37d5f350a2224ae1 +size 1100855 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v index 4bb92e9..ea250cb 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v @@ -36,19 +36,20 @@ assign out[0] = in[0] ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -63,21 +64,12 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -wire aps_rename_1_ ; - assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -103,10 +95,9 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -139,168 +130,160 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -408,10 +391,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -431,10 +411,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -659,189 +638,180 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1324,8 +1294,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - prog_clk__FEEDTHRU_1 ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1356,26 +1325,34 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1385,21 +1362,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1415,229 +1384,212 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -1645,280 +1597,275 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1937,10 +1884,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1960,10 +1904,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -2025,10 +1968,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2048,10 +1988,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -2201,7 +2140,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -2221,9 +2163,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -2272,171 +2215,163 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -2864,9 +2799,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -2892,25 +2825,31 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -2919,21 +2858,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -2943,350 +2874,335 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) ) ; endmodule @@ -3298,19 +3214,18 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3334,9 +3249,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -3364,10 +3282,9 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -3403,21 +3320,20 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3441,6 +3357,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -3470,8 +3388,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -3480,7 +3396,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3495,11 +3411,10 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , @@ -3507,230 +3422,222 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) ) ; endmodule @@ -3742,19 +3649,18 @@ assign out[0] = in[0] ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -3769,12 +3675,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_1_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -3800,10 +3710,9 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -3836,169 +3745,161 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4281,7 +4182,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -4301,9 +4205,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -4352,190 +4257,181 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -4870,6 +4766,58 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -4904,54 +4852,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -5015,7 +4915,7 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -5050,26 +4950,36 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -5079,21 +4989,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -5111,541 +5013,530 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) ) ; + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -5753,7 +5644,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -5773,9 +5667,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -5971,6 +5866,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -5994,174 +5891,166 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -6443,7 +6332,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6469,9 +6361,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -6545,6 +6438,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6574,8 +6469,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6617,22 +6510,30 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -6641,21 +6542,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -6673,393 +6566,368 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) ) ; + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7077,11 +6945,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -7107,10 +6973,9 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7142,18 +7007,17 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7170,8 +7034,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -7197,11 +7062,9 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7225,27 +7088,25 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7259,11 +7120,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_3_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) ) ; endmodule @@ -7289,11 +7155,9 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7317,32 +7181,30 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7350,19 +7212,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7372,6 +7236,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -7380,12 +7245,11 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7409,27 +7273,28 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -7446,9 +7311,8 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -7474,11 +7338,9 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7502,11 +7364,10 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule @@ -7519,23 +7380,22 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7543,19 +7403,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7565,6 +7427,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -7573,12 +7436,11 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -7602,9 +7464,11 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; @@ -7612,126 +7476,120 @@ endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -7753,10 +7611,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -7782,10 +7637,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -8060,7 +7914,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -8100,34 +7954,37 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -8135,437 +7992,448 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , + .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , + .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , + .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , + .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , + .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -8644,408 +8512,386 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9439,11 +9285,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -9515,85 +9365,85 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9642,10 +9492,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9656,10 +9503,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -9674,10 +9520,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9688,10 +9531,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -9708,6 +9550,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9722,84 +9566,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -9925,7 +9761,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9939,9 +9778,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule @@ -9986,54 +9826,65 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -10058,34 +9909,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -10098,546 +9938,502 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10693,13 +10489,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -10753,96 +10549,91 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -10963,82 +10754,78 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11084,8 +10871,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -11097,6 +10882,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) ) ; endmodule @@ -11140,6 +10929,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -11151,27 +10942,24 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11194,8 +10982,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11222,61 +11008,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11368,6 +11153,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11385,139 +11172,130 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11538,6 +11316,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11558,8 +11338,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11578,6 +11356,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11598,8 +11378,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11658,6 +11436,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11678,8 +11458,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11736,7 +11514,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11753,9 +11534,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -11800,42 +11582,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -11978,63 +11758,60 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12056,6 +11833,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12079,8 +11858,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12173,42 +11950,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -12232,6 +12007,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12261,8 +12038,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12331,7 +12106,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -12369,86 +12145,92 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -12457,86 +12239,77 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -12545,8 +12318,8 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -12555,587 +12328,538 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) ) ; + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) ) ; + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) ) ; + .X ( ropt_net_144 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13237,6 +12961,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -13248,348 +12974,328 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -13603,55 +13309,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13671,7 +13337,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13686,11 +13372,27 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -13701,13 +13403,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13719,15 +13421,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -13757,13 +13455,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13775,11 +13473,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -13793,13 +13495,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13813,13 +13515,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -13984,34 +13686,32 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14066,38 +13766,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14168,38 +13866,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14308,46 +14004,56 @@ output [0:19] chany_top_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -14368,33 +14074,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; @@ -14403,465 +14099,399 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14903,18 +14533,17 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -14929,114 +14558,108 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15052,6 +14675,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -15060,8 +14685,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15122,18 +14745,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -15146,18 +14765,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -15186,58 +14801,55 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15254,8 +14866,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -15267,6 +14877,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15310,8 +14922,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -15323,24 +14933,25 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15378,153 +14989,145 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15662,6 +15265,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -15681,7 +15285,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15778,10 +15385,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15798,10 +15402,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -15846,43 +15449,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -15976,43 +15577,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16154,64 +15753,61 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16361,22 +15957,21 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -16448,9 +16043,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , + clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -16490,33 +16085,55 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -16524,35 +16141,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -16562,22 +16166,19 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -16586,55 +16187,51 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -16644,8 +16241,8 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -16654,545 +16251,528 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -17331,7 +16911,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -17348,259 +16931,248 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18231,92 +17803,88 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18335,7 +17903,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -18389,12 +17956,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; endmodule @@ -18469,8 +18033,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) ) ; endmodule @@ -18574,6 +18140,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -18621,174 +18189,164 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -18874,8 +18432,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18911,6 +18467,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19291,7 +18849,8 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -19340,33 +18899,51 @@ output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -19380,21 +18957,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -19404,29 +18973,23 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -19434,7 +18997,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , @@ -19443,8 +19006,8 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -19452,8 +19015,8 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -19461,8 +19024,8 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -19470,8 +19033,8 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -19479,8 +19042,8 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -19488,8 +19051,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -19497,54 +19061,46 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -19554,9 +19110,8 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -19566,8 +19121,8 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -19577,9 +19132,8 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -19589,39 +19143,34 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , @@ -19629,508 +19178,488 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20200,39 +19729,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20310,43 +19837,41 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20426,6 +19951,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20458,24 +19985,21 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20501,120 +20025,113 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20788,39 +20305,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -20882,172 +20397,163 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21185,10 +20691,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21205,10 +20708,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -21413,64 +20915,61 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -21618,11 +21117,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -21658,38 +21153,48 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -21698,40 +21203,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -21742,19 +21232,14 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , @@ -21762,271 +21247,249 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -22034,9 +21497,8 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -22044,565 +21506,508 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22696,11 +22101,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -22734,13 +22143,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22752,15 +22161,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -22792,15 +22197,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -22894,13 +22295,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -22965,34 +22366,32 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23047,38 +22446,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23149,38 +22546,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23287,42 +22682,48 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -23341,21 +22742,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; @@ -23366,474 +22761,427 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -23903,11 +23251,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -23941,98 +23293,93 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24159,57 +23506,54 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24336,133 +23680,126 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24480,34 +23817,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -24524,6 +23833,34 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; @@ -24592,8 +23929,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -24605,6 +23940,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -24648,8 +23985,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -24661,99 +23996,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24900,8 +24232,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24916,137 +24246,134 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -25102,8 +24429,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -25121,6 +24446,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; endmodule @@ -25174,44 +24503,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -25234,6 +24525,38 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -25334,18 +24657,45 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -25353,33 +24703,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -25388,34 +24726,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -25424,11 +24750,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -25437,613 +24760,556 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26143,7 +25409,10 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26151,281 +25420,266 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -26441,66 +25695,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -26511,6 +25705,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -26581,13 +25831,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26601,26 +25851,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -26631,6 +25861,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -26661,13 +25911,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26771,38 +26021,42 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:0] ccff_tail ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -26819,13 +26073,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -26834,392 +26084,332 @@ wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) ) ; endmodule module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , + .X ( net_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27241,12 +26431,13 @@ endmodule module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27254,11 +26445,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , - .X ( BUF_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , - .X ( p_abuf0 ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -27276,8 +26465,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -27297,12 +26486,9 @@ output p_abuf2 ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , - .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; endmodule @@ -27322,18 +26508,17 @@ endmodule module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27354,49 +26539,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -27437,7 +26621,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -27522,13 +26706,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , @@ -27551,16 +26735,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -27568,16 +26753,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -27593,8 +26769,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -27611,12 +26787,11 @@ grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -27638,7 +26813,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -27655,19 +26831,20 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -27690,7 +26867,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( fabric_regout[0] ) , + .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { @@ -27698,36 +26875,34 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; @@ -27769,7 +26944,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p_abuf4 , p0 ) ; + p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -27786,7 +26961,8 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; -output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; input p0 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -27796,17 +26972,17 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , - .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , + .p_abuf6 ( p_abuf6 ) , .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf2 } ) ) ; grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; @@ -27832,61 +27008,76 @@ endmodule module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -27895,10 +27086,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , + .X ( BUF_net_89 ) ) ; endmodule -module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -27914,27 +27109,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -27969,81 +27145,79 @@ endmodule module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28081,10 +27255,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -28173,9 +27347,9 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , @@ -28198,16 +27372,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -28215,33 +27390,24 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -28258,12 +27424,11 @@ grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -28285,7 +27450,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -28299,20 +27464,21 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -28323,7 +27489,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -28341,36 +27507,34 @@ grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -28411,7 +27575,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -28425,9 +27590,10 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; -output p_abuf3 ; input p0 ; +input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -28435,11 +27601,11 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; + .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; @@ -28471,51 +27637,48 @@ endmodule module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28550,28 +27713,30 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -28606,17 +27771,16 @@ endmodule module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28638,48 +27802,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -28714,17 +27877,17 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( @@ -28835,16 +27998,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -28852,16 +28016,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -28877,8 +28032,8 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -28895,12 +28050,11 @@ grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -28922,7 +28076,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -28936,19 +28090,20 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -28977,36 +28132,34 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -29047,7 +28200,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29061,6 +28214,7 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p3 ; @@ -29070,101 +28224,101 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_2_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -29185,8 +28339,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -29205,7 +28359,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -29240,17 +28394,16 @@ endmodule module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29272,49 +28425,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29440,13 +28592,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , @@ -29469,16 +28621,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -29486,16 +28639,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -29511,8 +28655,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -29529,12 +28673,11 @@ grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -29578,13 +28721,13 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -29613,36 +28756,34 @@ grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -29745,52 +28886,49 @@ endmodule module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29812,25 +28950,6 @@ endmodule module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; @@ -29846,8 +28965,26 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule @@ -29882,17 +29019,16 @@ endmodule module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29914,48 +29050,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -29988,22 +29123,22 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -30086,7 +29221,7 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , @@ -30111,16 +29246,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -30128,16 +29264,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -30153,8 +29280,8 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -30171,12 +29298,11 @@ grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -30198,7 +29324,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30212,20 +29338,20 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -30254,36 +29380,34 @@ grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -30324,7 +29448,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30338,8 +29462,8 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -30348,11 +29472,11 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; @@ -30384,52 +29508,49 @@ endmodule module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30450,42 +29571,45 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; output p_abuf1 ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -30520,80 +29644,78 @@ endmodule module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -30626,11 +29748,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , @@ -30720,13 +29842,13 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , @@ -30749,16 +29871,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -30766,33 +29889,24 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -30809,12 +29923,11 @@ grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -30836,7 +29949,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30852,19 +29965,19 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -30875,7 +29988,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , @@ -30893,36 +30006,35 @@ grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -30963,8 +30075,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p2 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30980,7 +30092,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p0 ; +output p_abuf3 ; input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -30990,87 +30102,87 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31105,25 +30217,28 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; +output p_abuf1 ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -31158,17 +30273,16 @@ endmodule module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31190,49 +30304,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31266,7 +30379,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; @@ -31387,16 +30500,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -31404,16 +30518,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -31429,8 +30534,8 @@ input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -31447,12 +30552,11 @@ grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -31474,7 +30578,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31488,6 +30592,7 @@ output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -31495,13 +30600,13 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -31530,36 +30635,34 @@ grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -31600,7 +30703,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31614,6 +30718,7 @@ output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; output p_abuf2 ; input p0 ; input p1 ; @@ -31624,141 +30729,147 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_2_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_regout ) ) ; grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p4 ) ; +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; output p_abuf1 ; -input p4 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , + .X ( p_abuf0 ) ) ; endmodule @@ -31801,17 +30912,16 @@ endmodule module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31833,49 +30943,48 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , endmodule -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -output [0:16] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -31916,7 +31025,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -32030,16 +31139,17 @@ output [0:1] frac_lut4_lut3_out ; output [0:0] frac_lut4_lut4_out ; output [0:0] ccff_tail ; +wire [0:15] frac_lut4_0__undriven_sram_inv ; wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( frac_lut4_0__undriven_sram_inv ) , .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -32047,16 +31157,7 @@ grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfx frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; endmodule @@ -32072,8 +31173,8 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , @@ -32090,12 +31191,11 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; + .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; @@ -32117,7 +31217,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32133,19 +31233,20 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_fabric_out_0_undriven_sram_inv ; +wire [0:1] mux_fabric_out_1_undriven_sram_inv ; +wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; wire [0:0] mux_tree_size2_2_out ; wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; wire [0:0] mux_tree_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_size2_mem_1_ccff_tail ; @@ -32174,36 +31275,35 @@ grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; + .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; + .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , + .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p1 ( p1 ) ) ; + .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_size2_0_sram ) ) ; grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_size2_1_sram ) ) ; grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_size2_2_sram ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; @@ -32244,8 +31344,8 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , - p4 ) ; + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32261,8 +31361,9 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +output p_abuf3 ; +input p0 ; input p1 ; -input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -32271,13 +31372,13 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf2 } ) ) ; + .out ( { p_abuf3 } ) ) ; grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; @@ -32313,9 +31414,9 @@ module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , - p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , p_abuf18 , - p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , p_abuf30 , - p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; + p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , p_abuf19 , + p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , p_abuf31 , + p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32346,26 +31447,25 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf3 ; output p_abuf5 ; -output p_abuf6 ; -output p_abuf8 ; -output p_abuf10 ; -output p_abuf12 ; -output p_abuf14 ; -output p_abuf16 ; -output p_abuf18 ; -output p_abuf20 ; -output p_abuf22 ; -output p_abuf24 ; -output p_abuf26 ; -output p_abuf28 ; -output p_abuf30 ; +output p_abuf7 ; +output p_abuf9 ; +output p_abuf11 ; +output p_abuf13 ; +output p_abuf15 ; +output p_abuf17 ; +output p_abuf19 ; +output p_abuf21 ; +output p_abuf23 ; +output p_abuf25 ; +output p_abuf27 ; +output p_abuf29 ; output p_abuf31 ; +output p_abuf33 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; -input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -32391,7 +31491,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , @@ -32399,10 +31499,10 @@ grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , - .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf3 ( p_abuf6 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32411,10 +31511,11 @@ grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf6 ) , .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , + .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32423,11 +31524,11 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , - .p0 ( p0 ) , .p2 ( p3 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , + .p_abuf3 ( p_abuf14 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32436,11 +31537,11 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf14 ) , .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , + .p_abuf0 ( p_abuf15 ) , .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32449,11 +31550,11 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf18 ) , .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , + .p_abuf0 ( p_abuf19 ) , .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32462,10 +31563,11 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf22 ) , .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf23 ) , .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , + .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32474,11 +31576,11 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf26 ) , .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , - .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf27 ) , .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , + .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .fle_clk ( clb_clk ) , @@ -32486,202 +31588,211 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , - .p0 ( p1 ) ) ; + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , + .p_abuf6 ( p_abuf34 ) , .p0 ( p1 ) ) ; grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf5 } ) ) ; + .out ( { p_abuf6 } ) ) ; grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf11 } ) ) ; -grid_clb_direct_interc direct_interc_7_ ( + .out ( { p_abuf8 } ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf15 } ) ) ; -grid_clb_direct_interc direct_interc_8_ ( + .out ( { p_abuf14 } ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf21 } ) ) ; -grid_clb_direct_interc direct_interc_12_ ( + .out ( { p_abuf12 } ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf29 } ) ) ; -grid_clb_direct_interc direct_interc_15_ ( + .out ( { p_abuf18 } ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { p_abuf30 } ) ) ; -grid_clb_direct_interc direct_interc_16_ ( + .out ( { p_abuf22 } ) ) ; +grid_clb_direct_interc direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( + .out ( { p_abuf24 } ) ) ; +grid_clb_direct_interc direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_18_ ( + .out ( { p_abuf28 } ) ) ; +grid_clb_direct_interc direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( clb_I0[2] ) ) ; -grid_clb_direct_interc direct_interc_19_ ( + .out ( { p_abuf34 } ) ) ; +grid_clb_direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( clb_I0[0] ) ) ; +grid_clb_direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , .out ( clb_I0[1] ) ) ; grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( clb_I0[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .out ( clb_I0[2] ) ) ; grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , .out ( clb_I0i ) ) ; grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , .out ( clb_regin ) ) ; grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , .out ( clb_sc_in ) ) ; grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( clb_I1[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .out ( clb_I1[0] ) ) ; grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , .out ( clb_I1[1] ) ) ; grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I1[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .out ( clb_I1[2] ) ) ; grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_I1i ) ) ; grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_I2[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .out ( clb_I2[0] ) ) ; grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , .out ( clb_I2[1] ) ) ; grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I2[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .out ( clb_I2[2] ) ) ; grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( clb_I2i ) ) ; grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( clb_I3[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .out ( clb_I3[0] ) ) ; grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , .out ( clb_I3[1] ) ) ; grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I3[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .out ( clb_I3[2] ) ) ; grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( clb_I3i ) ) ; grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( clb_I4[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .out ( clb_I4[0] ) ) ; grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , .out ( clb_I4[1] ) ) ; grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I4[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .out ( clb_I4[2] ) ) ; grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( clb_I4i ) ) ; grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( clb_I5[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .out ( clb_I5[0] ) ) ; grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , .out ( clb_I5[1] ) ) ; grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I5[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .out ( clb_I5[2] ) ) ; grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( clb_I5i ) ) ; grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( clb_I6[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( clb_I6[0] ) ) ; grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , .out ( clb_I6[1] ) ) ; grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I6[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .out ( clb_I6[2] ) ) ; grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( clb_I6i ) ) ; grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , .out ( clb_clk ) ) ; grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( clb_I7[2] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .out ( clb_I7[0] ) ) ; grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , .out ( clb_I7[1] ) ) ; grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I7[0] ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .out ( clb_I7[2] ) ) ; grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( clb_I7i ) ) ; grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , + .in ( { SYNOPSYS_UNCONNECTED_66 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , + .in ( { SYNOPSYS_UNCONNECTED_67 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , + .in ( { SYNOPSYS_UNCONNECTED_68 } ) , .out ( clb_clk ) ) ; endmodule @@ -32731,7 +31842,8 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32813,21 +31925,24 @@ output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] prog_clk__FEEDTHRU_4 ; output [0:0] Test_en__FEEDTHRU_1 ; output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf2 ; +wire ropt_net_156 ; +wire ropt_net_153 ; +wire ropt_net_151 ; wire ropt_net_150 ; -wire ropt_net_141 ; -wire ropt_net_139 ; -wire ropt_net_144 ; -wire ropt_net_140 ; -wire p_abuf15 ; -wire ropt_net_147 ; +wire ropt_net_167 ; +wire ropt_net_154 ; +wire ropt_net_168 ; +wire ropt_net_152 ; +wire ropt_net_163 ; +wire ropt_net_162 ; assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; +assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , @@ -32862,142 +31977,147 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , aps_rename_136_ , - top_width_0_height_0__pin_36_lower[0] , - top_width_0_height_0__pin_37_lower[0] , - top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , - top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , - aps_rename_144_ , aps_rename_145_ , - right_width_0_height_0__pin_44_lower[0] , - right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , - .clb_regout ( { ropt_net_153 } ) , - .clb_sc_out ( { aps_rename_155_ } ) , - .ccff_tail ( { ropt_net_149 } ) , - .p_abuf0 ( ropt_net_147 ) , .p_abuf3 ( ropt_net_150 ) , - .p_abuf5 ( p_abuf2 ) , - .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , - .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf10 ( ropt_net_141 ) , - .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , - .p_abuf14 ( ropt_net_139 ) , - .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf18 ( ropt_net_144 ) , - .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , - .p_abuf26 ( ropt_net_140 ) , - .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf30 ( p_abuf15 ) , - .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , - .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , - .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; + .clb_O ( { aps_rename_138_ , aps_rename_139_ , + top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , + aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , + top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , + aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , + aps_rename_158_ } ) , + .clb_regout ( { ropt_net_161 } ) , + .clb_sc_out ( { aps_rename_160_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_162 ) , + .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , + .p_abuf7 ( ropt_net_156 ) , + .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , + .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , + .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , + .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , + .p_abuf27 ( ropt_net_152 ) , + .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , + .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , + .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , + .p4 ( optlc_net_141 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , - .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1134 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_5138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , - .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , - .X ( aps_rename_154_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , - .X ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , - .X ( clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , - .X ( BUF_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , - .X ( prog_clk__FEEDTHRU_3[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , + .X ( aps_rename_143_ ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_6147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , + .X ( aps_rename_152_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , + .X ( aps_rename_155_ ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , + .X ( clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , + .X ( aps_rename_159_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , - .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , + .X ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , + .X ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , + .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , + .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , + .X ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , + .X ( prog_clk__FEEDTHRU_4[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , + .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , + .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , + .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , + .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; endmodule @@ -33429,7 +32549,6 @@ wire [0:0] prog_clk__FEEDTHRU_16 ; wire [0:0] prog_clk__FEEDTHRU_17 ; wire [0:0] prog_clk__FEEDTHRU_18 ; wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] prog_clk__FEEDTHRU_20 ; wire [0:0] Test_en__FEEDTHRU_1 ; wire [0:0] Test_en__FEEDTHRU_2 ; wire [0:0] Test_en__FEEDTHRU_3 ; @@ -33440,15 +32559,14 @@ wire [0:0] clk__FEEDTHRU_1 ; wire [0:0] clk__FEEDTHRU_2 ; wire [0:0] clk__FEEDTHRU_3 ; wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] clk__FEEDTHRU_5 ; +wire [0:0] clk__FEEDTHRU_6 ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , +grid_clb grid_clb_1__1_ ( + .prog_clk ( { ctsbuf_net_1921 } ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -33522,13 +32640,15 @@ grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; +grid_clb grid_clb_1__2_ ( + .prog_clk ( { ctsbuf_net_1113 } ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -33546,7 +32666,7 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -33598,18 +32718,18 @@ grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; -grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , + .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; +grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -33627,7 +32747,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -33679,18 +32799,19 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; grid_clb grid_clb_2__2_ ( .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -33708,7 +32829,7 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -33760,16 +32881,18 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; -sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +sb_0__0_ sb_0__0_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -33783,7 +32906,7 @@ sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -33802,8 +32925,8 @@ sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , .ccff_tail ( sb_0__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -33820,8 +32943,8 @@ sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , @@ -33851,18 +32974,12 @@ sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; +sb_1__1_ sb_1__1_ ( + .prog_clk ( { ctsbuf_net_2123 } ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -33905,13 +33022,14 @@ sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , .ccff_tail ( sb_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; -sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -33946,14 +33064,17 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -33975,7 +33096,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -34011,8 +33132,10 @@ sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , .ccff_tail ( sb_2__1__0_ccff_tail ) , .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , + .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -34037,10 +33160,10 @@ sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_3032 } ) , + .prog_clk ( { ctsbuf_net_2426 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -34074,12 +33197,11 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_3436 } ) , + .prog_clk ( { ctsbuf_net_2729 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -34113,11 +33235,10 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -34140,10 +33261,10 @@ cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -34166,10 +33287,10 @@ cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -34199,10 +33320,11 @@ cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; -cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_57 } ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -34232,9 +33354,12 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; -cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; +cby_0__1_ cby_0__1_ ( + .prog_clk ( { ctsbuf_net_1719 } ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -34247,9 +33372,8 @@ cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -34262,9 +33386,9 @@ cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; -cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; +cby_1__1_ cby_1__1_ ( + .prog_clk ( { ctsbuf_net_2325 } ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -34287,11 +33411,9 @@ cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -34314,11 +33436,9 @@ cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -34347,9 +33467,9 @@ cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; +cby_2__1_ cby_2__2_ ( + .prog_clk ( { ctsbuf_net_24 } ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -34378,8 +33498,7 @@ cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; @@ -34387,32 +33506,44 @@ direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , .out ( direct_interc_2_out ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , - .Y ( ctsbuf_net_57 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( - .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , +sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , + .Y ( ctsbuf_net_24 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , + .Y ( ctsbuf_net_46 ) ) ; +sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , + .Y ( ctsbuf_net_1113 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , .Y ( ctsbuf_net_1214 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , +sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( - .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , - .Y ( ctsbuf_net_1517 ) ) ; -sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , +sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , + .Y ( ctsbuf_net_1416 ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , + .Y ( ctsbuf_net_1719 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_1820 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , + .Y ( ctsbuf_net_1921 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , + .Y ( ctsbuf_net_2022 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , + .Y ( ctsbuf_net_2123 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , + .Y ( ctsbuf_net_2224 ) ) ; +sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , + .Y ( ctsbuf_net_2325 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , + .Y ( ctsbuf_net_2426 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , + .Y ( ctsbuf_net_2527 ) ) ; +sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , + .Y ( ctsbuf_net_2628 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , .Y ( ctsbuf_net_2729 ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( - .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , - .Y ( ctsbuf_net_3032 ) ) ; -sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( - .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , - .Y ( ctsbuf_net_3436 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_3537 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_2830 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv index 9003771..5a12b1a 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv @@ -1,18 +1,18 @@ | Module | Util| Area| Sites| Insts| Std_Cells |--------------------|----------|-----------------|-------|-------|------- -| sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95 -| sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138 -| sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96 -| sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150 -| sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185 -| sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140 -| sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107 -| sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151 -| sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89 -| cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140 -| cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112 -| cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104 -| cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106 -| cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95 -| cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87 -| grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52 +| sb_0__0_ | 24.99 | 8728.371200 | 6976 | 1 | 78 +| sb_0__1_ | 48.87 | 9449.062400 | 7552 | 1 | 127 +| sb_0__2_ | 29.93 | 8728.371200 | 6976 | 1 | 88 +| sb_1__0_ | 44.23 | 10970.521600 | 8768 | 1 | 135 +| sb_1__1_ | 65.73 | 11691.212800 | 9344 | 1 | 181 +| sb_1__2_ | 47.88 | 10970.521600 | 8768 | 1 | 145 +| sb_2__0_ | 36.31 | 8728.371200 | 6976 | 1 | 95 +| sb_2__1_ | 58.37 | 9449.062400 | 7552 | 1 | 146 +| sb_2__2_ | 39.94 | 8728.371200 | 6976 | 1 | 89 +| cbx_1__0_ | 56.73 | 5765.529600 | 4608 | 2 | 151 +| cbx_1__1_ | 71.12 | 5765.529600 | 4608 | 2 | 110 +| cbx_1__2_ | 74.91 | 5765.529600 | 4608 | 2 | 111 +| cby_0__1_ | 29.89 | 5044.838400 | 4032 | 2 | 103 +| cby_1__1_ | 78.17 | 5044.838400 | 4032 | 2 | 96 +| cby_2__1_ | 80.56 | 5044.838400 | 4032 | 2 | 88 +| grid_clb_1__1_ | 75.92 | 11531.059200 | 9216 | 4 | 58 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv index b071cf4..69a5c64 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv @@ -1,31 +1,32 @@ Ref Name Total Area Utilization_% Instance Count ---------------------------------------------------------------------------------------------------- - sky130_fd_sc_hd__mux2_1 33410.793600 6.86 2967 - sky130_fd_sc_hd__dfxbp_1 31285.004800 6.43 1316 - sky130_fd_sc_hd__dlymetal6s2s_1 9258.880000 1.90 740 - sky130_fd_sc_hd__dlymetal6s6s_1 9071.200000 1.86 725 - sky130_fd_sc_hd__dlygate4sd3_1 5695.462400 1.17 569 - sky130_fd_sc_hd__buf_4 2552.448000 0.52 340 - sky130_fd_sc_hd__dlygate4sd2_1 1769.196800 0.36 202 + sky130_fd_sc_hd__mux2_1 32960.361600 6.77 2927 + sky130_fd_sc_hd__dfxtp_1 25584.537600 5.25 1278 + sky130_fd_sc_hd__dlymetal6s2s_1 9484.096000 1.95 758 + sky130_fd_sc_hd__dlymetal6s6s_1 8896.032000 1.83 711 + sky130_fd_sc_hd__dlygate4sd3_1 6205.952000 1.27 620 + sky130_fd_sc_hd__buf_4 2695.084800 0.55 359 + sky130_fd_sc_hd__dlygate4sd2_1 1891.814400 0.39 216 sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64 - sky130_fd_sc_hd__mux2_8 1208.659200 0.25 46 - sky130_fd_sc_hd__dlygate4sd1_1 613.088000 0.13 70 - sky130_fd_sc_hd__buf_2 375.360000 0.08 75 - sky130_fd_sc_hd__inv_1 375.360000 0.08 100 - sky130_fd_sc_hd__conb_1 326.563200 0.07 87 + sky130_fd_sc_hd__mux2_8 814.531200 0.17 31 + sky130_fd_sc_hd__inv_1 390.374400 0.08 104 + sky130_fd_sc_hd__conb_1 330.316800 0.07 88 + sky130_fd_sc_hd__dlygate4sd1_1 289.027200 0.06 33 + sky130_fd_sc_hd__buf_6 202.694400 0.04 18 sky130_fd_sc_hd__or2_0 200.192000 0.04 32 - sky130_fd_sc_hd__buf_6 135.129600 0.03 12 + sky130_fd_sc_hd__buf_2 180.172800 0.04 36 + sky130_fd_sc_hd__clkinv_16 90.086400 0.02 3 sky130_fd_sc_hd__buf_12 80.076800 0.02 4 sky130_fd_sc_hd__buf_8 75.072000 0.02 5 - sky130_fd_sc_hd__clkbuf_1 60.057600 0.01 16 - sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1 - sky130_fd_sc_hd__clkdlybuf4s50_2 22.521600 0.00 2 - sky130_fd_sc_hd__clkinvlp_4 22.521600 0.00 3 - sky130_fd_sc_hd__clkinvlp_2 20.019200 0.00 4 - sky130_fd_sc_hd__clkinv_4 8.758400 0.00 1 - sky130_fd_sc_hd__inv_4 6.256000 0.00 1 - sky130_fd_sc_hd__clkinv_2 5.004800 0.00 1 - sky130_fd_sc_hd__inv_2 3.753600 0.00 1 -FPGA_BBOX_AREA 229900.4928 + sky130_fd_sc_hd__clkbuf_1 41.289600 0.01 11 + sky130_fd_sc_hd__mux2_4 30.028800 0.01 2 + sky130_fd_sc_hd__clkinv_8 16.265600 0.00 1 + sky130_fd_sc_hd__inv_2 15.014400 0.00 4 + sky130_fd_sc_hd__inv_4 12.512000 0.00 2 + sky130_fd_sc_hd__mux2_2 11.260800 0.00 1 + sky130_fd_sc_hd__clkinv_2 10.009600 0.00 2 + sky130_fd_sc_hd__inv_6 8.758400 0.00 1 + sky130_fd_sc_hd__clkinvlp_2 5.004800 0.00 1 +FPGA_BBOX_AREA 221972.8896 CORE_BBOX_AREA 486866.944 -FPGA_BBOX_UTIL 47.2203947368 +FPGA_BBOX_UTIL 45.5921052632 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt index 8f16ed6..ba5fec4 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt @@ -6,7 +6,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Sun Nov 8 18:28:15 2020 +Date : Mon Nov 9 18:55:42 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.162 0.000 -- 0.429 0.429 rp-+ nominal + grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.175 0.000 -- 0.370 0.370 rp-+ nominal --------------------------------------------------------------------------------------------------- Mode: full_chip @@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - sb_0__2_/mem_right_track_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 0.347 0.000 -- 4.898 4.898 rp-+ nominal + sb_0__2_/mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_/CLK 0.352 0.000 -- 4.373 4.373 rp-+ nominal --------------------------------------------------------------------------------------------------- **************************************** Report : clock timing @@ -34,7 +34,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Sun Nov 8 18:28:15 2020 +Date : Mon Nov 9 18:55:42 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.427 rp-+ nominal - grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.401 rp-+ nominal + grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.365 rp-+ nominal + grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.338 rp-+ nominal --------------------------------------------------------------------------------------------------- @@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - cby_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.374 rp-+ nominal - sb_2__0_/mem_top_track_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 0.949 0.000 2.424 rp-+ nominal + sb_0__2_/mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_/CLK 4.370 rp-+ nominal + cby_0__2_/mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 2.387 0.000 1.983 rp-+ nominal --------------------------------------------------------------------------------------------------- Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -63,7 +63,7 @@ Report : global timing -format { narrow } Design : fpga_core Version: P-2019.03-SP4 -Date : Sun Nov 8 18:28:15 2020 +Date : Mon Nov 9 18:55:42 2020 **************************************** No setup violations found. @@ -73,9 +73,9 @@ Hold violations -------------------------------------------------------------- Total reg->reg in->reg reg->out in->out -------------------------------------------------------------- -WNS -1.248 -1.248 0.000 0.000 0.000 -TNS -1.390 -1.390 0.000 0.000 0.000 -NUM 2 2 0 0 0 +WNS -0.238 -0.238 0.000 0.000 0.000 +TNS -0.598 -0.598 0.000 0.000 0.000 +NUM 3 3 0 0 0 -------------------------------------------------------------- 1 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds index 9042e43..bdbae55 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds @@ -1,3 +1,3 @@ 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100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cby_1__1__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cby_1__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c856f58946f08034f5a317ee687814d9cbbf4e35ff4059e175592e19b9edf7f3 -size 4442112 +oid sha256:083afd0679f9dcebd80cf80133f56019a10606a6ab6d9de27a818276add15461 +size 4448256 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds index dcbb030..0d7c565 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8ba610a994fea55c20cce268ef93cad632093794a1ab3a5cc8107b2075c7feb5 -size 4462592 +oid sha256:f7a9d82e4a6a6fdd64fb3651c3999a20cf0484b9461090ef5a122d79043f5225 +size 4454400 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__0__icv_in_design.gds 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--git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds index 3a3b7f0..a57125b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c23bd0ba7c739bded4092def6cd2f70546716f82bf0e30bf1afef37561bb30c4 -size 4411392 +oid sha256:fc23a072c7f392e74776929540302ce5b7d575ceb8b1bff1791c9477f3566eaa +size 4405248 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds index 9a44f88..71d6b70 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9bd943078017d06950cfa96dec21283456778eeda161feff1b6473a867889e69 -size 4560896 +oid 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b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8a6c6106d0166613a13fe9cad825083429eab5a3c9685937725a654a7b0a309e -size 4581376 +oid sha256:70804aec06b61f80095ddecf2a82b441a7fb323eedf22a9b5c79c03fa39fd35c +size 4577280 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds index fb6bf39..97c851b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1455eceae4c5e5fbed3bd7000d74bb83c8e14596164ad104608ac7756187f26f +oid sha256:b7873d74de58e1183796fcdb278e0a3d6b132927a9efdec51a1fb54f153586bc size 4444160 diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef index cb9a5d3..e8b224c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 87.04 ; + SIZE 66.24 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met3 ; - RECT 66.7 13.45 68.08 13.75 ; + RECT 64.86 13.45 66.24 13.75 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 82.13 1.38 82.43 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -475,7 +475,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -483,7 +483,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,7 +491,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -499,7 +499,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -507,7 +507,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 44.73 68.08 45.03 ; + RECT 64.86 59.69 66.24 59.99 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 56.97 68.08 57.27 ; + RECT 64.86 56.29 66.24 56.59 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,7 +547,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 59.69 68.08 59.99 ; + RECT 64.86 77.37 66.24 77.67 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -555,7 +555,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 75.33 68.08 75.63 ; + RECT 64.86 80.09 66.24 80.39 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 20.25 68.08 20.55 ; + RECT 64.86 48.13 66.24 48.43 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,7 +571,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 61.05 68.08 61.35 ; + RECT 64.86 82.13 66.24 82.43 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -579,7 +579,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 78.73 68.08 79.03 ; + RECT 64.86 73.29 66.24 73.59 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 8.69 68.08 8.99 ; + RECT 64.86 58.33 66.24 58.63 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,7 +595,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 35.21 68.08 35.51 ; + RECT 64.86 19.57 66.24 19.87 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -603,7 +603,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 52.89 68.08 53.19 ; + RECT 64.86 44.73 66.24 45.03 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 46.09 68.08 46.39 ; + RECT 64.86 71.93 66.24 72.23 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 82.81 68.08 83.11 ; + RECT 64.86 70.57 66.24 70.87 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 65.13 68.08 65.43 ; + RECT 64.86 74.65 66.24 74.95 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 16.17 68.08 16.47 ; + RECT 64.86 65.13 66.24 65.43 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 28.41 68.08 28.71 ; + RECT 64.86 27.73 66.24 28.03 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 37.93 68.08 38.23 ; + RECT 64.86 49.49 66.24 49.79 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 25.01 68.08 25.31 ; + RECT 64.86 40.65 66.24 40.95 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 69.21 68.08 69.51 ; + RECT 64.86 8.69 66.24 8.99 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 66.49 68.08 66.79 ; + RECT 64.86 50.85 66.24 51.15 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 71.25 68.08 71.55 ; + RECT 64.86 52.21 66.24 52.51 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 11.41 68.08 11.71 ; + RECT 64.86 16.85 66.24 17.15 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -715,7 +715,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -723,7 +723,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -731,7 +731,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,7 +763,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -771,7 +771,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -779,7 +779,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,7 +803,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 83.49 1.38 83.79 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -811,7 +811,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -819,7 +819,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -859,7 +859,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 76.69 68.08 76.99 ; + RECT 64.86 11.41 66.24 11.71 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 63.77 68.08 64.07 ; + RECT 64.86 66.49 66.24 66.79 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 58.33 68.08 58.63 ; + RECT 64.86 10.05 66.24 10.35 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 73.97 68.08 74.27 ; + RECT 64.86 21.61 66.24 21.91 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 23.65 68.08 23.95 ; + RECT 64.86 78.73 66.24 79.03 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 36.57 68.08 36.87 ; + RECT 64.86 15.49 66.24 15.79 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,7 +907,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 55.61 68.08 55.91 ; + RECT 64.86 33.17 66.24 33.47 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -915,7 +915,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 29.77 68.08 30.07 ; + RECT 64.86 83.49 66.24 83.79 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 26.37 68.08 26.67 ; + RECT 64.86 25.69 66.24 25.99 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 10.05 68.08 10.35 ; + RECT 64.86 34.53 66.24 34.83 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,7 +939,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 50.17 68.08 50.47 ; + RECT 64.86 39.29 66.24 39.59 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -947,7 +947,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 33.85 68.08 34.15 ; + RECT 64.86 18.21 66.24 18.51 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,7 +955,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 62.41 68.08 62.71 ; + RECT 64.86 76.01 66.24 76.31 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -963,7 +963,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 72.61 68.08 72.91 ; + RECT 64.86 69.21 66.24 69.51 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -971,7 +971,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 18.89 68.08 19.19 ; + RECT 64.86 42.01 66.24 42.31 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 39.29 68.08 39.59 ; + RECT 64.86 46.09 66.24 46.39 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 43.37 68.08 43.67 ; + RECT 64.86 29.77 66.24 30.07 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 32.49 68.08 32.79 ; + RECT 64.86 24.33 66.24 24.63 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 31.13 68.08 31.43 ; + RECT 64.86 22.97 66.24 23.27 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,7 +1011,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 17.53 68.08 17.83 ; + RECT 64.86 67.85 66.24 68.15 ; END END chanx_right_out[19] PIN bottom_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 5.97 68.08 6.27 ; + RECT 0 16.17 1.38 16.47 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_2_[0] @@ -1027,7 +1027,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 85.68 35.03 87.04 ; + RECT 11.43 85.68 11.57 87.04 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_4_[0] @@ -1035,7 +1035,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 18.89 1.38 19.19 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_6_[0] @@ -1043,7 +1043,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 64.86 5.97 66.24 6.27 ; END END bottom_grid_pin_6_[0] PIN bottom_grid_pin_8_[0] @@ -1051,15 +1051,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 0 18.47 1.36 ; + RECT 44.09 0 44.23 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_10_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + LAYER met2 ; + RECT 28.91 0 29.05 1.36 ; END END bottom_grid_pin_10_[0] PIN ccff_tail[0] @@ -1067,7 +1067,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 13.45 1.38 13.75 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1075,7 +1075,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[1] @@ -1083,7 +1083,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[1] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[2] @@ -1091,7 +1091,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[2] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[3] @@ -1099,7 +1099,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[3] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[4] @@ -1107,7 +1107,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[4] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[5] @@ -1115,7 +1115,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[5] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[1] @@ -1139,7 +1139,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; + RECT 14.19 0 14.33 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[2] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[3] @@ -1147,7 +1147,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[3] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[4] @@ -1155,7 +1155,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[4] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[5] @@ -1163,7 +1163,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[5] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1171,7 +1171,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[1] @@ -1179,7 +1179,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 27.99 0 28.13 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[1] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[2] @@ -1187,7 +1187,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[2] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[3] @@ -1195,7 +1195,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[3] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[4] @@ -1203,7 +1203,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 8.67 0 8.81 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[4] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[5] @@ -1211,7 +1211,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 0 8.81 1.36 ; + RECT 7.75 0 7.89 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[5] PIN top_width_0_height_0__pin_0_[0] @@ -1219,7 +1219,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 7.33 68.08 7.63 ; + RECT 0 17.53 1.38 17.83 ; END END top_width_0_height_0__pin_0_[0] PIN top_width_0_height_0__pin_2_[0] @@ -1227,7 +1227,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 85.68 34.11 87.04 ; + RECT 12.35 85.68 12.49 87.04 ; END END top_width_0_height_0__pin_2_[0] PIN top_width_0_height_0__pin_4_[0] @@ -1235,7 +1235,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 20.25 1.38 20.55 ; END END top_width_0_height_0__pin_4_[0] PIN top_width_0_height_0__pin_6_[0] @@ -1243,7 +1243,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 64.86 7.33 66.24 7.63 ; END END top_width_0_height_0__pin_6_[0] PIN top_width_0_height_0__pin_8_[0] @@ -1251,15 +1251,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END top_width_0_height_0__pin_8_[0] PIN top_width_0_height_0__pin_10_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; END END top_width_0_height_0__pin_10_[0] PIN top_width_0_height_0__pin_1_upper[0] @@ -1267,7 +1267,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 74.65 1.38 74.95 ; END END top_width_0_height_0__pin_1_upper[0] PIN top_width_0_height_0__pin_1_lower[0] @@ -1275,7 +1275,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 54.25 68.08 54.55 ; + RECT 64.86 63.77 66.24 64.07 ; END END top_width_0_height_0__pin_1_lower[0] PIN top_width_0_height_0__pin_3_upper[0] @@ -1283,7 +1283,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 59.69 1.38 59.99 ; END END top_width_0_height_0__pin_3_upper[0] PIN top_width_0_height_0__pin_3_lower[0] @@ -1291,7 +1291,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 51.53 68.08 51.83 ; + RECT 64.86 31.13 66.24 31.43 ; END END top_width_0_height_0__pin_3_lower[0] PIN top_width_0_height_0__pin_5_upper[0] @@ -1307,7 +1307,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 40.65 68.08 40.95 ; + RECT 64.86 43.37 66.24 43.67 ; END END top_width_0_height_0__pin_5_lower[0] PIN top_width_0_height_0__pin_7_upper[0] @@ -1315,7 +1315,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 50.17 1.38 50.47 ; END END top_width_0_height_0__pin_7_upper[0] PIN top_width_0_height_0__pin_7_lower[0] @@ -1323,7 +1323,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 67.85 68.08 68.15 ; + RECT 64.86 54.25 66.24 54.55 ; END END top_width_0_height_0__pin_7_lower[0] PIN top_width_0_height_0__pin_9_upper[0] @@ -1331,7 +1331,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 61.73 1.38 62.03 ; END END top_width_0_height_0__pin_9_upper[0] PIN top_width_0_height_0__pin_9_lower[0] @@ -1339,7 +1339,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 42.01 68.08 42.31 ; + RECT 64.86 61.73 66.24 62.03 ; END END top_width_0_height_0__pin_9_lower[0] PIN top_width_0_height_0__pin_11_upper[0] @@ -1347,7 +1347,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 48.81 1.38 49.11 ; END END top_width_0_height_0__pin_11_upper[0] PIN top_width_0_height_0__pin_11_lower[0] @@ -1355,7 +1355,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 48.13 68.08 48.43 ; + RECT 64.86 37.25 66.24 37.55 ; END END top_width_0_height_0__pin_11_lower[0] PIN SC_IN_TOP @@ -1363,7 +1363,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 85.68 53.89 87.04 ; + RECT 63.87 85.68 64.01 87.04 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1371,7 +1371,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 14.81 1.38 15.11 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1379,7 +1379,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 85.68 11.11 87.04 ; + RECT 14.19 85.68 14.33 87.04 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1387,7 +1387,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 22.29 68.08 22.59 ; + RECT 64.86 35.89 66.24 36.19 ; END END SC_OUT_BOT PIN VDD @@ -1396,47 +1396,47 @@ MACRO cbx_1__0_ PORT LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 64.88 11.32 68.08 14.52 ; + RECT 63.04 11.32 66.24 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 64.88 52.12 68.08 55.32 ; + RECT 63.04 52.12 66.24 55.32 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 86.44 12.26 87.04 ; - RECT 41.1 86.44 41.7 87.04 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 86.44 11.34 87.04 ; + RECT 40.18 86.44 40.78 87.04 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 67.6 78.64 68.08 79.12 ; + RECT 65.76 78.64 66.24 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 67.6 84.08 68.08 84.56 ; + RECT 65.76 84.08 66.24 84.56 ; END END VDD PIN VSS @@ -1445,170 +1445,147 @@ MACRO cbx_1__0_ PORT LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 64.88 31.72 68.08 34.92 ; + RECT 63.04 31.72 66.24 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 64.88 72.52 68.08 75.72 ; + RECT 63.04 72.52 66.24 75.72 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 86.44 26.98 87.04 ; - RECT 55.82 86.44 56.42 87.04 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 86.44 26.06 87.04 ; + RECT 54.9 86.44 55.5 87.04 ; LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; + RECT 65.76 70.48 66.24 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 67.6 75.92 68.08 76.4 ; + RECT 65.76 75.92 66.24 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 67.6 81.36 68.08 81.84 ; - RECT 0 86.8 68.08 87.04 ; + RECT 65.76 81.36 66.24 81.84 ; + RECT 0 86.8 66.24 87.04 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] DIRECTION OUTPUT ; USE CLOCK ; PORT - LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + LAYER met2 ; + RECT 6.37 85.68 6.51 87.04 ; END END prog_clk__FEEDTHRU_1[0] - PIN prog_clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 2.23 85.68 2.37 87.04 ; - END - END prog_clk__FEEDTHRU_2[0] OBS LAYER li1 ; - RECT 0 86.955 68.08 87.125 ; - RECT 67.62 84.235 68.08 84.405 ; + RECT 0 86.955 66.24 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 67.16 81.515 68.08 81.685 ; + RECT 65.32 81.515 66.24 81.685 ; RECT 0 81.515 1.84 81.685 ; - RECT 67.16 78.795 68.08 78.965 ; + RECT 65.32 78.795 66.24 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 67.16 76.075 68.08 76.245 ; + RECT 65.32 76.075 66.24 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 67.16 70.635 68.08 70.805 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 67.16 67.915 68.08 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; + RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; + RECT 65.32 62.475 66.24 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 65.32 59.755 66.24 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 67.16 43.435 68.08 43.605 ; + RECT 65.32 43.435 66.24 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 67.16 40.715 68.08 40.885 ; + RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 67.16 37.995 68.08 38.165 ; + RECT 62.56 37.995 66.24 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 67.16 35.275 68.08 35.445 ; + RECT 62.56 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 67.16 32.555 68.08 32.725 ; + RECT 65.32 32.555 66.24 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; + RECT 65.32 29.835 66.24 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 67.16 21.675 68.08 21.845 ; + RECT 65.32 27.115 66.24 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 65.32 24.395 66.24 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 65.32 21.675 66.24 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 67.16 18.955 68.08 19.125 ; + RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 67.16 16.235 68.08 16.405 ; + RECT 64.4 16.235 66.24 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 67.16 13.515 68.08 13.685 ; + RECT 64.4 13.515 66.24 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 67.16 10.795 68.08 10.965 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 64.4 5.355 68.08 5.525 ; + RECT 65.78 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 64.4 2.635 68.08 2.805 ; + RECT 65.78 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met3 ; - POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; - POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; - POLYGON 1.99 69.51 1.99 68.83 6.59 68.83 6.59 68.53 1.69 68.53 1.69 68.81 1.78 68.81 1.78 69.51 ; - POLYGON 1.545 56.605 1.545 56.59 1.99 56.59 1.99 55.61 1.78 55.61 1.78 56.31 1.215 56.31 1.215 56.605 ; - POLYGON 6.13 52.51 6.13 52.21 1.23 52.21 1.23 52.49 1.78 52.49 1.78 52.51 ; - POLYGON 1.545 47.085 1.545 47.07 11.19 47.07 11.19 46.77 1.545 46.77 1.545 46.755 1.215 46.755 1.215 47.085 ; - POLYGON 15.33 38.91 15.33 38.61 1.99 38.61 1.99 37.93 1.78 37.93 1.78 38.63 1.69 38.63 1.69 38.91 ; - POLYGON 1.545 37.565 1.545 37.55 20.39 37.55 20.39 37.25 1.545 37.25 1.545 37.235 1.215 37.235 1.215 37.565 ; - POLYGON 15.79 36.19 15.79 35.89 1.78 35.89 1.78 35.91 1.23 35.91 1.23 36.19 ; - POLYGON 13.03 30.75 13.03 30.45 1.78 30.45 1.78 30.47 1.23 30.47 1.23 30.75 ; - POLYGON 7.05 29.39 7.05 29.09 1.78 29.09 1.78 29.11 1.23 29.11 1.23 29.39 ; - POLYGON 7.05 23.95 7.05 23.65 1.99 23.65 1.99 22.97 1.78 22.97 1.78 23.67 1.69 23.67 1.69 23.95 ; - POLYGON 14.87 19.87 14.87 19.57 1.78 19.57 1.78 19.59 1.23 19.59 1.23 19.87 ; - POLYGON 66.85 17.15 66.85 16.87 66.3 16.87 66.3 16.85 47.69 16.85 47.69 17.15 ; - POLYGON 1.545 13.085 1.545 13.07 11.65 13.07 11.65 12.77 1.545 12.77 1.545 12.755 1.215 12.755 1.215 13.085 ; - POLYGON 5.67 11.71 5.67 11.41 1.99 11.41 1.99 10.73 1.78 10.73 1.78 11.43 1.69 11.43 1.69 11.71 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 86.64 67.68 83.51 66.3 83.51 66.3 82.41 67.68 82.41 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 77.39 66.3 77.39 66.3 76.29 67.68 76.29 67.68 76.03 66.3 76.03 66.3 74.93 67.68 74.93 67.68 74.67 66.3 74.67 66.3 73.57 67.68 73.57 67.68 73.31 66.3 73.31 66.3 72.21 67.68 72.21 67.68 71.95 66.3 71.95 66.3 70.85 67.68 70.85 67.68 69.91 66.3 69.91 66.3 68.81 67.68 68.81 67.68 68.55 66.3 68.55 66.3 67.45 67.68 67.45 67.68 67.19 66.3 67.19 66.3 66.09 67.68 66.09 67.68 65.83 66.3 65.83 66.3 64.73 67.68 64.73 67.68 64.47 66.3 64.47 66.3 63.37 67.68 63.37 67.68 63.11 66.3 63.11 66.3 62.01 67.68 62.01 67.68 61.75 66.3 61.75 66.3 60.65 67.68 60.65 67.68 60.39 66.3 60.39 66.3 59.29 67.68 59.29 67.68 59.03 66.3 59.03 66.3 57.93 67.68 57.93 67.68 57.67 66.3 57.67 66.3 56.57 67.68 56.57 67.68 56.31 66.3 56.31 66.3 55.21 67.68 55.21 67.68 54.95 66.3 54.95 66.3 53.85 67.68 53.85 67.68 53.59 66.3 53.59 66.3 52.49 67.68 52.49 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 50.87 66.3 50.87 66.3 49.77 67.68 49.77 67.68 48.83 66.3 48.83 66.3 47.73 67.68 47.73 67.68 46.79 66.3 46.79 66.3 45.69 67.68 45.69 67.68 45.43 66.3 45.43 66.3 44.33 67.68 44.33 67.68 44.07 66.3 44.07 66.3 42.97 67.68 42.97 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.83 66.3 31.83 66.3 30.73 67.68 30.73 67.68 30.47 66.3 30.47 66.3 29.37 67.68 29.37 67.68 29.11 66.3 29.11 66.3 28.01 67.68 28.01 67.68 27.07 66.3 27.07 66.3 25.97 67.68 25.97 67.68 25.71 66.3 25.71 66.3 24.61 67.68 24.61 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 22.99 66.3 22.99 66.3 21.89 67.68 21.89 67.68 20.95 66.3 20.95 66.3 19.85 67.68 19.85 67.68 19.59 66.3 19.59 66.3 18.49 67.68 18.49 67.68 18.23 66.3 18.23 66.3 17.13 67.68 17.13 67.68 16.87 66.3 16.87 66.3 15.77 67.68 15.77 67.68 14.15 66.3 14.15 66.3 13.05 67.68 13.05 67.68 12.11 66.3 12.11 66.3 11.01 67.68 11.01 67.68 10.75 66.3 10.75 66.3 9.65 67.68 9.65 67.68 9.39 66.3 9.39 66.3 8.29 67.68 8.29 67.68 8.03 66.3 8.03 66.3 6.93 67.68 6.93 67.68 6.67 66.3 6.67 66.3 5.57 67.68 5.57 67.68 0.4 0.4 0.4 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 ; + POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; + POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; + POLYGON 14.41 71.55 14.41 71.25 1.23 71.25 1.23 71.53 1.78 71.53 1.78 71.55 ; + POLYGON 1.99 45.03 1.99 44.35 4.29 44.35 4.29 44.05 1.69 44.05 1.69 44.33 1.78 44.33 1.78 45.03 ; + POLYGON 6.59 37.55 6.59 37.25 1.99 37.25 1.99 36.57 1.78 36.57 1.78 37.27 1.69 37.27 1.69 37.55 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 86.64 65.84 84.19 64.46 84.19 64.46 83.09 65.84 83.09 65.84 82.83 64.46 82.83 64.46 81.73 65.84 81.73 65.84 80.79 64.46 80.79 64.46 79.69 65.84 79.69 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 78.07 64.46 78.07 64.46 76.97 65.84 76.97 65.84 76.71 64.46 76.71 64.46 75.61 65.84 75.61 65.84 75.35 64.46 75.35 64.46 74.25 65.84 74.25 65.84 73.99 64.46 73.99 64.46 72.89 65.84 72.89 65.84 72.63 64.46 72.63 64.46 71.53 65.84 71.53 65.84 71.27 64.46 71.27 64.46 70.17 65.84 70.17 65.84 69.91 64.46 69.91 64.46 68.81 65.84 68.81 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 67.19 64.46 67.19 64.46 66.09 65.84 66.09 65.84 65.83 64.46 65.83 64.46 64.73 65.84 64.73 65.84 64.47 64.46 64.47 64.46 63.37 65.84 63.37 65.84 62.43 64.46 62.43 64.46 61.33 65.84 61.33 65.84 60.39 64.46 60.39 64.46 59.29 65.84 59.29 65.84 59.03 64.46 59.03 64.46 57.93 65.84 57.93 65.84 56.99 64.46 56.99 64.46 55.89 65.84 55.89 65.84 54.95 64.46 54.95 64.46 53.85 65.84 53.85 65.84 52.91 64.46 52.91 64.46 51.81 65.84 51.81 65.84 51.55 64.46 51.55 64.46 50.45 65.84 50.45 65.84 50.19 64.46 50.19 64.46 49.09 65.84 49.09 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 46.79 64.46 46.79 64.46 45.69 65.84 45.69 65.84 45.43 64.46 45.43 64.46 44.33 65.84 44.33 65.84 44.07 64.46 44.07 64.46 42.97 65.84 42.97 65.84 42.71 64.46 42.71 64.46 41.61 65.84 41.61 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 39.99 64.46 39.99 64.46 38.89 65.84 38.89 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 31.83 64.46 31.83 64.46 30.73 65.84 30.73 65.84 30.47 64.46 30.47 64.46 29.37 65.84 29.37 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 26.39 64.46 26.39 64.46 25.29 65.84 25.29 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 23.67 64.46 23.67 64.46 22.57 65.84 22.57 65.84 22.31 64.46 22.31 64.46 21.21 65.84 21.21 65.84 20.27 64.46 20.27 64.46 19.17 65.84 19.17 65.84 18.91 64.46 18.91 64.46 17.81 65.84 17.81 65.84 17.55 64.46 17.55 64.46 16.45 65.84 16.45 65.84 16.19 64.46 16.19 64.46 15.09 65.84 15.09 65.84 14.15 64.46 14.15 64.46 13.05 65.84 13.05 65.84 12.11 64.46 12.11 64.46 11.01 65.84 11.01 65.84 10.75 64.46 10.75 64.46 9.65 65.84 9.65 65.84 9.39 64.46 9.39 64.46 8.29 65.84 8.29 65.84 8.03 64.46 8.03 64.46 6.93 65.84 6.93 65.84 6.67 64.46 6.67 64.46 5.57 65.84 5.57 65.84 0.4 0.4 0.4 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 ; LAYER met2 ; - RECT 55.98 86.855 56.26 87.225 ; - RECT 26.54 86.855 26.82 87.225 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 0.28 0.28 0.28 86.76 1.95 86.76 1.95 85.4 2.65 85.4 2.65 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 33.69 86.76 33.69 85.4 34.39 85.4 34.39 86.76 34.61 86.76 34.61 85.4 35.31 85.4 35.31 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 ; + RECT 55.06 86.855 55.34 87.225 ; + RECT 25.62 86.855 25.9 87.225 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 86.76 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 8.17 0.28 8.17 1.64 7.47 1.64 7.47 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 0.28 0.28 0.28 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 11.15 86.76 11.15 85.4 11.85 85.4 11.85 86.76 12.07 86.76 12.07 85.4 12.77 85.4 12.77 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 63.59 86.76 63.59 85.4 64.29 85.4 64.29 86.76 ; LAYER met1 ; - POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER met4 ; - POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; + POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; LAYER met5 ; - POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; + POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER li1 ; - RECT 0.17 0.17 67.91 86.87 ; + RECT 0.17 0.17 66.07 86.87 ; LAYER mcon ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; RECT 65.925 86.955 66.095 87.125 ; RECT 65.465 86.955 65.635 87.125 ; RECT 65.005 86.955 65.175 87.125 ; @@ -1753,134 +1730,130 @@ MACRO cbx_1__0_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 67.765 84.235 67.935 84.405 ; - RECT 67.305 84.235 67.475 84.405 ; + RECT 65.925 84.235 66.095 84.405 ; + RECT 65.465 84.235 65.635 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; + RECT 65.925 81.515 66.095 81.685 ; + RECT 65.465 81.515 65.635 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 67.765 78.795 67.935 78.965 ; - RECT 67.305 78.795 67.475 78.965 ; + RECT 65.925 78.795 66.095 78.965 ; + RECT 65.465 78.795 65.635 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -2026,35 +1999,33 @@ MACRO cbx_1__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 86.965 56.195 87.115 ; - RECT 26.605 86.965 26.755 87.115 ; - RECT 53.745 1.625 53.895 1.775 ; - RECT 19.245 1.625 19.395 1.775 ; - RECT 8.665 1.625 8.815 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 86.965 55.275 87.115 ; + RECT 25.685 86.965 25.835 87.115 ; + RECT 56.045 1.625 56.195 1.775 ; + RECT 43.165 1.625 43.315 1.775 ; + RECT 29.825 1.625 29.975 1.775 ; + RECT 23.845 1.625 23.995 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 66.14 76.74 66.34 76.94 ; - RECT 1.28 75.38 1.48 75.58 ; - RECT 66.14 72.66 66.34 72.86 ; - RECT 1.28 66.54 1.48 66.74 ; - RECT 66.6 55.66 66.8 55.86 ; - RECT 66.6 33.9 66.8 34.1 ; - RECT 66.14 22.34 66.34 22.54 ; - RECT 1.28 21.66 1.48 21.86 ; - RECT 1.28 12.14 1.48 12.34 ; - RECT 1.28 9.42 1.48 9.62 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 64.76 67.9 64.96 68.1 ; + RECT 1.74 66.54 1.94 66.74 ; + RECT 64.76 63.82 64.96 64.02 ; + RECT 1.28 61.78 1.48 61.98 ; + RECT 1.74 23.02 1.94 23.22 ; + RECT 64.76 15.54 64.96 15.74 ; + RECT 1.74 13.5 1.94 13.7 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; + POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; END END cbx_1__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef index 231b996..61270a5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 87.04 ; + SIZE 66.24 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 54.67 0 54.81 1.36 ; + RECT 14.19 0 14.33 1.36 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -475,7 +475,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -483,7 +483,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,7 +491,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -507,7 +507,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 40.65 68.08 40.95 ; + RECT 64.86 71.93 66.24 72.23 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 59.69 68.08 59.99 ; + RECT 64.86 52.89 66.24 53.19 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,7 +547,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 71.93 68.08 72.23 ; + RECT 64.86 48.13 66.24 48.43 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -555,7 +555,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 56.29 68.08 56.59 ; + RECT 64.86 37.25 66.24 37.55 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 33.85 68.08 34.15 ; + RECT 64.86 51.53 66.24 51.83 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,7 +571,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 58.33 68.08 58.63 ; + RECT 64.86 77.37 66.24 77.67 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -579,7 +579,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 44.05 68.08 44.35 ; + RECT 64.86 35.89 66.24 36.19 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 29.77 68.08 30.07 ; + RECT 64.86 39.97 66.24 40.27 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,7 +595,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 32.49 68.08 32.79 ; + RECT 64.86 44.05 66.24 44.35 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -603,7 +603,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 46.77 68.08 47.07 ; + RECT 64.86 41.33 66.24 41.63 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 52.21 68.08 52.51 ; + RECT 64.86 50.17 66.24 50.47 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 54.93 68.08 55.23 ; + RECT 64.86 57.65 66.24 57.95 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 53.57 68.08 53.87 ; + RECT 64.86 31.81 66.24 32.11 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 62.41 68.08 62.71 ; + RECT 64.86 80.09 66.24 80.39 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 23.65 68.08 23.95 ; + RECT 64.86 22.29 66.24 22.59 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 66.49 68.08 66.79 ; + RECT 64.86 67.85 66.24 68.15 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 69.21 68.08 69.51 ; + RECT 64.86 59.01 66.24 59.31 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 28.41 68.08 28.71 ; + RECT 64.86 29.09 66.24 29.39 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 48.13 68.08 48.43 ; + RECT 64.86 42.69 66.24 42.99 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 67.85 68.08 68.15 ; + RECT 64.86 69.21 66.24 69.51 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 78.73 68.08 79.03 ; + RECT 64.86 65.81 66.24 66.11 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -723,7 +723,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -731,7 +731,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,7 +763,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -771,7 +771,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -779,7 +779,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.17 1.38 67.47 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,7 +803,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -819,7 +819,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -851,7 +851,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -859,7 +859,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 42.01 68.08 42.31 ; + RECT 64.86 55.61 66.24 55.91 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 61.05 68.08 61.35 ; + RECT 64.86 73.29 66.24 73.59 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 74.65 68.08 74.95 ; + RECT 64.86 74.65 66.24 74.95 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 25.69 68.08 25.99 ; + RECT 64.86 26.37 66.24 26.67 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 31.13 68.08 31.43 ; + RECT 64.86 33.17 66.24 33.47 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 36.57 68.08 36.87 ; + RECT 64.86 20.93 66.24 21.23 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,7 +907,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 80.09 68.08 80.39 ; + RECT 64.86 78.73 66.24 79.03 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -915,7 +915,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 49.49 68.08 49.79 ; + RECT 64.86 54.25 66.24 54.55 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 45.41 68.08 45.71 ; + RECT 64.86 46.09 66.24 46.39 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 73.29 68.08 73.59 ; + RECT 64.86 70.57 66.24 70.87 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,7 +939,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 77.37 68.08 77.67 ; + RECT 64.86 38.61 66.24 38.91 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -947,7 +947,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 76.01 68.08 76.31 ; + RECT 64.86 64.45 66.24 64.75 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,7 +955,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 35.21 68.08 35.51 ; + RECT 64.86 81.45 66.24 81.75 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -963,7 +963,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 37.93 68.08 38.23 ; + RECT 64.86 34.53 66.24 34.83 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -971,7 +971,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 50.85 68.08 51.15 ; + RECT 64.86 76.01 66.24 76.31 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 65.13 68.08 65.43 ; + RECT 64.86 60.37 66.24 60.67 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 70.57 68.08 70.87 ; + RECT 64.86 30.45 66.24 30.75 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 39.29 68.08 39.59 ; + RECT 64.86 27.73 66.24 28.03 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 63.77 68.08 64.07 ; + RECT 64.86 63.09 66.24 63.39 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,7 +1011,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 27.05 68.08 27.35 ; + RECT 64.86 61.73 66.24 62.03 ; END END chanx_right_out[19] PIN bottom_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_1_[0] @@ -1027,7 +1027,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END bottom_grid_pin_1_[0] PIN bottom_grid_pin_2_[0] @@ -1035,7 +1035,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_3_[0] @@ -1043,7 +1043,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END bottom_grid_pin_3_[0] PIN bottom_grid_pin_4_[0] @@ -1051,7 +1051,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_5_[0] @@ -1059,7 +1059,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END bottom_grid_pin_5_[0] PIN bottom_grid_pin_6_[0] @@ -1067,7 +1067,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END bottom_grid_pin_6_[0] PIN bottom_grid_pin_7_[0] @@ -1075,7 +1075,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END bottom_grid_pin_7_[0] PIN bottom_grid_pin_8_[0] @@ -1083,7 +1083,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; + RECT 2.23 0 2.37 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_9_[0] @@ -1091,7 +1091,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END bottom_grid_pin_9_[0] PIN bottom_grid_pin_10_[0] @@ -1099,7 +1099,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END bottom_grid_pin_10_[0] PIN bottom_grid_pin_11_[0] @@ -1107,7 +1107,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END bottom_grid_pin_11_[0] PIN bottom_grid_pin_12_[0] @@ -1115,7 +1115,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END bottom_grid_pin_12_[0] PIN bottom_grid_pin_13_[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END bottom_grid_pin_13_[0] PIN bottom_grid_pin_14_[0] @@ -1131,7 +1131,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 0 5.59 1.36 ; + RECT 16.03 0 16.17 1.36 ; END END bottom_grid_pin_14_[0] PIN bottom_grid_pin_15_[0] @@ -1139,7 +1139,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END bottom_grid_pin_15_[0] PIN ccff_tail[0] @@ -1147,7 +1147,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 32.49 1.38 32.79 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1155,7 +1155,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 85.68 53.89 87.04 ; + RECT 63.87 85.68 64.01 87.04 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1163,7 +1163,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1171,7 +1171,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 85.68 11.11 87.04 ; + RECT 14.19 85.68 14.33 87.04 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1179,7 +1179,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 16.95 0 17.09 1.36 ; END END SC_OUT_BOT PIN VDD @@ -1187,48 +1187,48 @@ MACRO cbx_1__1_ USE POWER ; PORT LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 86.44 12.26 87.04 ; - RECT 41.1 86.44 41.7 87.04 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 86.44 11.34 87.04 ; + RECT 40.18 86.44 40.78 87.04 ; LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 64.88 11.32 68.08 14.52 ; + RECT 63.04 11.32 66.24 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 64.88 52.12 68.08 55.32 ; + RECT 63.04 52.12 66.24 55.32 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 67.6 78.64 68.08 79.12 ; + RECT 65.76 78.64 66.24 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 67.6 84.08 68.08 84.56 ; + RECT 65.76 84.08 66.24 84.56 ; END END VDD PIN VSS @@ -1236,48 +1236,48 @@ MACRO cbx_1__1_ USE GROUND ; PORT LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 86.44 26.98 87.04 ; - RECT 55.82 86.44 56.42 87.04 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 86.44 26.06 87.04 ; + RECT 54.9 86.44 55.5 87.04 ; LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 64.88 31.72 68.08 34.92 ; + RECT 63.04 31.72 66.24 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 64.88 72.52 68.08 75.72 ; + RECT 63.04 72.52 66.24 75.72 ; LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; + RECT 65.76 70.48 66.24 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 67.6 75.92 68.08 76.4 ; + RECT 65.76 75.92 66.24 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 67.6 81.36 68.08 81.84 ; - RECT 0 86.8 68.08 87.04 ; + RECT 65.76 81.36 66.24 81.84 ; + RECT 0 86.8 66.24 87.04 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] @@ -1285,110 +1285,107 @@ MACRO cbx_1__1_ USE CLOCK ; PORT LAYER met3 ; - RECT 66.7 6.65 68.08 6.95 ; + RECT 64.86 24.33 66.24 24.63 ; END END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 86.955 68.08 87.125 ; - RECT 67.16 84.235 68.08 84.405 ; + RECT 0 86.955 66.24 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 67.16 81.515 68.08 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 67.16 78.795 68.08 78.965 ; + RECT 65.32 81.515 66.24 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 65.32 78.795 66.24 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 67.16 76.075 68.08 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 67.16 70.635 68.08 70.805 ; + RECT 65.32 76.075 66.24 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 67.16 67.915 68.08 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; + RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; + RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; + RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 62.56 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 67.16 43.435 68.08 43.605 ; + RECT 62.56 43.435 66.24 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 67.16 40.715 68.08 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 67.16 37.995 68.08 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 67.16 35.275 68.08 35.445 ; + RECT 65.32 40.715 66.24 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 65.32 37.995 66.24 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 67.16 32.555 68.08 32.725 ; + RECT 65.32 32.555 66.24 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; + RECT 65.32 29.835 66.24 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; + RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; + RECT 65.32 24.395 66.24 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 67.16 21.675 68.08 21.845 ; + RECT 65.32 21.675 66.24 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 67.16 18.955 68.08 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 67.16 16.235 68.08 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 67.16 13.515 68.08 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 67.16 10.795 68.08 10.965 ; + RECT 65.32 18.955 66.24 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 65.32 16.235 66.24 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 65.32 13.515 66.24 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.32 8.075 66.24 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 65.32 5.355 66.24 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 65.78 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; - RECT 55.98 86.855 56.26 87.225 ; - RECT 26.54 86.855 26.82 87.225 ; - RECT 9.53 1.54 9.79 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 55.09 0.28 55.09 1.64 54.39 1.64 54.39 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 0.28 0.28 0.28 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 ; + RECT 55.06 86.855 55.34 87.225 ; + RECT 25.62 86.855 25.9 87.225 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 86.76 65.96 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 63.59 86.76 63.59 85.4 64.29 85.4 64.29 86.76 ; LAYER met3 ; - POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; - POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; - POLYGON 2.03 77 2.03 76.99 53.51 76.99 53.51 76.69 2.03 76.69 2.03 76.68 1.65 76.68 1.65 77 ; - POLYGON 6.13 75.63 6.13 75.33 1.53 75.33 1.53 74.67 1.23 74.67 1.23 75.63 ; - POLYGON 66.3 72.91 66.3 72.89 67.77 72.89 67.77 72.61 65.63 72.61 65.63 72.91 ; - POLYGON 2.03 64.08 2.03 64.07 8.43 64.07 8.43 63.77 2.03 63.77 2.03 63.76 1.65 63.76 1.65 64.08 ; - POLYGON 1.99 63.39 1.99 62.71 5.67 62.71 5.67 62.41 1.69 62.41 1.69 62.69 1.78 62.69 1.78 63.39 ; - POLYGON 6.59 61.35 6.59 61.05 1.23 61.05 1.23 61.33 1.78 61.33 1.78 61.35 ; - POLYGON 2.005 57.965 2.005 57.96 2.03 57.96 2.03 57.64 2.005 57.64 2.005 57.635 1.275 57.635 1.275 57.965 ; - POLYGON 1.99 45.03 1.99 44.365 2.005 44.365 2.005 44.035 1.675 44.035 1.675 44.33 1.78 44.33 1.78 45.03 ; - POLYGON 66.43 34.84 66.43 34.52 66.05 34.52 66.05 34.53 43.09 34.53 43.09 34.83 66.05 34.83 66.05 34.84 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 86.64 67.68 80.79 66.3 80.79 66.3 79.69 67.68 79.69 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 78.07 66.3 78.07 66.3 76.97 67.68 76.97 67.68 76.71 66.3 76.71 66.3 75.61 67.68 75.61 67.68 75.35 66.3 75.35 66.3 74.25 67.68 74.25 67.68 73.99 66.3 73.99 66.3 72.89 67.68 72.89 67.68 72.63 66.3 72.63 66.3 71.53 67.68 71.53 67.68 71.27 66.3 71.27 66.3 70.17 67.68 70.17 67.68 69.91 66.3 69.91 66.3 68.81 67.68 68.81 67.68 68.55 66.3 68.55 66.3 67.45 67.68 67.45 67.68 67.19 66.3 67.19 66.3 66.09 67.68 66.09 67.68 65.83 66.3 65.83 66.3 64.73 67.68 64.73 67.68 64.47 66.3 64.47 66.3 63.37 67.68 63.37 67.68 63.11 66.3 63.11 66.3 62.01 67.68 62.01 67.68 61.75 66.3 61.75 66.3 60.65 67.68 60.65 67.68 60.39 66.3 60.39 66.3 59.29 67.68 59.29 67.68 59.03 66.3 59.03 66.3 57.93 67.68 57.93 67.68 56.99 66.3 56.99 66.3 55.89 67.68 55.89 67.68 55.63 66.3 55.63 66.3 54.53 67.68 54.53 67.68 54.27 66.3 54.27 66.3 53.17 67.68 53.17 67.68 52.91 66.3 52.91 66.3 51.81 67.68 51.81 67.68 51.55 66.3 51.55 66.3 50.45 67.68 50.45 67.68 50.19 66.3 50.19 66.3 49.09 67.68 49.09 67.68 48.83 66.3 48.83 66.3 47.73 67.68 47.73 67.68 47.47 66.3 47.47 66.3 46.37 67.68 46.37 67.68 46.11 66.3 46.11 66.3 45.01 67.68 45.01 67.68 44.75 66.3 44.75 66.3 43.65 67.68 43.65 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.83 66.3 31.83 66.3 30.73 67.68 30.73 67.68 30.47 66.3 30.47 66.3 29.37 67.68 29.37 67.68 29.11 66.3 29.11 66.3 28.01 67.68 28.01 67.68 27.75 66.3 27.75 66.3 26.65 67.68 26.65 67.68 26.39 66.3 26.39 66.3 25.29 67.68 25.29 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 7.35 66.3 7.35 66.3 6.25 67.68 6.25 67.68 0.4 0.4 0.4 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 86.64 ; + POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; + POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; + POLYGON 2.03 78.36 2.03 78.35 4.29 78.35 4.29 78.05 2.03 78.05 2.03 78.04 1.65 78.04 1.65 78.36 ; + POLYGON 7.51 71.55 7.51 71.25 1.78 71.25 1.78 71.27 1.23 71.27 1.23 71.55 ; + POLYGON 24.07 68.83 24.07 68.53 1.78 68.53 1.78 68.55 1.23 68.55 1.23 68.83 ; + POLYGON 65.01 64.07 65.01 63.79 64.46 63.79 64.46 63.77 61.95 63.77 61.95 64.07 ; + POLYGON 11.65 55.23 11.65 54.93 1.78 54.93 1.78 54.95 1.08 54.95 1.08 55.23 ; + POLYGON 3.37 48.43 3.37 48.13 1.99 48.13 1.99 47.45 1.78 47.45 1.78 48.15 1.69 48.15 1.69 48.43 ; + POLYGON 2.03 40.28 2.03 40.27 11.65 40.27 11.65 39.97 2.03 39.97 2.03 39.96 1.65 39.96 1.65 40.28 ; + POLYGON 1.99 39.59 1.99 38.91 18.09 38.91 18.09 38.61 1.69 38.61 1.69 38.89 1.78 38.89 1.78 39.59 ; + POLYGON 1.545 36.205 1.545 36.19 50.75 36.19 50.75 35.89 1.545 35.89 1.545 35.875 1.215 35.875 1.215 36.205 ; + POLYGON 23.15 30.75 23.15 30.45 1.23 30.45 1.23 30.73 1.78 30.73 1.78 30.75 ; + POLYGON 10.73 23.95 10.73 23.65 1.99 23.65 1.99 23.27 2.91 23.27 2.91 22.97 1.78 22.97 1.78 23.67 1.69 23.67 1.69 23.95 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 86.64 65.84 82.15 64.46 82.15 64.46 81.05 65.84 81.05 65.84 80.79 64.46 80.79 64.46 79.69 65.84 79.69 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 78.07 64.46 78.07 64.46 76.97 65.84 76.97 65.84 76.71 64.46 76.71 64.46 75.61 65.84 75.61 65.84 75.35 64.46 75.35 64.46 74.25 65.84 74.25 65.84 73.99 64.46 73.99 64.46 72.89 65.84 72.89 65.84 72.63 64.46 72.63 64.46 71.53 65.84 71.53 65.84 71.27 64.46 71.27 64.46 70.17 65.84 70.17 65.84 69.91 64.46 69.91 64.46 68.81 65.84 68.81 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 66.51 64.46 66.51 64.46 65.41 65.84 65.41 65.84 65.15 64.46 65.15 64.46 64.05 65.84 64.05 65.84 63.79 64.46 63.79 64.46 62.69 65.84 62.69 65.84 62.43 64.46 62.43 64.46 61.33 65.84 61.33 65.84 61.07 64.46 61.07 64.46 59.97 65.84 59.97 65.84 59.71 64.46 59.71 64.46 58.61 65.84 58.61 65.84 58.35 64.46 58.35 64.46 57.25 65.84 57.25 65.84 56.31 64.46 56.31 64.46 55.21 65.84 55.21 65.84 54.95 64.46 54.95 64.46 53.85 65.84 53.85 65.84 53.59 64.46 53.59 64.46 52.49 65.84 52.49 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 50.87 64.46 50.87 64.46 49.77 65.84 49.77 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 46.79 64.46 46.79 64.46 45.69 65.84 45.69 65.84 44.75 64.46 44.75 64.46 43.65 65.84 43.65 65.84 43.39 64.46 43.39 64.46 42.29 65.84 42.29 65.84 42.03 64.46 42.03 64.46 40.93 65.84 40.93 65.84 40.67 64.46 40.67 64.46 39.57 65.84 39.57 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 32.51 64.46 32.51 64.46 31.41 65.84 31.41 65.84 31.15 64.46 31.15 64.46 30.05 65.84 30.05 65.84 29.79 64.46 29.79 64.46 28.69 65.84 28.69 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 27.07 64.46 27.07 64.46 25.97 65.84 25.97 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 22.99 64.46 22.99 64.46 21.89 65.84 21.89 65.84 21.63 64.46 21.63 64.46 20.53 65.84 20.53 65.84 0.4 0.4 0.4 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 86.64 ; LAYER met1 ; - POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER met5 ; - POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; + POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met4 ; - POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; + POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; LAYER li1 ; - RECT 0.17 0.17 67.91 86.87 ; + RECT 0.17 0.17 66.07 86.87 ; LAYER mcon ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; RECT 65.925 86.955 66.095 87.125 ; RECT 65.465 86.955 65.635 87.125 ; RECT 65.005 86.955 65.175 87.125 ; @@ -1533,134 +1530,130 @@ MACRO cbx_1__1_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 67.765 84.235 67.935 84.405 ; - RECT 67.305 84.235 67.475 84.405 ; + RECT 65.925 84.235 66.095 84.405 ; + RECT 65.465 84.235 65.635 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; + RECT 65.925 81.515 66.095 81.685 ; + RECT 65.465 81.515 65.635 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 67.765 78.795 67.935 78.965 ; - RECT 67.305 78.795 67.475 78.965 ; + RECT 65.925 78.795 66.095 78.965 ; + RECT 65.465 78.795 65.635 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1806,39 +1799,40 @@ MACRO cbx_1__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 86.965 56.195 87.115 ; - RECT 26.605 86.965 26.755 87.115 ; - RECT 33.045 1.625 33.195 1.775 ; - RECT 11.885 1.625 12.035 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 86.965 55.275 87.115 ; + RECT 25.685 86.965 25.835 87.115 ; + RECT 36.725 1.625 36.875 1.775 ; + RECT 16.945 1.625 17.095 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 1.28 76.06 1.48 76.26 ; - RECT 1.74 69.94 1.94 70.14 ; - RECT 66.6 69.26 66.8 69.46 ; - RECT 1.28 67.22 1.48 67.42 ; - RECT 66.6 65.18 66.8 65.38 ; - RECT 1.74 53.62 1.94 53.82 ; - RECT 66.14 52.26 66.34 52.46 ; - RECT 1.74 33.22 1.94 33.42 ; - RECT 1.74 29.14 1.94 29.34 ; - RECT 1.28 26.42 1.48 26.62 ; - RECT 66.6 25.74 66.8 25.94 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 1.28 80.14 1.48 80.34 ; + RECT 64.76 73.34 64.96 73.54 ; + RECT 1.74 63.82 1.94 64.02 ; + RECT 64.76 60.42 64.96 60.62 ; + RECT 1.74 52.94 1.94 53.14 ; + RECT 64.76 46.14 64.96 46.34 ; + RECT 1.28 46.14 1.48 46.34 ; + RECT 64.76 40.02 64.96 40.22 ; + RECT 64.3 38.66 64.5 38.86 ; + RECT 64.3 34.58 64.5 34.78 ; + RECT 64.76 33.22 64.96 33.42 ; + RECT 1.28 32.54 1.48 32.74 ; + RECT 1.28 25.74 1.48 25.94 ; + RECT 64.76 20.98 64.96 21.18 ; + RECT 1.74 20.98 1.94 21.18 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 1.74 71.3 1.94 71.5 ; - RECT 1.74 68.58 1.94 68.78 ; - RECT 1.74 31.86 1.94 32.06 ; - RECT 66.14 28.46 66.34 28.66 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 1.74 57.02 1.94 57.22 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; + POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; END END cbx_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef index cf227be..6a93c37 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 87.04 ; + SIZE 66.24 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 54.67 0 54.81 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + RECT 0 3.25 1.38 3.55 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; + RECT 0 4.61 1.38 4.91 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -475,7 +475,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; + RECT 0 16.85 1.38 17.15 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -483,7 +483,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,7 +491,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -499,7 +499,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -507,7 +507,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 60.37 68.08 60.67 ; + RECT 64.86 61.05 66.24 61.35 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 78.73 68.08 79.03 ; + RECT 64.86 78.73 66.24 79.03 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,7 +547,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 57.65 68.08 57.95 ; + RECT 64.86 62.41 66.24 62.71 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -555,7 +555,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 40.65 68.08 40.95 ; + RECT 64.86 41.33 66.24 41.63 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 64.45 68.08 64.75 ; + RECT 64.86 59.69 66.24 59.99 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,7 +571,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 35.21 68.08 35.51 ; + RECT 64.86 56.97 66.24 57.27 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -579,7 +579,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 43.37 68.08 43.67 ; + RECT 64.86 35.89 66.24 36.19 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 39.29 68.08 39.59 ; + RECT 64.86 37.25 66.24 37.55 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,7 +595,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 63.09 68.08 63.39 ; + RECT 64.86 66.49 66.24 66.79 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -603,7 +603,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 26.37 68.08 26.67 ; + RECT 64.86 33.17 66.24 33.47 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 61.73 68.08 62.03 ; + RECT 64.86 42.69 66.24 42.99 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 19.57 68.08 19.87 ; + RECT 64.86 26.37 66.24 26.67 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 59.01 68.08 59.31 ; + RECT 64.86 63.77 66.24 64.07 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 37.93 68.08 38.23 ; + RECT 64.86 16.85 66.24 17.15 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 42.01 68.08 42.31 ; + RECT 64.86 52.21 66.24 52.51 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 51.53 68.08 51.83 ; + RECT 64.86 29.09 66.24 29.39 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 32.49 68.08 32.79 ; + RECT 64.86 13.45 66.24 13.75 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 15.49 68.08 15.79 ; + RECT 64.86 20.93 66.24 21.23 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 48.81 68.08 49.11 ; + RECT 64.86 34.53 66.24 34.83 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 16.85 68.08 17.15 ; + RECT 64.86 54.93 66.24 55.23 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 20.93 68.08 21.23 ; + RECT 64.86 3.93 66.24 4.23 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -715,7 +715,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -723,7 +723,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -731,7 +731,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 13.45 1.38 13.75 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,7 +763,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -771,7 +771,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -779,7 +779,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,7 +803,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -811,7 +811,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -819,7 +819,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -851,7 +851,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -859,7 +859,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 33.85 68.08 34.15 ; + RECT 64.86 31.81 66.24 32.11 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 50.17 68.08 50.47 ; + RECT 64.86 44.05 66.24 44.35 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 29.09 68.08 29.39 ; + RECT 64.86 38.61 66.24 38.91 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 12.77 68.08 13.07 ; + RECT 64.86 10.73 66.24 11.03 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 18.21 68.08 18.51 ; + RECT 64.86 12.09 66.24 12.39 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 14.13 68.08 14.43 ; + RECT 64.86 22.29 66.24 22.59 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,7 +907,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 30.45 68.08 30.75 ; + RECT 64.86 15.49 66.24 15.79 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -915,7 +915,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 25.01 68.08 25.31 ; + RECT 64.86 18.21 66.24 18.51 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 22.29 68.08 22.59 ; + RECT 64.86 30.45 66.24 30.75 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 54.25 68.08 54.55 ; + RECT 64.86 45.41 66.24 45.71 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,7 +939,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 36.57 68.08 36.87 ; + RECT 64.86 46.77 66.24 47.07 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -947,7 +947,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 9.37 68.08 9.67 ; + RECT 64.86 48.13 66.24 48.43 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,7 +955,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 6.65 68.08 6.95 ; + RECT 64.86 8.01 66.24 8.31 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -963,7 +963,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 11.41 68.08 11.71 ; + RECT 64.86 9.37 66.24 9.67 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -971,7 +971,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 8.01 68.08 8.31 ; + RECT 64.86 6.65 66.24 6.95 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 23.65 68.08 23.95 ; + RECT 64.86 19.57 66.24 19.87 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 47.45 68.08 47.75 ; + RECT 64.86 53.57 66.24 53.87 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 52.89 68.08 53.19 ; + RECT 64.86 39.97 66.24 40.27 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 46.09 68.08 46.39 ; + RECT 64.86 58.33 66.24 58.63 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,15 +1011,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 27.73 68.08 28.03 ; + RECT 64.86 27.73 66.24 28.03 ; END END chanx_right_out[19] PIN top_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 46.85 85.68 46.99 87.04 ; + LAYER met3 ; + RECT 64.86 67.85 66.24 68.15 ; END END top_grid_pin_0_[0] PIN bottom_grid_pin_0_[0] @@ -1027,7 +1027,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_1_[0] @@ -1035,7 +1035,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END bottom_grid_pin_1_[0] PIN bottom_grid_pin_2_[0] @@ -1043,7 +1043,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_3_[0] @@ -1051,7 +1051,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END bottom_grid_pin_3_[0] PIN bottom_grid_pin_4_[0] @@ -1059,7 +1059,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_5_[0] @@ -1067,7 +1067,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END bottom_grid_pin_5_[0] PIN bottom_grid_pin_6_[0] @@ -1075,7 +1075,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END bottom_grid_pin_6_[0] PIN bottom_grid_pin_7_[0] @@ -1083,7 +1083,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END bottom_grid_pin_7_[0] PIN bottom_grid_pin_8_[0] @@ -1091,7 +1091,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; + RECT 2.23 0 2.37 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_9_[0] @@ -1099,7 +1099,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END bottom_grid_pin_9_[0] PIN bottom_grid_pin_10_[0] @@ -1107,7 +1107,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END bottom_grid_pin_10_[0] PIN bottom_grid_pin_11_[0] @@ -1115,7 +1115,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END bottom_grid_pin_11_[0] PIN bottom_grid_pin_12_[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END bottom_grid_pin_12_[0] PIN bottom_grid_pin_13_[0] @@ -1131,7 +1131,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END bottom_grid_pin_13_[0] PIN bottom_grid_pin_14_[0] @@ -1139,7 +1139,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 0 5.59 1.36 ; + RECT 16.03 0 16.17 1.36 ; END END bottom_grid_pin_14_[0] PIN bottom_grid_pin_15_[0] @@ -1147,7 +1147,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END bottom_grid_pin_15_[0] PIN ccff_tail[0] @@ -1155,7 +1155,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 37.25 1.38 37.55 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1163,7 +1163,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 85.68 53.89 87.04 ; + RECT 62.49 85.68 62.63 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1171,7 +1171,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 85.68 59.41 87.04 ; + RECT 50.99 85.68 51.13 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1179,15 +1179,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 85.68 6.97 87.04 ; + RECT 7.29 85.68 7.43 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN bottom_width_0_height_0__pin_0_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 45.93 85.68 46.07 87.04 ; + LAYER met3 ; + RECT 64.86 65.13 66.24 65.43 ; END END bottom_width_0_height_0__pin_0_[0] PIN bottom_width_0_height_0__pin_1_upper[0] @@ -1195,7 +1195,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 27.05 1.38 27.35 ; END END bottom_width_0_height_0__pin_1_upper[0] PIN bottom_width_0_height_0__pin_1_lower[0] @@ -1203,7 +1203,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 44.73 68.08 45.03 ; + RECT 64.86 50.17 66.24 50.47 ; END END bottom_width_0_height_0__pin_1_lower[0] PIN SC_IN_TOP @@ -1219,7 +1219,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1227,7 +1227,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 51.53 1.38 51.83 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1235,7 +1235,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 3.25 68.08 3.55 ; + RECT 64.86 5.29 66.24 5.59 ; END END SC_OUT_BOT PIN VDD @@ -1243,48 +1243,48 @@ MACRO cbx_1__2_ USE POWER ; PORT LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 86.44 12.26 87.04 ; - RECT 41.1 86.44 41.7 87.04 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 86.44 11.34 87.04 ; + RECT 40.18 86.44 40.78 87.04 ; LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 64.88 11.32 68.08 14.52 ; + RECT 63.04 11.32 66.24 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 64.88 52.12 68.08 55.32 ; + RECT 63.04 52.12 66.24 55.32 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 67.6 78.64 68.08 79.12 ; + RECT 65.76 78.64 66.24 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 67.6 84.08 68.08 84.56 ; + RECT 65.76 84.08 66.24 84.56 ; END END VDD PIN VSS @@ -1292,147 +1292,156 @@ MACRO cbx_1__2_ USE GROUND ; PORT LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 86.44 26.98 87.04 ; - RECT 55.82 86.44 56.42 87.04 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 86.44 26.06 87.04 ; + RECT 54.9 86.44 55.5 87.04 ; LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 64.88 31.72 68.08 34.92 ; + RECT 63.04 31.72 66.24 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 64.88 72.52 68.08 75.72 ; + RECT 63.04 72.52 66.24 75.72 ; LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; + RECT 65.76 70.48 66.24 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 67.6 75.92 68.08 76.4 ; + RECT 65.76 75.92 66.24 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 67.6 81.36 68.08 81.84 ; - RECT 0 86.8 68.08 87.04 ; + RECT 65.76 81.36 66.24 81.84 ; + RECT 0 86.8 66.24 87.04 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END prog_clk__FEEDTHRU_1[0] + PIN prog_clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 64.86 24.33 66.24 24.63 ; + END + END prog_clk__FEEDTHRU_2[0] OBS LAYER li1 ; - RECT 0 86.955 68.08 87.125 ; - RECT 67.16 84.235 68.08 84.405 ; + RECT 0 86.955 66.24 87.125 ; + RECT 65.32 84.235 66.24 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 67.16 81.515 68.08 81.685 ; + RECT 65.32 81.515 66.24 81.685 ; RECT 0 81.515 1.84 81.685 ; - RECT 67.62 78.795 68.08 78.965 ; + RECT 65.32 78.795 66.24 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 67.16 76.075 68.08 76.245 ; + RECT 65.32 76.075 66.24 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 64.4 70.635 68.08 70.805 ; + RECT 64.4 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 64.4 67.915 68.08 68.085 ; + RECT 64.4 67.915 66.24 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; + RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; + RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; + RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 67.16 43.435 68.08 43.605 ; + RECT 65.32 43.435 66.24 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 66.24 40.715 68.08 40.885 ; + RECT 65.32 40.715 66.24 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 66.24 37.995 68.08 38.165 ; + RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 67.16 35.275 68.08 35.445 ; + RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 67.16 32.555 68.08 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; + RECT 65.32 32.555 66.24 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 65.32 29.835 66.24 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; + RECT 65.32 24.395 66.24 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 67.16 21.675 68.08 21.845 ; + RECT 65.32 21.675 66.24 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 67.16 18.955 68.08 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 67.16 16.235 68.08 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 67.16 13.515 68.08 13.685 ; + RECT 65.32 18.955 66.24 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 65.32 16.235 66.24 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 67.16 10.795 68.08 10.965 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; - RECT 55.98 86.855 56.26 87.225 ; - RECT 26.54 86.855 26.82 87.225 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 55.09 0.28 55.09 1.64 54.39 1.64 54.39 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 45.65 86.76 45.65 85.4 46.35 85.4 46.35 86.76 46.57 86.76 46.57 85.4 47.27 85.4 47.27 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 58.99 86.76 58.99 85.4 59.69 85.4 59.69 86.76 ; + RECT 55.06 86.855 55.34 87.225 ; + RECT 25.62 86.855 25.9 87.225 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 86.76 65.96 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 50.71 86.76 50.71 85.4 51.41 85.4 51.41 86.76 62.21 86.76 62.21 85.4 62.91 85.4 62.91 86.76 ; LAYER met3 ; - POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; - POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; - POLYGON 66.43 53.88 66.43 53.56 66.05 53.56 66.05 53.57 51.37 53.57 51.37 53.87 66.05 53.87 66.05 53.88 ; - POLYGON 20.39 41.63 20.39 41.33 1.99 41.33 1.99 40.65 1.78 40.65 1.78 41.35 1.69 41.35 1.69 41.63 ; - POLYGON 66.43 33.48 66.43 33.16 66.05 33.16 66.05 33.17 53.21 33.17 53.21 33.47 66.05 33.47 66.05 33.48 ; - POLYGON 66.865 17.845 66.865 17.515 66.535 17.515 66.535 17.53 60.57 17.53 60.57 17.83 66.535 17.83 66.535 17.845 ; - POLYGON 2.005 11.725 2.005 11.71 28.21 11.71 28.21 11.41 2.005 11.41 2.005 11.395 1.99 11.395 1.99 10.73 1.78 10.73 1.78 11.43 1.675 11.43 1.675 11.725 ; - POLYGON 2.03 6.28 2.03 6.27 60.87 6.27 60.87 5.97 2.03 5.97 2.03 5.96 1.65 5.96 1.65 6.28 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 86.64 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 65.15 66.3 65.15 66.3 64.05 67.68 64.05 67.68 63.79 66.3 63.79 66.3 62.69 67.68 62.69 67.68 62.43 66.3 62.43 66.3 61.33 67.68 61.33 67.68 61.07 66.3 61.07 66.3 59.97 67.68 59.97 67.68 59.71 66.3 59.71 66.3 58.61 67.68 58.61 67.68 58.35 66.3 58.35 66.3 57.25 67.68 57.25 67.68 54.95 66.3 54.95 66.3 53.85 67.68 53.85 67.68 53.59 66.3 53.59 66.3 52.49 67.68 52.49 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 50.87 66.3 50.87 66.3 49.77 67.68 49.77 67.68 49.51 66.3 49.51 66.3 48.41 67.68 48.41 67.68 48.15 66.3 48.15 66.3 47.05 67.68 47.05 67.68 46.79 66.3 46.79 66.3 45.69 67.68 45.69 67.68 45.43 66.3 45.43 66.3 44.33 67.68 44.33 67.68 44.07 66.3 44.07 66.3 42.97 67.68 42.97 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.15 66.3 31.15 66.3 30.05 67.68 30.05 67.68 29.79 66.3 29.79 66.3 28.69 67.68 28.69 67.68 28.43 66.3 28.43 66.3 27.33 67.68 27.33 67.68 27.07 66.3 27.07 66.3 25.97 67.68 25.97 67.68 25.71 66.3 25.71 66.3 24.61 67.68 24.61 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 22.99 66.3 22.99 66.3 21.89 67.68 21.89 67.68 21.63 66.3 21.63 66.3 20.53 67.68 20.53 67.68 20.27 66.3 20.27 66.3 19.17 67.68 19.17 67.68 18.91 66.3 18.91 66.3 17.81 67.68 17.81 67.68 17.55 66.3 17.55 66.3 16.45 67.68 16.45 67.68 16.19 66.3 16.19 66.3 15.09 67.68 15.09 67.68 14.83 66.3 14.83 66.3 13.73 67.68 13.73 67.68 13.47 66.3 13.47 66.3 12.37 67.68 12.37 67.68 12.11 66.3 12.11 66.3 11.01 67.68 11.01 67.68 10.07 66.3 10.07 66.3 8.97 67.68 8.97 67.68 8.71 66.3 8.71 66.3 7.61 67.68 7.61 67.68 7.35 66.3 7.35 66.3 6.25 67.68 6.25 67.68 3.95 66.3 3.95 66.3 2.85 67.68 2.85 67.68 0.4 0.4 0.4 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 86.64 ; + POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; + POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; + POLYGON 2.005 35.525 2.005 35.52 2.03 35.52 2.03 35.2 2.005 35.2 2.005 35.195 1.275 35.195 1.275 35.525 ; + POLYGON 1.545 30.085 1.545 30.07 7.05 30.07 7.05 29.77 1.545 29.77 1.545 29.755 1.215 29.755 1.215 30.085 ; + POLYGON 2.03 19.88 2.03 19.87 30.51 19.87 30.51 19.57 2.03 19.57 2.03 19.56 1.65 19.56 1.65 19.88 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 86.64 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 67.19 64.46 67.19 64.46 66.09 65.84 66.09 65.84 65.83 64.46 65.83 64.46 64.73 65.84 64.73 65.84 64.47 64.46 64.47 64.46 63.37 65.84 63.37 65.84 63.11 64.46 63.11 64.46 62.01 65.84 62.01 65.84 61.75 64.46 61.75 64.46 60.65 65.84 60.65 65.84 60.39 64.46 60.39 64.46 59.29 65.84 59.29 65.84 59.03 64.46 59.03 64.46 57.93 65.84 57.93 65.84 57.67 64.46 57.67 64.46 56.57 65.84 56.57 65.84 55.63 64.46 55.63 64.46 54.53 65.84 54.53 65.84 54.27 64.46 54.27 64.46 53.17 65.84 53.17 65.84 52.91 64.46 52.91 64.46 51.81 65.84 51.81 65.84 50.87 64.46 50.87 64.46 49.77 65.84 49.77 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 47.47 64.46 47.47 64.46 46.37 65.84 46.37 65.84 46.11 64.46 46.11 64.46 45.01 65.84 45.01 65.84 44.75 64.46 44.75 64.46 43.65 65.84 43.65 65.84 43.39 64.46 43.39 64.46 42.29 65.84 42.29 65.84 42.03 64.46 42.03 64.46 40.93 65.84 40.93 65.84 40.67 64.46 40.67 64.46 39.57 65.84 39.57 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 32.51 64.46 32.51 64.46 31.41 65.84 31.41 65.84 31.15 64.46 31.15 64.46 30.05 65.84 30.05 65.84 29.79 64.46 29.79 64.46 28.69 65.84 28.69 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 27.07 64.46 27.07 64.46 25.97 65.84 25.97 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 22.99 64.46 22.99 64.46 21.89 65.84 21.89 65.84 21.63 64.46 21.63 64.46 20.53 65.84 20.53 65.84 20.27 64.46 20.27 64.46 19.17 65.84 19.17 65.84 18.91 64.46 18.91 64.46 17.81 65.84 17.81 65.84 17.55 64.46 17.55 64.46 16.45 65.84 16.45 65.84 16.19 64.46 16.19 64.46 15.09 65.84 15.09 65.84 14.15 64.46 14.15 64.46 13.05 65.84 13.05 65.84 12.79 64.46 12.79 64.46 11.69 65.84 11.69 65.84 11.43 64.46 11.43 64.46 10.33 65.84 10.33 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 4.63 64.46 4.63 64.46 3.53 65.84 3.53 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 86.64 ; LAYER met1 ; - POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER met5 ; - POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; + POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met4 ; - POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; + POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; LAYER li1 ; - RECT 0.17 0.17 67.91 86.87 ; + RECT 0.17 0.17 66.07 86.87 ; LAYER mcon ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; RECT 65.925 86.955 66.095 87.125 ; RECT 65.465 86.955 65.635 87.125 ; RECT 65.005 86.955 65.175 87.125 ; @@ -1577,134 +1586,130 @@ MACRO cbx_1__2_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 67.765 84.235 67.935 84.405 ; - RECT 67.305 84.235 67.475 84.405 ; + RECT 65.925 84.235 66.095 84.405 ; + RECT 65.465 84.235 65.635 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; + RECT 65.925 81.515 66.095 81.685 ; + RECT 65.465 81.515 65.635 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 67.765 78.795 67.935 78.965 ; - RECT 67.305 78.795 67.475 78.965 ; + RECT 65.925 78.795 66.095 78.965 ; + RECT 65.465 78.795 65.635 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; + RECT 65.925 76.075 66.095 76.245 ; + RECT 65.465 76.075 65.635 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1850,52 +1855,39 @@ MACRO cbx_1__2_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 86.965 56.195 87.115 ; - RECT 26.605 86.965 26.755 87.115 ; - RECT 59.265 85.265 59.415 85.415 ; - RECT 45.925 85.265 46.075 85.415 ; - RECT 11.885 1.625 12.035 1.775 ; - RECT 10.965 1.625 11.115 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 86.965 55.275 87.115 ; + RECT 25.685 86.965 25.835 87.115 ; + RECT 37.645 1.625 37.795 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 1.28 70.62 1.48 70.82 ; - RECT 1.28 64.5 1.48 64.7 ; - RECT 1.28 61.78 1.48 61.98 ; - RECT 66.6 60.42 66.8 60.62 ; - RECT 1.74 60.42 1.94 60.62 ; - RECT 1.28 57.02 1.48 57.22 ; - RECT 1.28 51.58 1.48 51.78 ; - RECT 1.28 50.22 1.48 50.42 ; - RECT 66.6 48.86 66.8 49.06 ; - RECT 1.28 44.1 1.48 44.3 ; - RECT 1.28 42.06 1.48 42.26 ; - RECT 1.74 39.34 1.94 39.54 ; - RECT 66.6 36.62 66.8 36.82 ; - RECT 1.74 31.86 1.94 32.06 ; - RECT 66.6 30.5 66.8 30.7 ; - RECT 1.28 29.82 1.48 30.02 ; - RECT 66.14 27.78 66.34 27.98 ; - RECT 1.74 26.42 1.94 26.62 ; - RECT 1.74 23.7 1.94 23.9 ; - RECT 66.14 22.34 66.34 22.54 ; - RECT 66.6 15.54 66.8 15.74 ; - RECT 1.28 15.54 1.48 15.74 ; - RECT 66.6 12.82 66.8 13.02 ; - RECT 66.14 3.3 66.34 3.5 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 64.76 78.78 64.96 78.98 ; + RECT 1.28 57.7 1.48 57.9 ; + RECT 1.28 47.5 1.48 47.7 ; + RECT 1.74 42.74 1.94 42.94 ; + RECT 1.74 41.38 1.94 41.58 ; + RECT 64.3 40.02 64.5 40.22 ; + RECT 1.28 40.02 1.48 40.22 ; + RECT 1.28 37.3 1.48 37.5 ; + RECT 1.28 27.1 1.48 27.3 ; + RECT 1.28 24.38 1.48 24.58 ; + RECT 64.76 18.26 64.96 18.46 ; + RECT 1.28 18.26 1.48 18.46 ; + RECT 1.28 12.14 1.48 12.34 ; + RECT 1.74 9.42 1.94 9.62 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 86.94 56.22 87.14 ; - RECT 26.58 86.94 26.78 87.14 ; - RECT 1.74 74.7 1.94 74.9 ; - RECT 66.14 51.58 66.34 51.78 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 86.94 55.3 87.14 ; + RECT 25.66 86.94 25.86 87.14 ; + RECT 1.74 38.66 1.94 38.86 ; + RECT 1.74 10.78 1.94 10.98 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; + POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; END END cbx_1__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef index 0e2544b..06d8f74 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cby_0__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 76.16 ; + SIZE 66.24 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 61.57 0 61.71 1.36 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -371,15 +371,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; + LAYER met4 ; + RECT 12.73 0 13.03 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,15 +387,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 0 16.63 1.36 ; + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,47 +403,47 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 0 64.47 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + LAYER met4 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + LAYER met4 ; + RECT 34.81 0 35.11 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + LAYER met4 ; + RECT 23.77 0 24.07 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 15.57 0 15.71 1.36 ; + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + LAYER met4 ; + RECT 32.97 0 33.27 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 61.49 0 61.79 1.36 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 39.41 0 39.71 1.36 ; + RECT 31.13 0 31.43 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 15.49 0 15.79 1.36 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 35.73 0 36.03 1.36 ; + RECT 27.45 0 27.75 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 59.65 0 59.95 1.36 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 57.81 0 58.11 1.36 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 37.57 0 37.87 1.36 ; + RECT 29.29 0 29.59 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,7 +531,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 74.8 53.89 76.16 ; + RECT 47.31 74.8 47.45 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -539,7 +539,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 74.8 55.27 76.16 ; + RECT 49.15 74.8 49.29 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,15 +547,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 74.8 65.39 76.16 ; + RECT 53.75 74.8 53.89 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 61.11 74.8 61.25 76.16 ; + LAYER met4 ; + RECT 46.77 74.8 47.07 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,31 +563,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; + RECT 57.43 74.8 57.57 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 17.41 74.8 17.55 76.16 ; + LAYER met4 ; + RECT 5.37 74.8 5.67 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.95 74.8 40.09 76.16 ; + LAYER met4 ; + RECT 27.45 74.8 27.75 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 60.19 74.8 60.33 76.16 ; + LAYER met4 ; + RECT 48.61 74.8 48.91 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,15 +595,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 74.8 59.41 76.16 ; + RECT 51.91 74.8 52.05 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.35 74.8 35.49 76.16 ; + LAYER met4 ; + RECT 52.29 74.8 52.59 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,15 +611,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 74.8 63.09 76.16 ; + RECT 56.05 74.8 56.19 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; + LAYER met4 ; + RECT 29.29 74.8 29.59 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,31 +627,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 74.8 41.93 76.16 ; + RECT 28.45 74.8 28.59 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 74.8 14.79 76.16 ; + LAYER met4 ; + RECT 7.21 74.8 7.51 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 74.8 16.63 76.16 ; + LAYER met4 ; + RECT 9.05 74.8 9.35 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.27 74.8 36.41 76.16 ; + LAYER met4 ; + RECT 50.45 74.8 50.75 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,7 +659,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 74.8 43.77 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -667,7 +667,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 74.8 57.57 76.16 ; + RECT 50.07 74.8 50.21 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -675,7 +675,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.57 74.8 15.71 76.16 ; + RECT 9.13 74.8 9.27 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -683,7 +683,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 74.8 58.49 76.16 ; + RECT 50.99 74.8 51.13 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; + RECT 40.87 74.8 41.01 76.16 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -699,7 +699,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -707,7 +707,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -715,7 +715,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,7 +723,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -731,7 +731,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 0 18.47 1.36 ; + RECT 8.21 0 8.35 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,7 +771,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 17.33 0 17.63 1.36 ; + RECT 36.65 0 36.95 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -779,7 +779,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 54.13 0 54.43 1.36 ; + RECT 44.93 0 45.23 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,7 +787,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -795,7 +795,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 0 13.87 1.36 ; + RECT 9.13 0 9.27 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,7 +819,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.41 0 17.55 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -827,7 +827,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 63.33 0 63.63 1.36 ; + RECT 56.89 0 57.19 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 33.89 0 34.19 1.36 ; + RECT 21.93 0 22.23 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,7 +851,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] @@ -859,7 +859,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 74.8 52.05 76.16 ; + RECT 61.11 74.8 61.25 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -867,7 +867,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 74.8 48.37 76.16 ; + RECT 60.19 74.8 60.33 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -875,7 +875,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 74.8 64.01 76.16 ; + RECT 44.55 74.8 44.69 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 74.8 62.17 76.16 ; + RECT 46.39 74.8 46.53 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; + RECT 58.35 74.8 58.49 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; + RECT 27.53 74.8 27.67 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 74.8 19.39 76.16 ; + RECT 33.05 74.8 33.19 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 74.8 34.57 76.16 ; + RECT 52.83 74.8 52.97 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 74.8 12.95 76.16 ; + RECT 10.05 74.8 10.19 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 74.8 18.47 76.16 ; + RECT 26.61 74.8 26.75 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 17.87 74.8 18.01 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 74.8 32.73 76.16 ; + RECT 48.23 74.8 48.37 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -963,7 +963,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 74.8 33.65 76.16 ; + RECT 32.13 74.8 32.27 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 74.8 41.01 76.16 ; + RECT 29.37 74.8 29.51 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 74.8 13.87 76.16 ; + RECT 30.29 74.8 30.43 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 74.8 25.83 76.16 ; + RECT 39.03 74.8 39.17 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 74.8 11.11 76.16 ; + RECT 8.21 74.8 8.35 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 74.8 12.03 76.16 ; + RECT 7.29 74.8 7.43 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,7 +1011,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 74.8 10.19 76.16 ; + RECT 31.21 74.8 31.35 76.16 ; END END chany_top_out[19] PIN left_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 19.25 0 19.39 1.36 ; END END left_grid_pin_0_[0] PIN ccff_tail[0] @@ -1027,7 +1027,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 51.53 68.08 51.83 ; + RECT 64.86 51.53 66.24 51.83 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1051,7 +1051,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 65.81 1.38 66.11 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN right_width_0_height_0__pin_0_[0] @@ -1059,7 +1059,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 20.17 0 20.31 1.36 ; END END right_width_0_height_0__pin_0_[0] PIN right_width_0_height_0__pin_1_upper[0] @@ -1067,7 +1067,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; + RECT 59.27 74.8 59.41 76.16 ; END END right_width_0_height_0__pin_1_upper[0] PIN right_width_0_height_0__pin_1_lower[0] @@ -1075,7 +1075,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END right_width_0_height_0__pin_1_lower[0] PIN VDD @@ -1084,43 +1084,43 @@ MACRO cby_0__1_ PORT LAYER met5 ; RECT 0 5.88 3.2 9.08 ; - RECT 64.88 5.88 68.08 9.08 ; + RECT 63.04 5.88 66.24 9.08 ; RECT 0 46.68 3.2 49.88 ; - RECT 64.88 46.68 68.08 49.88 ; + RECT 63.04 46.68 66.24 49.88 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 75.56 12.26 76.16 ; - RECT 41.1 75.56 41.7 76.16 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 75.56 11.34 76.16 ; + RECT 40.18 75.56 40.78 76.16 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; END END VDD PIN VSS @@ -1129,138 +1129,126 @@ MACRO cby_0__1_ PORT LAYER met5 ; RECT 0 26.28 3.2 29.48 ; - RECT 64.88 26.28 68.08 29.48 ; + RECT 63.04 26.28 66.24 29.48 ; RECT 0 67.08 3.2 70.28 ; - RECT 64.88 67.08 68.08 70.28 ; + RECT 63.04 67.08 66.24 70.28 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 75.56 26.98 76.16 ; - RECT 55.82 75.56 56.42 76.16 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 75.56 26.06 76.16 ; + RECT 54.9 75.56 55.5 76.16 ; LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; - RECT 0 75.92 68.08 76.16 ; + RECT 65.76 70.48 66.24 70.96 ; + RECT 0 75.92 66.24 76.16 ; END END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 37.65 74.8 37.79 76.16 ; - END - END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 68.08 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; + RECT 0 76.075 66.24 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 67.16 70.635 68.08 70.805 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 67.16 67.915 68.08 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; + RECT 65.32 65.195 66.24 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; + RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; + RECT 65.78 48.875 66.24 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 65.78 46.155 66.24 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 66.24 43.435 68.08 43.605 ; + RECT 62.56 43.435 66.24 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 66.24 40.715 68.08 40.885 ; + RECT 62.56 40.715 66.24 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 67.62 37.995 68.08 38.165 ; + RECT 62.56 37.995 66.24 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 66.24 35.275 68.08 35.445 ; + RECT 62.56 35.275 66.24 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 66.24 32.555 68.08 32.725 ; + RECT 62.56 32.555 66.24 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; + RECT 64.4 29.835 66.24 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; + RECT 65.78 27.115 66.24 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; + RECT 65.78 24.395 66.24 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 64.4 21.675 68.08 21.845 ; + RECT 65.78 21.675 66.24 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 64.4 18.955 68.08 19.125 ; + RECT 62.56 18.955 66.24 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 66.24 16.235 68.08 16.405 ; + RECT 62.56 16.235 66.24 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 66.24 13.515 68.08 13.685 ; + RECT 62.56 13.515 66.24 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 67.16 10.795 68.08 10.965 ; + RECT 62.56 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; - RECT 55.98 75.975 56.26 76.345 ; - RECT 26.54 75.975 26.82 76.345 ; - POLYGON 45.61 74.53 45.61 69.97 45.47 69.97 45.47 74.39 44.55 74.39 44.55 74.52 44.97 74.52 44.97 74.53 ; - RECT 24.71 1.54 24.97 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 75.88 67.8 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 0.28 0.28 0.28 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.29 75.88 15.29 74.52 15.99 74.52 15.99 75.88 16.21 75.88 16.21 74.52 16.91 74.52 16.91 75.88 17.13 75.88 17.13 74.52 17.83 74.52 17.83 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 25.41 75.88 25.41 74.52 26.11 74.52 26.11 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 58.07 75.88 58.07 74.52 58.77 74.52 58.77 75.88 58.99 75.88 58.99 74.52 59.69 74.52 59.69 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 62.67 75.88 62.67 74.52 63.37 74.52 63.37 75.88 63.59 75.88 63.59 74.52 64.29 74.52 64.29 75.88 64.97 75.88 64.97 74.52 65.67 74.52 65.67 75.88 ; + RECT 55.06 75.975 55.34 76.345 ; + RECT 25.62 75.975 25.9 76.345 ; + RECT 31.61 74.3 31.87 74.62 ; + RECT 57.37 1.54 57.63 1.86 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 75.88 65.96 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 0.28 0.28 0.28 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 17.59 75.88 17.59 74.52 18.29 74.52 18.29 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 58.07 75.88 58.07 74.52 58.77 74.52 58.77 75.88 58.99 75.88 58.99 74.52 59.69 74.52 59.69 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 ; LAYER met4 ; - POLYGON 67.68 75.76 67.68 0.4 64.03 0.4 64.03 1.76 62.93 1.76 62.93 0.4 62.19 0.4 62.19 1.76 61.09 1.76 61.09 0.4 60.35 0.4 60.35 1.76 59.25 1.76 59.25 0.4 58.51 0.4 58.51 1.76 57.41 1.76 57.41 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 54.83 0.4 54.83 1.76 53.73 1.76 53.73 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 40.11 0.4 40.11 1.76 39.01 1.76 39.01 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 36.43 0.4 36.43 1.76 35.33 1.76 35.33 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 18.03 0.4 18.03 1.76 16.93 1.76 16.93 0.4 16.19 0.4 16.19 1.76 15.09 1.76 15.09 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; + POLYGON 65.84 75.76 65.84 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 37.35 0.4 37.35 1.76 36.25 1.76 36.25 0.4 35.51 0.4 35.51 1.76 34.41 1.76 34.41 0.4 33.67 0.4 33.67 1.76 32.57 1.76 32.57 0.4 31.83 0.4 31.83 1.76 30.73 1.76 30.73 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 13.43 0.4 13.43 1.76 12.33 1.76 12.33 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 75.76 4.97 75.76 4.97 74.4 6.07 74.4 6.07 75.76 6.81 75.76 6.81 74.4 7.91 74.4 7.91 75.76 8.65 75.76 8.65 74.4 9.75 74.4 9.75 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 27.05 75.76 27.05 74.4 28.15 74.4 28.15 75.76 28.89 75.76 28.89 74.4 29.99 74.4 29.99 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 46.37 75.76 46.37 74.4 47.47 74.4 47.47 75.76 48.21 75.76 48.21 74.4 49.31 74.4 49.31 75.76 50.05 75.76 50.05 74.4 51.15 74.4 51.15 75.76 51.89 75.76 51.89 74.4 52.99 74.4 52.99 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met3 ; - POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; - POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 75.76 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 0.4 0.4 0.4 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 75.76 ; + POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; + POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 75.76 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 0.4 0.4 0.4 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 75.76 ; LAYER met1 ; - POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER met5 ; - POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; + POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER li1 ; - RECT 0.17 0.17 67.91 75.99 ; + RECT 0.17 0.17 66.07 75.99 ; LAYER mcon ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; - RECT 66.845 76.075 67.015 76.245 ; - RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1405,118 +1393,114 @@ MACRO cby_0__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1662,22 +1646,27 @@ MACRO cby_0__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 76.085 56.195 76.235 ; - RECT 26.605 76.085 26.755 76.235 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 76.085 55.275 76.235 ; + RECT 25.685 76.085 25.835 76.235 ; + RECT 44.545 74.385 44.695 74.535 ; + RECT 30.285 74.385 30.435 74.535 ; + RECT 60.185 1.625 60.335 1.775 ; + RECT 9.125 1.625 9.275 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 64.3 51.58 64.5 51.78 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; + POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; END END cby_0__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef index 8f98901..034db54 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cby_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 76.16 ; + SIZE 66.24 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -371,7 +371,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,7 +387,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 21.55 0 21.69 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + RECT 31.67 0 31.81 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 44.09 0 44.23 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 22.47 0 22.61 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.19 0 37.33 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; + RECT 8.67 0 8.81 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,7 +531,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; + RECT 38.11 74.8 38.25 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -539,7 +539,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 74.8 35.03 76.16 ; + RECT 19.25 74.8 19.39 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,7 +547,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 74.8 31.35 76.16 ; + RECT 29.37 74.8 29.51 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -555,7 +555,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 74.8 52.05 76.16 ; + RECT 40.41 74.8 40.55 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,7 +563,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.23 74.8 25.37 76.16 ; + RECT 32.59 74.8 32.73 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -571,7 +571,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 74.8 60.33 76.16 ; + RECT 49.61 74.8 49.75 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -579,7 +579,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 74.8 22.61 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -587,7 +587,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 74.8 50.21 76.16 ; + RECT 47.77 74.8 47.91 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,7 +595,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 74.8 58.03 76.16 ; + RECT 56.97 74.8 57.11 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -603,7 +603,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 74.8 45.61 76.16 ; + RECT 48.69 74.8 48.83 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,7 +611,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 74.8 24.45 76.16 ; + RECT 30.29 74.8 30.43 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -619,7 +619,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 74.8 49.29 76.16 ; + RECT 45.93 74.8 46.07 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,7 +627,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 74.8 16.17 76.16 ; + RECT 54.21 74.8 54.35 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -635,7 +635,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 74.8 61.25 76.16 ; + RECT 50.53 74.8 50.67 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -643,7 +643,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 74.8 23.53 76.16 ; + RECT 8.67 74.8 8.81 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -651,7 +651,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 74.8 62.17 76.16 ; + RECT 62.49 74.8 62.63 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,7 +659,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 74.8 57.11 76.16 ; + RECT 56.05 74.8 56.19 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -667,7 +667,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; + RECT 61.57 74.8 61.71 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -675,7 +675,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; + RECT 28.45 74.8 28.59 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -683,7 +683,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 74.8 63.09 76.16 ; + RECT 63.41 74.8 63.55 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 65.13 1.38 65.43 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -699,7 +699,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + RECT 38.11 0 38.25 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -707,15 +707,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; + LAYER met4 ; + RECT 42.17 0 42.47 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,7 +723,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -731,7 +731,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 30.75 0 30.89 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,15 +771,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 38.49 0 38.79 1.36 ; + LAYER met2 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,15 +787,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + LAYER met4 ; + RECT 37.57 0 37.87 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,7 +819,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -827,7 +827,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,7 +851,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] @@ -859,7 +859,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 74.8 41.01 76.16 ; + RECT 51.45 74.8 51.59 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -867,7 +867,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 74.8 41.93 76.16 ; + RECT 43.17 74.8 43.31 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -875,7 +875,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; + RECT 53.29 74.8 53.43 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; + RECT 44.09 74.8 44.23 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 74.8 33.19 76.16 ; + RECT 39.49 74.8 39.63 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 74.8 36.87 76.16 ; + RECT 33.51 74.8 33.65 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 74.8 34.11 76.16 ; + RECT 21.09 74.8 21.23 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 74.8 46.99 76.16 ; + RECT 34.43 74.8 34.57 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 74.8 40.09 76.16 ; + RECT 22.01 74.8 22.15 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 74.8 55.27 76.16 ; + RECT 41.33 74.8 41.47 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 74.8 43.77 76.16 ; + RECT 42.25 74.8 42.39 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 74.8 47.91 76.16 ; + RECT 45.01 74.8 45.15 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -955,7 +955,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; + RECT 36.73 74.8 36.87 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -963,7 +963,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 74.8 20.77 76.16 ; + RECT 35.35 74.8 35.49 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 74.8 53.89 76.16 ; + RECT 22.93 74.8 23.07 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 74.8 21.69 76.16 ; + RECT 31.21 74.8 31.35 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 74.8 32.27 76.16 ; + RECT 52.37 74.8 52.51 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 74.8 35.95 76.16 ; + RECT 20.17 74.8 20.31 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.11 74.8 38.25 76.16 ; + RECT 23.85 74.8 23.99 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,7 +1011,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; + RECT 46.85 74.8 46.99 76.16 ; END END chany_top_out[19] PIN left_grid_pin_16_[0] @@ -1019,7 +1019,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 27.05 1.38 27.35 ; END END left_grid_pin_16_[0] PIN left_grid_pin_17_[0] @@ -1027,7 +1027,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 32.49 1.38 32.79 ; END END left_grid_pin_17_[0] PIN left_grid_pin_18_[0] @@ -1035,7 +1035,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 4.61 1.38 4.91 ; END END left_grid_pin_18_[0] PIN left_grid_pin_19_[0] @@ -1043,7 +1043,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 31.13 1.38 31.43 ; END END left_grid_pin_19_[0] PIN left_grid_pin_20_[0] @@ -1051,7 +1051,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; + RECT 0 8.69 1.38 8.99 ; END END left_grid_pin_20_[0] PIN left_grid_pin_21_[0] @@ -1059,7 +1059,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 4.61 1.38 4.91 ; + RECT 0 5.97 1.38 6.27 ; END END left_grid_pin_21_[0] PIN left_grid_pin_22_[0] @@ -1067,7 +1067,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 7.33 1.38 7.63 ; END END left_grid_pin_22_[0] PIN left_grid_pin_23_[0] @@ -1075,7 +1075,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 12.77 1.38 13.07 ; END END left_grid_pin_23_[0] PIN left_grid_pin_24_[0] @@ -1083,7 +1083,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.97 1.38 6.27 ; + RECT 0 25.69 1.38 25.99 ; END END left_grid_pin_24_[0] PIN left_grid_pin_25_[0] @@ -1091,7 +1091,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 24.33 1.38 24.63 ; END END left_grid_pin_25_[0] PIN left_grid_pin_26_[0] @@ -1099,7 +1099,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 7.33 1.38 7.63 ; + RECT 0 14.13 1.38 14.43 ; END END left_grid_pin_26_[0] PIN left_grid_pin_27_[0] @@ -1107,7 +1107,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 52.89 1.38 53.19 ; END END left_grid_pin_27_[0] PIN left_grid_pin_28_[0] @@ -1123,7 +1123,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 29.77 1.38 30.07 ; END END left_grid_pin_29_[0] PIN left_grid_pin_30_[0] @@ -1131,7 +1131,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 28.41 1.38 28.71 ; END END left_grid_pin_30_[0] PIN left_grid_pin_31_[0] @@ -1147,7 +1147,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 51.53 68.08 51.83 ; + RECT 64.86 51.53 66.24 51.83 ; END END ccff_tail[0] PIN VDD @@ -1156,43 +1156,43 @@ MACRO cby_1__1_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; LAYER met5 ; RECT 0 5.88 3.2 9.08 ; - RECT 64.88 5.88 68.08 9.08 ; + RECT 63.04 5.88 66.24 9.08 ; RECT 0 46.68 3.2 49.88 ; - RECT 64.88 46.68 68.08 49.88 ; + RECT 63.04 46.68 66.24 49.88 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 75.56 12.26 76.16 ; - RECT 41.1 75.56 41.7 76.16 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 75.56 11.34 76.16 ; + RECT 40.18 75.56 40.78 76.16 ; END END VDD PIN VSS @@ -1200,44 +1200,44 @@ MACRO cby_1__1_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; - RECT 0 75.92 68.08 76.16 ; + RECT 65.76 70.48 66.24 70.96 ; + RECT 0 75.92 66.24 76.16 ; LAYER met5 ; RECT 0 26.28 3.2 29.48 ; - RECT 64.88 26.28 68.08 29.48 ; + RECT 63.04 26.28 66.24 29.48 ; RECT 0 67.08 3.2 70.28 ; - RECT 64.88 67.08 68.08 70.28 ; + RECT 63.04 67.08 66.24 70.28 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 75.56 26.98 76.16 ; - RECT 55.82 75.56 56.42 76.16 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 75.56 26.06 76.16 ; + RECT 54.9 75.56 55.5 76.16 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] @@ -1245,7 +1245,7 @@ MACRO cby_1__1_ USE CLOCK ; PORT LAYER met3 ; - RECT 66.7 9.37 68.08 9.67 ; + RECT 64.86 9.37 66.24 9.67 ; END END prog_clk__FEEDTHRU_1[0] PIN prog_clk__FEEDTHRU_2[0] @@ -1253,112 +1253,93 @@ MACRO cby_1__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 27.99 74.8 28.13 76.16 ; + RECT 27.07 74.8 27.21 76.16 ; END END prog_clk__FEEDTHRU_2[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 68.08 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; + RECT 0 76.075 66.24 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 67.16 70.635 68.08 70.805 ; + RECT 65.32 70.635 66.24 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 67.16 67.915 68.08 68.085 ; + RECT 65.32 67.915 66.24 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; + RECT 65.32 65.195 66.24 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; + RECT 62.56 62.475 66.24 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; + RECT 62.56 59.755 66.24 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; + RECT 65.32 57.035 66.24 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 65.32 54.315 66.24 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 65.32 51.595 66.24 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; + RECT 65.32 48.875 66.24 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 67.16 43.435 68.08 43.605 ; + RECT 65.78 43.435 66.24 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 67.16 40.715 68.08 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 67.16 37.995 68.08 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 67.16 35.275 68.08 35.445 ; + RECT 65.32 40.715 66.24 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 65.32 37.995 66.24 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 67.16 32.555 68.08 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; + RECT 65.32 32.555 66.24 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 65.32 29.835 66.24 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 65.32 27.115 66.24 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 67.16 21.675 68.08 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 67.16 18.955 68.08 19.125 ; + RECT 65.32 24.395 66.24 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 65.32 21.675 66.24 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 67.16 16.235 68.08 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 64.4 13.515 68.08 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 64.4 10.795 68.08 10.965 ; + RECT 65.32 16.235 66.24 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 65.32 13.515 66.24 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.32 5.355 66.24 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; - RECT 55.98 75.975 56.26 76.345 ; - RECT 26.54 75.975 26.82 76.345 ; - RECT 48.17 74.3 48.43 74.62 ; - RECT 22.87 74.3 23.13 74.62 ; - RECT 41.73 1.54 41.99 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 75.88 67.8 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 20.35 75.88 20.35 74.52 21.05 74.52 21.05 75.88 21.27 75.88 21.27 74.52 21.97 74.52 21.97 75.88 22.19 75.88 22.19 74.52 22.89 74.52 22.89 75.88 23.11 75.88 23.11 74.52 23.81 74.52 23.81 75.88 24.03 75.88 24.03 74.52 24.73 74.52 24.73 75.88 24.95 75.88 24.95 74.52 25.65 74.52 25.65 75.88 27.71 75.88 27.71 74.52 28.41 74.52 28.41 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 34.61 75.88 34.61 74.52 35.31 74.52 35.31 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 57.61 75.88 57.61 74.52 58.31 74.52 58.31 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 62.67 75.88 62.67 74.52 63.37 74.52 63.37 75.88 ; + RECT 55.06 75.975 55.34 76.345 ; + RECT 25.62 75.975 25.9 76.345 ; + RECT 45.41 74.3 45.67 74.62 ; + RECT 37.59 74.3 37.85 74.62 ; + RECT 27.93 74.3 28.19 74.62 ; + RECT 46.33 1.54 46.59 1.86 ; + RECT 19.19 1.54 19.45 1.86 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 75.88 65.96 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 0.28 0.28 0.28 75.88 8.39 75.88 8.39 74.52 9.09 74.52 9.09 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.79 75.88 26.79 74.52 27.49 74.52 27.49 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 45.65 75.88 45.65 74.52 46.35 74.52 46.35 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.41 75.88 48.41 74.52 49.11 74.52 49.11 75.88 49.33 75.88 49.33 74.52 50.03 74.52 50.03 75.88 50.25 75.88 50.25 74.52 50.95 74.52 50.95 75.88 51.17 75.88 51.17 74.52 51.87 74.52 51.87 75.88 52.09 75.88 52.09 74.52 52.79 74.52 52.79 75.88 53.01 75.88 53.01 74.52 53.71 74.52 53.71 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 61.29 75.88 61.29 74.52 61.99 74.52 61.99 75.88 62.21 75.88 62.21 74.52 62.91 74.52 62.91 75.88 63.13 75.88 63.13 74.52 63.83 74.52 63.83 75.88 ; LAYER met3 ; - POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; - POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; - POLYGON 3.83 52.51 3.83 52.21 1.23 52.21 1.23 52.49 1.78 52.49 1.78 52.51 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 75.76 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 10.07 66.3 10.07 66.3 8.97 67.68 8.97 67.68 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 75.76 ; + POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; + POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 75.76 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 75.76 ; LAYER met4 ; - POLYGON 67.68 75.76 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; + POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 42.87 0.4 42.87 1.76 41.77 1.76 41.77 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met5 ; - POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; + POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER met1 ; - POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER li1 ; - RECT 0.17 0.17 67.91 75.99 ; + RECT 0.17 0.17 66.07 75.99 ; LAYER mcon ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; - RECT 66.845 76.075 67.015 76.245 ; - RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1503,118 +1484,114 @@ MACRO cby_1__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1760,33 +1737,36 @@ MACRO cby_1__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 76.085 56.195 76.235 ; - RECT 26.605 76.085 26.755 76.235 ; - RECT 62.025 74.385 62.175 74.535 ; - RECT 52.825 74.385 52.975 74.535 ; - RECT 29.365 74.385 29.515 74.535 ; - RECT 22.925 1.625 23.075 1.775 ; - RECT 8.205 1.625 8.355 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 76.085 55.275 76.235 ; + RECT 25.685 76.085 25.835 76.235 ; + RECT 43.165 74.385 43.315 74.535 ; + RECT 33.505 74.385 33.655 74.535 ; + RECT 30.285 74.385 30.435 74.535 ; + RECT 57.425 1.625 57.575 1.775 ; + RECT 43.165 1.625 43.315 1.775 ; + RECT 33.505 1.625 33.655 1.775 ; + RECT 8.665 1.625 8.815 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 1.28 54.3 1.48 54.5 ; - RECT 66.14 51.58 66.34 51.78 ; - RECT 1.74 48.86 1.94 49.06 ; - RECT 1.28 25.74 1.48 25.94 ; - RECT 1.28 6.02 1.48 6.22 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 1.28 65.18 1.48 65.38 ; + RECT 64.76 51.58 64.96 51.78 ; + RECT 1.28 51.58 1.48 51.78 ; + RECT 1.28 31.18 1.48 31.38 ; + RECT 1.28 14.18 1.48 14.38 ; + RECT 1.28 7.38 1.48 7.58 ; + RECT 1.28 4.66 1.48 4.86 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 1.74 29.82 1.94 30.02 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; + POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; END END cby_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef index e70b66d..4680740 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef @@ -356,7 +356,7 @@ END unithddbl MACRO cby_2__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 68.08 BY 76.16 ; + SIZE 66.24 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; @@ -371,7 +371,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,7 +387,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 38.11 0 38.25 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.43 0 11.57 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 0 14.33 1.36 ; + RECT 31.67 0 31.81 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.35 0 12.49 1.36 ; + RECT 20.17 0 20.31 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 37.19 0 37.33 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.51 0 10.65 1.36 ; + RECT 16.49 0 16.63 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 13.73 0 13.87 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 0 9.73 1.36 ; + RECT 14.65 0 14.79 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 15.57 0 15.71 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 0 15.25 1.36 ; + RECT 22.01 0 22.15 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 0 16.17 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 0 13.41 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; + RECT 6.37 0 6.51 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,15 +531,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; + RECT 38.11 74.8 38.25 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 51.45 74.8 51.59 76.16 ; + LAYER met4 ; + RECT 32.97 74.8 33.27 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,7 +547,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 74.8 49.75 76.16 ; + RECT 56.05 74.8 56.19 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -555,7 +555,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 74.8 12.03 76.16 ; + RECT 15.11 74.8 15.25 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,7 +563,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 74.8 13.87 76.16 ; + RECT 11.43 74.8 11.57 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -571,7 +571,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 74.8 11.11 76.16 ; + RECT 16.03 74.8 16.17 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -579,7 +579,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 74.8 30.89 76.16 ; + RECT 40.41 74.8 40.55 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -587,7 +587,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 22.01 74.8 22.15 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,7 +595,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.13 74.8 9.27 76.16 ; + RECT 31.67 74.8 31.81 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -603,7 +603,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 74.8 7.43 76.16 ; + RECT 12.35 74.8 12.49 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,7 +611,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 74.8 25.83 76.16 ; + RECT 45.93 74.8 46.07 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -619,7 +619,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; + RECT 8.21 74.8 8.35 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,7 +627,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 74.8 18.47 76.16 ; + RECT 33.05 74.8 33.19 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -635,7 +635,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 74.8 12.95 76.16 ; + RECT 6.37 74.8 6.51 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -643,7 +643,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 74.8 50.67 76.16 ; + RECT 41.33 74.8 41.47 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -651,7 +651,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 74.8 38.71 76.16 ; + RECT 23.39 74.8 23.53 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,7 +659,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 74.8 17.09 76.16 ; + RECT 26.61 74.8 26.75 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -667,7 +667,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + RECT 19.71 74.8 19.85 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -675,7 +675,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 74.8 19.39 76.16 ; + RECT 45.01 74.8 45.15 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -683,7 +683,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 74.8 16.17 76.16 ; + RECT 5.45 74.8 5.59 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 65.13 1.38 65.43 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -707,7 +707,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 35.73 0 36.03 1.36 ; + RECT 37.57 0 37.87 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -715,7 +715,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 33.89 0 34.19 1.36 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,7 +723,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -731,7 +731,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,7 +771,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 18.25 0 18.55 1.36 ; + RECT 33.89 0 34.19 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -779,7 +779,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 16.41 0 16.71 1.36 ; + RECT 27.45 0 27.75 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,7 +787,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 21.09 0 21.23 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -795,7 +795,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,7 +819,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 35.35 0 35.49 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -827,7 +827,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,15 +851,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 74.8 24.99 76.16 ; + LAYER met2 ; + RECT 29.83 74.8 29.97 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -867,7 +867,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -875,7 +875,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 22.85 74.8 23.15 76.16 ; + RECT 31.13 74.8 31.43 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 21.09 74.8 21.23 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 74.8 10.19 76.16 ; + RECT 28.45 74.8 28.59 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 27.53 74.8 27.67 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 74.8 39.63 76.16 ; + RECT 43.63 74.8 43.77 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 74.8 52.51 76.16 ; + RECT 37.19 74.8 37.33 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 74.8 57.11 76.16 ; + RECT 46.85 74.8 46.99 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 74.8 37.79 76.16 ; + RECT 39.03 74.8 39.17 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 74.8 6.05 76.16 ; + RECT 14.19 74.8 14.33 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 74.8 29.05 76.16 ; + RECT 36.27 74.8 36.41 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -955,7 +955,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 16.95 74.8 17.09 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -963,7 +963,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 74.8 34.57 76.16 ; + RECT 18.33 74.8 18.47 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 74.8 40.55 76.16 ; + RECT 30.75 74.8 30.89 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 74.8 44.23 76.16 ; + RECT 34.43 74.8 34.57 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 74.8 29.97 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 74.8 54.35 76.16 ; + RECT 47.77 74.8 47.91 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 74.8 55.27 76.16 ; + RECT 48.69 74.8 48.83 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,15 +1011,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 74.8 53.43 76.16 ; + RECT 35.35 74.8 35.49 76.16 ; END END chany_top_out[19] PIN right_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 21.93 0 22.23 1.36 ; + LAYER met3 ; + RECT 64.86 14.81 66.24 15.11 ; END END right_grid_pin_0_[0] PIN left_grid_pin_16_[0] @@ -1027,7 +1027,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 27.05 1.38 27.35 ; END END left_grid_pin_16_[0] PIN left_grid_pin_17_[0] @@ -1035,7 +1035,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 32.49 1.38 32.79 ; END END left_grid_pin_17_[0] PIN left_grid_pin_18_[0] @@ -1043,7 +1043,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 4.61 1.38 4.91 ; END END left_grid_pin_18_[0] PIN left_grid_pin_19_[0] @@ -1051,7 +1051,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 31.13 1.38 31.43 ; END END left_grid_pin_19_[0] PIN left_grid_pin_20_[0] @@ -1059,7 +1059,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; + RECT 0 8.69 1.38 8.99 ; END END left_grid_pin_20_[0] PIN left_grid_pin_21_[0] @@ -1067,7 +1067,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 4.61 1.38 4.91 ; + RECT 0 5.97 1.38 6.27 ; END END left_grid_pin_21_[0] PIN left_grid_pin_22_[0] @@ -1075,7 +1075,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 7.33 1.38 7.63 ; END END left_grid_pin_22_[0] PIN left_grid_pin_23_[0] @@ -1083,7 +1083,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 12.77 1.38 13.07 ; END END left_grid_pin_23_[0] PIN left_grid_pin_24_[0] @@ -1091,7 +1091,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.97 1.38 6.27 ; + RECT 0 25.69 1.38 25.99 ; END END left_grid_pin_24_[0] PIN left_grid_pin_25_[0] @@ -1099,7 +1099,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 24.33 1.38 24.63 ; END END left_grid_pin_25_[0] PIN left_grid_pin_26_[0] @@ -1107,7 +1107,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 7.33 1.38 7.63 ; + RECT 0 14.13 1.38 14.43 ; END END left_grid_pin_26_[0] PIN left_grid_pin_27_[0] @@ -1115,7 +1115,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 52.89 1.38 53.19 ; END END left_grid_pin_27_[0] PIN left_grid_pin_28_[0] @@ -1131,7 +1131,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 29.77 1.38 30.07 ; END END left_grid_pin_29_[0] PIN left_grid_pin_30_[0] @@ -1139,7 +1139,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 28.41 1.38 28.71 ; END END left_grid_pin_30_[0] PIN left_grid_pin_31_[0] @@ -1155,7 +1155,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 0 7.89 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1163,7 +1163,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 38.61 68.08 38.91 ; + RECT 64.86 38.61 66.24 38.91 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1171,7 +1171,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 18.89 68.08 19.19 ; + RECT 64.86 18.89 66.24 19.19 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1179,15 +1179,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 66.7 17.53 68.08 17.83 ; + RECT 64.86 3.25 66.24 3.55 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN left_width_0_height_0__pin_0_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 20.09 0 20.39 1.36 ; + LAYER met3 ; + RECT 64.86 16.17 66.24 16.47 ; END END left_width_0_height_0__pin_0_[0] PIN left_width_0_height_0__pin_1_upper[0] @@ -1195,7 +1195,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.65 74.8 14.79 76.16 ; + RECT 13.27 74.8 13.41 76.16 ; END END left_width_0_height_0__pin_1_upper[0] PIN left_width_0_height_0__pin_1_lower[0] @@ -1203,7 +1203,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END left_width_0_height_0__pin_1_lower[0] PIN VDD @@ -1212,43 +1212,43 @@ MACRO cby_2__1_ PORT LAYER met5 ; RECT 0 5.88 3.2 9.08 ; - RECT 64.88 5.88 68.08 9.08 ; + RECT 63.04 5.88 66.24 9.08 ; RECT 0 46.68 3.2 49.88 ; - RECT 64.88 46.68 68.08 49.88 ; + RECT 63.04 46.68 66.24 49.88 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 67.6 13.36 68.08 13.84 ; + RECT 65.76 13.36 66.24 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 67.6 18.8 68.08 19.28 ; + RECT 65.76 18.8 66.24 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 67.6 24.24 68.08 24.72 ; + RECT 65.76 24.24 66.24 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 67.6 29.68 68.08 30.16 ; + RECT 65.76 29.68 66.24 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 67.6 35.12 68.08 35.6 ; + RECT 65.76 35.12 66.24 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 67.6 40.56 68.08 41.04 ; + RECT 65.76 40.56 66.24 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 67.6 46 68.08 46.48 ; + RECT 65.76 46 66.24 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 67.6 51.44 68.08 51.92 ; + RECT 65.76 51.44 66.24 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 67.6 56.88 68.08 57.36 ; + RECT 65.76 56.88 66.24 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 67.6 62.32 68.08 62.8 ; + RECT 65.76 62.32 66.24 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 67.6 67.76 68.08 68.24 ; + RECT 65.76 67.76 66.24 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 67.6 73.2 68.08 73.68 ; + RECT 65.76 73.2 66.24 73.68 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 11.66 75.56 12.26 76.16 ; - RECT 41.1 75.56 41.7 76.16 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 10.74 75.56 11.34 76.16 ; + RECT 40.18 75.56 40.78 76.16 ; END END VDD PIN VSS @@ -1257,139 +1257,129 @@ MACRO cby_2__1_ PORT LAYER met5 ; RECT 0 26.28 3.2 29.48 ; - RECT 64.88 26.28 68.08 29.48 ; + RECT 63.04 26.28 66.24 29.48 ; RECT 0 67.08 3.2 70.28 ; - RECT 64.88 67.08 68.08 70.28 ; + RECT 63.04 67.08 66.24 70.28 ; LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; + RECT 65.76 5.2 66.24 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 67.6 10.64 68.08 11.12 ; + RECT 65.76 10.64 66.24 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 67.6 16.08 68.08 16.56 ; + RECT 65.76 16.08 66.24 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 67.6 21.52 68.08 22 ; + RECT 65.76 21.52 66.24 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 67.6 26.96 68.08 27.44 ; + RECT 65.76 26.96 66.24 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 67.6 32.4 68.08 32.88 ; + RECT 65.76 32.4 66.24 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 67.6 37.84 68.08 38.32 ; + RECT 65.76 37.84 66.24 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 67.6 43.28 68.08 43.76 ; + RECT 65.76 43.28 66.24 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 67.6 48.72 68.08 49.2 ; + RECT 65.76 48.72 66.24 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 67.6 54.16 68.08 54.64 ; + RECT 65.76 54.16 66.24 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 67.6 59.6 68.08 60.08 ; + RECT 65.76 59.6 66.24 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 67.6 65.04 68.08 65.52 ; + RECT 65.76 65.04 66.24 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 67.6 70.48 68.08 70.96 ; - RECT 0 75.92 68.08 76.16 ; + RECT 65.76 70.48 66.24 70.96 ; + RECT 0 75.92 66.24 76.16 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 75.56 26.98 76.16 ; - RECT 55.82 75.56 56.42 76.16 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 75.56 26.06 76.16 ; + RECT 54.9 75.56 55.5 76.16 ; END END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 74.8 3.29 76.16 ; - END - END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 68.08 76.245 ; - RECT 67.16 73.355 68.08 73.525 ; + RECT 0 76.075 66.24 76.245 ; + RECT 65.32 73.355 66.24 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 67.16 70.635 68.08 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 67.16 67.915 68.08 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 67.16 65.195 68.08 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 67.16 62.475 68.08 62.645 ; + RECT 65.32 70.635 66.24 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 65.32 67.915 66.24 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 65.32 65.195 66.24 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 65.32 62.475 66.24 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 67.16 59.755 68.08 59.925 ; + RECT 65.32 59.755 66.24 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 67.16 57.035 68.08 57.205 ; + RECT 65.32 57.035 66.24 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 67.16 54.315 68.08 54.485 ; + RECT 65.32 54.315 66.24 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 67.16 51.595 68.08 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 67.16 48.875 68.08 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 67.16 46.155 68.08 46.325 ; + RECT 65.32 51.595 66.24 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 65.32 48.875 66.24 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 65.32 46.155 66.24 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 67.16 43.435 68.08 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 67.16 40.715 68.08 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 67.16 37.995 68.08 38.165 ; + RECT 65.32 43.435 66.24 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 65.32 40.715 66.24 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 65.32 37.995 66.24 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 67.16 35.275 68.08 35.445 ; + RECT 65.32 35.275 66.24 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 67.16 32.555 68.08 32.725 ; + RECT 65.32 32.555 66.24 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 67.16 29.835 68.08 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 67.16 27.115 68.08 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 67.16 24.395 68.08 24.565 ; + RECT 65.32 29.835 66.24 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 65.32 27.115 66.24 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 65.32 24.395 66.24 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 67.16 21.675 68.08 21.845 ; + RECT 65.32 21.675 66.24 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 67.16 18.955 68.08 19.125 ; + RECT 65.32 18.955 66.24 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 67.16 16.235 68.08 16.405 ; + RECT 65.32 16.235 66.24 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 67.16 13.515 68.08 13.685 ; + RECT 65.32 13.515 66.24 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 67.16 10.795 68.08 10.965 ; + RECT 65.32 10.795 66.24 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.78 8.075 66.24 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.32 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met3 ; - POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; - POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; - POLYGON 3.83 29.39 3.83 29.09 1.99 29.09 1.99 28.41 1.78 28.41 1.78 29.11 1.69 29.11 1.69 29.39 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 75.76 67.68 39.31 66.3 39.31 66.3 38.21 67.68 38.21 67.68 19.59 66.3 19.59 66.3 18.49 67.68 18.49 67.68 18.23 66.3 18.23 66.3 17.13 67.68 17.13 67.68 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 75.76 ; + POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; + POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 75.76 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 19.59 64.46 19.59 64.46 18.49 65.84 18.49 65.84 16.87 64.46 16.87 64.46 15.77 65.84 15.77 65.84 15.51 64.46 15.51 64.46 14.41 65.84 14.41 65.84 3.95 64.46 3.95 64.46 2.85 65.84 2.85 65.84 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 75.76 ; LAYER met2 ; - RECT 55.98 75.975 56.26 76.345 ; - RECT 26.54 75.975 26.82 76.345 ; + RECT 55.06 75.975 55.34 76.345 ; + RECT 25.62 75.975 25.9 76.345 ; RECT 40.81 74.3 41.07 74.62 ; - RECT 34.83 1.54 35.09 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 75.88 67.8 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 15.53 0.28 15.53 1.64 14.83 1.64 14.83 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.69 0.28 13.69 1.64 12.99 1.64 12.99 0.28 12.77 0.28 12.77 1.64 12.07 1.64 12.07 0.28 11.85 0.28 11.85 1.64 11.15 1.64 11.15 0.28 10.93 0.28 10.93 1.64 10.23 1.64 10.23 0.28 10.01 0.28 10.01 1.64 9.31 1.64 9.31 0.28 8.17 0.28 8.17 1.64 7.47 1.64 7.47 0.28 0.28 0.28 0.28 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 5.63 75.88 5.63 74.52 6.33 74.52 6.33 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 16.67 75.88 16.67 74.52 17.37 74.52 17.37 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 25.41 75.88 25.41 74.52 26.11 74.52 26.11 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.63 75.88 28.63 74.52 29.33 74.52 29.33 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.29 75.88 38.29 74.52 38.99 74.52 38.99 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 49.33 75.88 49.33 74.52 50.03 74.52 50.03 75.88 50.25 75.88 50.25 74.52 50.95 74.52 50.95 75.88 51.17 75.88 51.17 74.52 51.87 74.52 51.87 75.88 52.09 75.88 52.09 74.52 52.79 74.52 52.79 75.88 53.01 75.88 53.01 74.52 53.71 74.52 53.71 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 ; + RECT 35.75 74.3 36.01 74.62 ; + RECT 33.45 74.3 33.71 74.62 ; + RECT 43.11 1.54 43.37 1.86 ; + RECT 16.89 1.54 17.15 1.86 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 75.88 65.96 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 75.88 5.17 75.88 5.17 74.52 5.87 74.52 5.87 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 11.15 75.88 11.15 74.52 11.85 74.52 11.85 75.88 12.07 75.88 12.07 74.52 12.77 74.52 12.77 75.88 12.99 75.88 12.99 74.52 13.69 74.52 13.69 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 16.67 75.88 16.67 74.52 17.37 74.52 17.37 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 19.43 75.88 19.43 74.52 20.13 74.52 20.13 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 23.11 75.88 23.11 74.52 23.81 74.52 23.81 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 31.39 75.88 31.39 74.52 32.09 74.52 32.09 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 36.91 75.88 36.91 74.52 37.61 74.52 37.61 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 45.65 75.88 45.65 74.52 46.35 74.52 46.35 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.41 75.88 48.41 74.52 49.11 74.52 49.11 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 ; LAYER met4 ; - POLYGON 67.68 75.76 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 36.43 0.4 36.43 1.76 35.33 1.76 35.33 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 20.79 0.4 20.79 1.76 19.69 1.76 19.69 0.4 18.95 0.4 18.95 1.76 17.85 1.76 17.85 0.4 17.11 0.4 17.11 1.76 16.01 1.76 16.01 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 22.45 75.76 22.45 74.4 23.55 74.4 23.55 75.76 24.29 75.76 24.29 74.4 25.39 74.4 25.39 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; + POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 30.73 75.76 30.73 74.4 31.83 74.4 31.83 75.76 32.57 75.76 32.57 74.4 33.67 74.4 33.67 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; LAYER met1 ; - POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER met5 ; - POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; + POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER li1 ; - RECT 0.17 0.17 67.91 75.99 ; + RECT 0.17 0.17 66.07 75.99 ; LAYER mcon ; - RECT 67.765 76.075 67.935 76.245 ; - RECT 67.305 76.075 67.475 76.245 ; - RECT 66.845 76.075 67.015 76.245 ; - RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1534,118 +1524,114 @@ MACRO cby_2__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 67.765 73.355 67.935 73.525 ; - RECT 67.305 73.355 67.475 73.525 ; + RECT 65.925 73.355 66.095 73.525 ; + RECT 65.465 73.355 65.635 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 67.765 70.635 67.935 70.805 ; - RECT 67.305 70.635 67.475 70.805 ; + RECT 65.925 70.635 66.095 70.805 ; + RECT 65.465 70.635 65.635 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 67.765 67.915 67.935 68.085 ; - RECT 67.305 67.915 67.475 68.085 ; + RECT 65.925 67.915 66.095 68.085 ; + RECT 65.465 67.915 65.635 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; + RECT 65.925 65.195 66.095 65.365 ; + RECT 65.465 65.195 65.635 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 67.765 62.475 67.935 62.645 ; - RECT 67.305 62.475 67.475 62.645 ; + RECT 65.925 62.475 66.095 62.645 ; + RECT 65.465 62.475 65.635 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 67.765 59.755 67.935 59.925 ; - RECT 67.305 59.755 67.475 59.925 ; + RECT 65.925 59.755 66.095 59.925 ; + RECT 65.465 59.755 65.635 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 67.765 57.035 67.935 57.205 ; - RECT 67.305 57.035 67.475 57.205 ; + RECT 65.925 57.035 66.095 57.205 ; + RECT 65.465 57.035 65.635 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 67.765 54.315 67.935 54.485 ; - RECT 67.305 54.315 67.475 54.485 ; + RECT 65.925 54.315 66.095 54.485 ; + RECT 65.465 54.315 65.635 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 67.765 51.595 67.935 51.765 ; - RECT 67.305 51.595 67.475 51.765 ; + RECT 65.925 51.595 66.095 51.765 ; + RECT 65.465 51.595 65.635 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 67.765 48.875 67.935 49.045 ; - RECT 67.305 48.875 67.475 49.045 ; + RECT 65.925 48.875 66.095 49.045 ; + RECT 65.465 48.875 65.635 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 67.765 46.155 67.935 46.325 ; - RECT 67.305 46.155 67.475 46.325 ; + RECT 65.925 46.155 66.095 46.325 ; + RECT 65.465 46.155 65.635 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 67.765 43.435 67.935 43.605 ; - RECT 67.305 43.435 67.475 43.605 ; + RECT 65.925 43.435 66.095 43.605 ; + RECT 65.465 43.435 65.635 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 67.765 40.715 67.935 40.885 ; - RECT 67.305 40.715 67.475 40.885 ; + RECT 65.925 40.715 66.095 40.885 ; + RECT 65.465 40.715 65.635 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 67.765 37.995 67.935 38.165 ; - RECT 67.305 37.995 67.475 38.165 ; + RECT 65.925 37.995 66.095 38.165 ; + RECT 65.465 37.995 65.635 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 67.765 35.275 67.935 35.445 ; - RECT 67.305 35.275 67.475 35.445 ; + RECT 65.925 35.275 66.095 35.445 ; + RECT 65.465 35.275 65.635 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 67.765 32.555 67.935 32.725 ; - RECT 67.305 32.555 67.475 32.725 ; + RECT 65.925 32.555 66.095 32.725 ; + RECT 65.465 32.555 65.635 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 67.765 29.835 67.935 30.005 ; - RECT 67.305 29.835 67.475 30.005 ; + RECT 65.925 29.835 66.095 30.005 ; + RECT 65.465 29.835 65.635 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 67.765 27.115 67.935 27.285 ; - RECT 67.305 27.115 67.475 27.285 ; + RECT 65.925 27.115 66.095 27.285 ; + RECT 65.465 27.115 65.635 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 67.765 24.395 67.935 24.565 ; - RECT 67.305 24.395 67.475 24.565 ; + RECT 65.925 24.395 66.095 24.565 ; + RECT 65.465 24.395 65.635 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 67.765 21.675 67.935 21.845 ; - RECT 67.305 21.675 67.475 21.845 ; + RECT 65.925 21.675 66.095 21.845 ; + RECT 65.465 21.675 65.635 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 67.765 18.955 67.935 19.125 ; - RECT 67.305 18.955 67.475 19.125 ; + RECT 65.925 18.955 66.095 19.125 ; + RECT 65.465 18.955 65.635 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; + RECT 65.925 16.235 66.095 16.405 ; + RECT 65.465 16.235 65.635 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 67.765 13.515 67.935 13.685 ; - RECT 67.305 13.515 67.475 13.685 ; + RECT 65.925 13.515 66.095 13.685 ; + RECT 65.465 13.515 65.635 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1791,29 +1777,34 @@ MACRO cby_2__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 76.085 56.195 76.235 ; - RECT 26.605 76.085 26.755 76.235 ; - RECT 53.285 74.385 53.435 74.535 ; - RECT 38.565 74.385 38.715 74.535 ; - RECT 15.105 1.625 15.255 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 76.085 55.275 76.235 ; + RECT 25.685 76.085 25.835 76.235 ; + RECT 13.265 74.385 13.415 74.535 ; + RECT 11.425 74.385 11.575 74.535 ; + RECT 10.965 1.625 11.115 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 1.28 54.3 1.48 54.5 ; - RECT 1.28 48.86 1.48 49.06 ; - RECT 1.74 29.82 1.94 30.02 ; - RECT 1.28 7.38 1.48 7.58 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 1.28 65.18 1.48 65.38 ; + RECT 1.28 51.58 1.48 51.78 ; + RECT 1.74 32.54 1.94 32.74 ; + RECT 1.28 25.74 1.48 25.94 ; + RECT 64.76 14.86 64.96 15.06 ; + RECT 1.74 6.02 1.94 6.22 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 76.06 56.22 76.26 ; - RECT 26.58 76.06 26.78 76.26 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 76.06 55.3 76.26 ; + RECT 25.66 76.06 25.86 76.26 ; + RECT 64.3 18.94 64.5 19.14 ; + RECT 64.3 16.22 64.5 16.42 ; + RECT 1.74 12.82 1.94 13.02 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; + POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; END END cby_2__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef index 6c35862..088a988 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 97.92 ; + SIZE 92 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met3 ; - RECT 94.3 6.65 95.68 6.95 ; + LAYER met2 ; + RECT 73.53 85.68 73.67 87.04 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 96.56 41.47 97.92 ; + RECT 44.55 96.56 44.69 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 53.75 96.56 53.89 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; + RECT 57.89 96.56 58.03 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; + RECT 39.95 96.56 40.09 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; + RECT 27.53 96.56 27.67 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 96.56 18.47 97.92 ; + RECT 8.21 96.56 8.35 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 96.56 40.55 97.92 ; + RECT 28.45 96.56 28.59 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 96.56 39.63 97.92 ; + RECT 29.37 96.56 29.51 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 17.33 96.56 17.63 97.92 ; + RECT 36.65 96.56 36.95 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 54.13 96.56 54.43 97.92 ; + RECT 44.93 96.56 45.23 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; + RECT 50.07 96.56 50.21 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; + RECT 49.15 96.56 49.29 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 96.56 63.09 97.92 ; + RECT 56.97 96.56 57.11 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 96.56 13.87 97.92 ; + RECT 9.13 96.56 9.27 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.41 96.56 17.55 97.92 ; + RECT 30.29 96.56 30.43 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 96.56 34.11 97.92 ; + RECT 33.51 96.56 33.65 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 63.33 96.56 63.63 97.92 ; + RECT 56.89 96.56 57.19 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 33.89 96.56 34.19 97.92 ; + RECT 21.93 96.56 22.23 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 96.56 35.03 97.92 ; + RECT 52.83 96.56 52.97 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 96.56 51.59 97.92 ; + RECT 60.19 96.56 60.33 97.92 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -539,7 +539,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 76.69 95.68 76.99 ; + RECT 90.62 73.29 92 73.59 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -547,7 +547,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 25.69 95.68 25.99 ; + RECT 90.62 71.93 92 72.23 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -555,7 +555,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 13.45 95.68 13.75 ; + RECT 90.62 9.37 92 9.67 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -563,7 +563,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 39.29 95.68 39.59 ; + RECT 90.62 21.61 92 21.91 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -571,7 +571,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 37.93 95.68 38.23 ; + RECT 90.62 76.01 92 76.31 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -579,7 +579,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 40.65 95.68 40.95 ; + RECT 90.62 22.97 92 23.27 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -587,7 +587,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 27.05 95.68 27.35 ; + RECT 90.62 42.01 92 42.31 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -595,7 +595,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 52.89 95.68 53.19 ; + RECT 90.62 36.57 92 36.87 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -603,7 +603,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 75.33 95.68 75.63 ; + RECT 90.62 24.33 92 24.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -611,7 +611,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 46.09 95.68 46.39 ; + RECT 90.62 44.73 92 45.03 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -619,7 +619,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 44.73 95.68 45.03 ; + RECT 90.62 54.93 92 55.23 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -627,7 +627,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 21.61 95.68 21.91 ; + RECT 90.62 31.13 92 31.43 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -635,7 +635,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 10.73 95.68 11.03 ; + RECT 90.62 12.09 92 12.39 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -643,7 +643,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 70.57 95.68 70.87 ; + RECT 90.62 83.49 92 83.79 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -651,7 +651,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 61.73 95.68 62.03 ; + RECT 90.62 77.37 92 77.67 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -659,7 +659,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 71.93 95.68 72.23 ; + RECT 90.62 26.37 92 26.67 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -667,7 +667,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 22.97 95.68 23.27 ; + RECT 90.62 32.49 92 32.79 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -675,7 +675,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 9.37 95.68 9.67 ; + RECT 90.62 10.73 92 11.03 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -683,7 +683,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 31.13 95.68 31.43 ; + RECT 90.62 35.21 92 35.51 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -691,7 +691,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 28.41 95.68 28.71 ; + RECT 90.62 28.41 92 28.71 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_1_[0] @@ -699,7 +699,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 60.37 95.68 60.67 ; + RECT 90.62 74.65 92 74.95 ; END END right_bottom_grid_pin_1_[0] PIN right_bottom_grid_pin_3_[0] @@ -707,7 +707,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 56.97 95.68 57.27 ; + RECT 90.62 59.69 92 59.99 ; END END right_bottom_grid_pin_3_[0] PIN right_bottom_grid_pin_5_[0] @@ -715,7 +715,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 66.49 95.68 66.79 ; + RECT 90.62 66.49 92 66.79 ; END END right_bottom_grid_pin_5_[0] PIN right_bottom_grid_pin_7_[0] @@ -723,7 +723,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 43.37 95.68 43.67 ; + RECT 90.62 50.17 92 50.47 ; END END right_bottom_grid_pin_7_[0] PIN right_bottom_grid_pin_9_[0] @@ -731,7 +731,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 69.21 95.68 69.51 ; + RECT 90.62 61.73 92 62.03 ; END END right_bottom_grid_pin_9_[0] PIN right_bottom_grid_pin_11_[0] @@ -739,7 +739,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 55.61 95.68 55.91 ; + RECT 90.62 48.81 92 49.11 ; END END right_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -747,7 +747,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 12.09 95.68 12.39 ; + RECT 90.62 13.45 92 13.75 ; END END ccff_head[0] PIN chany_top_out[0] @@ -755,15 +755,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 96.56 14.79 97.92 ; + LAYER met4 ; + RECT 12.73 96.56 13.03 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -771,15 +771,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 96.56 16.63 97.92 ; + LAYER met4 ; + RECT 5.37 96.56 5.67 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -787,47 +787,47 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 96.56 64.47 97.92 ; + RECT 56.05 96.56 56.19 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.81 96.56 35.95 97.92 ; + LAYER met4 ; + RECT 46.77 96.56 47.07 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 38.57 96.56 38.71 97.92 ; + LAYER met4 ; + RECT 34.81 96.56 35.11 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.73 96.56 36.87 97.92 ; + LAYER met4 ; + RECT 23.77 96.56 24.07 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 15.57 96.56 15.71 97.92 ; + LAYER met4 ; + RECT 7.21 96.56 7.51 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 37.65 96.56 37.79 97.92 ; + LAYER met4 ; + RECT 32.97 96.56 33.27 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -835,7 +835,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -843,7 +843,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 61.49 96.56 61.79 97.92 ; + RECT 48.61 96.56 48.91 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -851,7 +851,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 96.56 58.49 97.92 ; + RECT 50.99 96.56 51.13 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -859,7 +859,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 39.41 96.56 39.71 97.92 ; + RECT 31.13 96.56 31.43 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -867,7 +867,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 15.49 96.56 15.79 97.92 ; + RECT 9.05 96.56 9.35 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -875,7 +875,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 35.73 96.56 36.03 97.92 ; + RECT 27.45 96.56 27.75 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -883,7 +883,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 51.91 96.56 52.05 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -891,7 +891,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 59.65 96.56 59.95 97.92 ; + RECT 52.29 96.56 52.59 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -899,7 +899,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 57.81 96.56 58.11 97.92 ; + RECT 50.45 96.56 50.75 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -907,7 +907,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 37.57 96.56 37.87 97.92 ; + RECT 29.29 96.56 29.59 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -915,7 +915,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 81.45 95.68 81.75 ; + RECT 90.62 56.97 92 57.27 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -923,7 +923,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 65.13 95.68 65.43 ; + RECT 90.62 67.85 92 68.15 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -931,7 +931,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 80.09 95.68 80.39 ; + RECT 90.62 43.37 92 43.67 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -939,7 +939,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 58.33 95.68 58.63 ; + RECT 90.62 80.09 92 80.39 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -947,7 +947,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 24.33 95.68 24.63 ; + RECT 90.62 33.85 92 34.15 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -955,7 +955,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 63.77 95.68 64.07 ; + RECT 90.62 82.13 92 82.43 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -963,7 +963,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 78.73 95.68 79.03 ; + RECT 90.62 39.29 92 39.59 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -971,7 +971,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 42.01 95.68 42.31 ; + RECT 90.62 53.57 92 53.87 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -979,7 +979,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 54.25 95.68 54.55 ; + RECT 90.62 47.45 92 47.75 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -987,7 +987,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 73.97 95.68 74.27 ; + RECT 90.62 78.73 92 79.03 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -995,7 +995,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 47.45 95.68 47.75 ; + RECT 90.62 46.09 92 46.39 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1003,7 +1003,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 82.81 95.68 83.11 ; + RECT 90.62 69.21 92 69.51 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1011,7 +1011,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 32.49 95.68 32.79 ; + RECT 90.62 40.65 92 40.95 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1019,7 +1019,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 35.21 95.68 35.51 ; + RECT 90.62 37.93 92 38.23 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1027,7 +1027,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 33.85 95.68 34.15 ; + RECT 90.62 29.77 92 30.07 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1035,7 +1035,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 51.53 95.68 51.83 ; + RECT 90.62 52.21 92 52.51 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1043,7 +1043,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 48.81 95.68 49.11 ; + RECT 90.62 58.33 92 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1051,7 +1051,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 50.17 95.68 50.47 ; + RECT 90.62 63.09 92 63.39 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1059,7 +1059,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 67.85 95.68 68.15 ; + RECT 90.62 70.57 92 70.87 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1067,7 +1067,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 29.77 95.68 30.07 ; + RECT 90.62 65.13 92 65.43 ; END END chanx_right_out[19] PIN ccff_tail[0] @@ -1075,7 +1075,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END ccff_tail[0] PIN VDD @@ -1084,53 +1084,53 @@ MACRO sb_0__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; + RECT 91.52 2.48 92 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; + RECT 91.52 84.08 92 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 67.6 89.52 68.08 90 ; + RECT 65.76 89.52 66.24 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 67.6 94.96 68.08 95.44 ; + RECT 65.76 94.96 66.24 95.44 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 85.26 0 85.86 0.6 ; - RECT 85.26 86.44 85.86 87.04 ; - RECT 11.66 97.32 12.26 97.92 ; - RECT 41.1 97.32 41.7 97.92 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 80.66 86.44 81.26 87.04 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 40.18 97.32 40.78 97.92 ; LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 92.48 11.32 95.68 14.52 ; + RECT 88.8 11.32 92 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 92.48 52.12 95.68 55.32 ; + RECT 88.8 52.12 92 55.32 ; END END VDD PIN VSS @@ -1138,159 +1138,151 @@ MACRO sb_0__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 95.68 0.24 ; + RECT 0 0 92 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; + RECT 91.52 5.2 92 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 95.2 10.64 95.68 11.12 ; + RECT 91.52 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; - RECT 0 86.8 95.68 87.28 ; + RECT 91.52 81.36 92 81.84 ; + RECT 0 86.8 92 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 67.6 92.24 68.08 92.72 ; - RECT 0 97.68 68.08 97.92 ; + RECT 65.76 92.24 66.24 92.72 ; + RECT 0 97.68 66.24 97.92 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 97.32 26.98 97.92 ; - RECT 55.82 97.32 56.42 97.92 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 97.32 26.06 97.92 ; + RECT 54.9 97.32 55.5 97.92 ; LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 92.48 31.72 95.68 34.92 ; + RECT 88.8 31.72 92 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 92.48 72.52 95.68 75.72 ; + RECT 88.8 72.52 92 75.72 ; END END VSS OBS LAYER li1 ; - RECT 0 97.835 68.08 98.005 ; - RECT 67.16 95.115 68.08 95.285 ; + RECT 0 97.835 66.24 98.005 ; + RECT 65.32 95.115 66.24 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 67.16 92.395 68.08 92.565 ; + RECT 65.32 92.395 66.24 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 67.16 89.675 68.08 89.845 ; + RECT 65.32 89.675 66.24 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 65.32 86.955 95.68 87.125 ; + RECT 62.56 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 95.22 84.235 95.68 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 95.22 81.515 95.68 81.685 ; + RECT 91.08 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 94.76 78.795 95.68 78.965 ; + RECT 91.08 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 94.76 76.075 95.68 76.245 ; + RECT 91.54 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 94.76 73.355 95.68 73.525 ; + RECT 91.54 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 94.76 70.635 95.68 70.805 ; + RECT 91.08 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 94.76 67.915 95.68 68.085 ; + RECT 91.08 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 94.76 65.195 95.68 65.365 ; + RECT 91.08 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 94.76 62.475 95.68 62.645 ; + RECT 91.08 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 94.76 59.755 95.68 59.925 ; + RECT 91.08 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 94.76 57.035 95.68 57.205 ; + RECT 91.08 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 94.76 54.315 95.68 54.485 ; + RECT 91.08 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 94.76 51.595 95.68 51.765 ; + RECT 91.08 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 94.76 48.875 95.68 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 94.76 46.155 95.68 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 94.76 43.435 95.68 43.605 ; + RECT 91.08 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 94.76 40.715 95.68 40.885 ; + RECT 91.08 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 94.76 37.995 95.68 38.165 ; + RECT 91.08 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 93.84 35.275 95.68 35.445 ; + RECT 91.08 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 93.84 32.555 95.68 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 94.76 29.835 95.68 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 94.76 27.115 95.68 27.285 ; + RECT 91.54 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 95.22 24.395 95.68 24.565 ; + RECT 91.54 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 95.22 21.675 95.68 21.845 ; + RECT 91.54 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 95.22 18.955 95.68 19.125 ; + RECT 91.54 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 94.76 16.235 95.68 16.405 ; + RECT 91.54 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 92 13.515 95.68 13.685 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 92 10.795 95.68 10.965 ; + RECT 91.54 10.795 92 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 95.22 8.075 95.68 8.245 ; + RECT 91.54 8.075 92 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 95.22 5.355 95.68 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 95.68 0.085 ; - LAYER met3 ; - POLYGON 56.285 98.085 56.285 98.08 56.5 98.08 56.5 97.76 56.285 97.76 56.285 97.755 55.955 97.755 55.955 97.76 55.74 97.76 55.74 98.08 55.955 98.08 55.955 98.085 ; - POLYGON 26.845 98.085 26.845 98.08 27.06 98.08 27.06 97.76 26.845 97.76 26.845 97.755 26.515 97.755 26.515 97.76 26.3 97.76 26.3 98.08 26.515 98.08 26.515 98.085 ; - POLYGON 94.45 67.47 94.45 67.19 93.9 67.19 93.9 67.17 79.89 67.17 79.89 67.47 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 97.52 67.68 86.64 95.28 86.64 95.28 83.51 93.9 83.51 93.9 82.41 95.28 82.41 95.28 82.15 93.9 82.15 93.9 81.05 95.28 81.05 95.28 80.79 93.9 80.79 93.9 79.69 95.28 79.69 95.28 79.43 93.9 79.43 93.9 78.33 95.28 78.33 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 72.63 93.9 72.63 93.9 71.53 95.28 71.53 95.28 71.27 93.9 71.27 93.9 70.17 95.28 70.17 95.28 69.91 93.9 69.91 93.9 68.81 95.28 68.81 95.28 68.55 93.9 68.55 93.9 67.45 95.28 67.45 95.28 67.19 93.9 67.19 93.9 66.09 95.28 66.09 95.28 65.83 93.9 65.83 93.9 64.73 95.28 64.73 95.28 64.47 93.9 64.47 93.9 63.37 95.28 63.37 95.28 62.43 93.9 62.43 93.9 61.33 95.28 61.33 95.28 61.07 93.9 61.07 93.9 59.97 95.28 59.97 95.28 59.03 93.9 59.03 93.9 57.93 95.28 57.93 95.28 57.67 93.9 57.67 93.9 56.57 95.28 56.57 95.28 56.31 93.9 56.31 93.9 55.21 95.28 55.21 95.28 54.95 93.9 54.95 93.9 53.85 95.28 53.85 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 52.23 93.9 52.23 93.9 51.13 95.28 51.13 95.28 50.87 93.9 50.87 93.9 49.77 95.28 49.77 95.28 49.51 93.9 49.51 93.9 48.41 95.28 48.41 95.28 48.15 93.9 48.15 93.9 47.05 95.28 47.05 95.28 46.79 93.9 46.79 93.9 45.69 95.28 45.69 95.28 45.43 93.9 45.43 93.9 44.33 95.28 44.33 95.28 44.07 93.9 44.07 93.9 42.97 95.28 42.97 95.28 42.71 93.9 42.71 93.9 41.61 95.28 41.61 95.28 41.35 93.9 41.35 93.9 40.25 95.28 40.25 95.28 39.99 93.9 39.99 93.9 38.89 95.28 38.89 95.28 38.63 93.9 38.63 93.9 37.53 95.28 37.53 95.28 35.91 93.9 35.91 93.9 34.81 95.28 34.81 95.28 34.55 93.9 34.55 93.9 33.45 95.28 33.45 95.28 33.19 93.9 33.19 93.9 32.09 95.28 32.09 95.28 31.83 93.9 31.83 93.9 30.73 95.28 30.73 95.28 30.47 93.9 30.47 93.9 29.37 95.28 29.37 95.28 29.11 93.9 29.11 93.9 28.01 95.28 28.01 95.28 27.75 93.9 27.75 93.9 26.65 95.28 26.65 95.28 26.39 93.9 26.39 93.9 25.29 95.28 25.29 95.28 25.03 93.9 25.03 93.9 23.93 95.28 23.93 95.28 23.67 93.9 23.67 93.9 22.57 95.28 22.57 95.28 22.31 93.9 22.31 93.9 21.21 95.28 21.21 95.28 14.15 93.9 14.15 93.9 13.05 95.28 13.05 95.28 12.79 93.9 12.79 93.9 11.69 95.28 11.69 95.28 11.43 93.9 11.43 93.9 10.33 95.28 10.33 95.28 10.07 93.9 10.07 93.9 8.97 95.28 8.97 95.28 7.35 93.9 7.35 93.9 6.25 95.28 6.25 95.28 0.4 0.4 0.4 0.4 97.52 ; + RECT 0 -0.085 92 0.085 ; LAYER met2 ; - RECT 55.98 97.735 56.26 98.105 ; - RECT 26.54 97.735 26.82 98.105 ; - RECT 66.11 96.06 66.37 96.38 ; - RECT 56.91 96.06 57.17 96.38 ; - RECT 52.77 96.06 53.03 96.38 ; - RECT 39.89 96.06 40.15 96.38 ; - RECT 18.73 96.06 18.99 96.38 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 97.64 67.8 86.76 95.4 86.76 95.4 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 0.28 0.28 0.28 97.64 13.45 97.64 13.45 96.28 14.15 96.28 14.15 97.64 14.37 97.64 14.37 96.28 15.07 96.28 15.07 97.64 15.29 97.64 15.29 96.28 15.99 96.28 15.99 97.64 16.21 97.64 16.21 96.28 16.91 96.28 16.91 97.64 17.13 97.64 17.13 96.28 17.83 96.28 17.83 97.64 18.05 97.64 18.05 96.28 18.75 96.28 18.75 97.64 33.69 97.64 33.69 96.28 34.39 96.28 34.39 97.64 34.61 97.64 34.61 96.28 35.31 96.28 35.31 97.64 35.53 97.64 35.53 96.28 36.23 96.28 36.23 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 ; + RECT 55.06 97.735 55.34 98.105 ; + RECT 25.62 97.735 25.9 98.105 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 97.64 65.96 86.76 73.25 86.76 73.25 85.4 73.95 85.4 73.95 86.76 91.72 86.76 91.72 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 0.28 0.28 0.28 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 30.01 97.64 30.01 96.28 30.71 96.28 30.71 97.64 33.23 97.64 33.23 96.28 33.93 96.28 33.93 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 52.55 97.64 52.55 96.28 53.25 96.28 53.25 97.64 53.47 97.64 53.47 96.28 54.17 96.28 54.17 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 ; LAYER met4 ; - POLYGON 67.68 97.52 67.68 86.64 84.86 86.64 84.86 86.04 86.26 86.04 86.26 86.64 95.28 86.64 95.28 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 97.52 11.26 97.52 11.26 96.92 12.66 96.92 12.66 97.52 15.09 97.52 15.09 96.16 16.19 96.16 16.19 97.52 16.93 97.52 16.93 96.16 18.03 96.16 18.03 97.52 25.98 97.52 25.98 96.92 27.38 96.92 27.38 97.52 33.49 97.52 33.49 96.16 34.59 96.16 34.59 97.52 35.33 97.52 35.33 96.16 36.43 96.16 36.43 97.52 37.17 97.52 37.17 96.16 38.27 96.16 38.27 97.52 39.01 97.52 39.01 96.16 40.11 96.16 40.11 97.52 40.7 97.52 40.7 96.92 42.1 96.92 42.1 97.52 53.73 97.52 53.73 96.16 54.83 96.16 54.83 97.52 55.42 97.52 55.42 96.92 56.82 96.92 56.82 97.52 57.41 97.52 57.41 96.16 58.51 96.16 58.51 97.52 59.25 97.52 59.25 96.16 60.35 96.16 60.35 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 ; + POLYGON 65.84 97.52 65.84 86.64 80.26 86.64 80.26 86.04 81.66 86.04 81.66 86.64 91.6 86.64 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 97.52 4.97 97.52 4.97 96.16 6.07 96.16 6.07 97.52 6.81 97.52 6.81 96.16 7.91 96.16 7.91 97.52 8.65 97.52 8.65 96.16 9.75 96.16 9.75 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 12.33 97.52 12.33 96.16 13.43 96.16 13.43 97.52 21.53 97.52 21.53 96.16 22.63 96.16 22.63 97.52 23.37 97.52 23.37 96.16 24.47 96.16 24.47 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 27.05 97.52 27.05 96.16 28.15 96.16 28.15 97.52 28.89 97.52 28.89 96.16 29.99 96.16 29.99 97.52 30.73 97.52 30.73 96.16 31.83 96.16 31.83 97.52 32.57 97.52 32.57 96.16 33.67 96.16 33.67 97.52 34.41 97.52 34.41 96.16 35.51 96.16 35.51 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 44.53 97.52 44.53 96.16 45.63 96.16 45.63 97.52 46.37 97.52 46.37 96.16 47.47 96.16 47.47 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 50.05 97.52 50.05 96.16 51.15 96.16 51.15 97.52 51.89 97.52 51.89 96.16 52.99 96.16 52.99 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 ; + LAYER met3 ; + POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; + POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; + POLYGON 90.785 56.605 90.785 56.275 90.455 56.275 90.455 56.29 76.67 56.29 76.67 56.59 90.455 56.59 90.455 56.605 ; + POLYGON 90.77 30.75 90.77 30.47 90.22 30.47 90.22 30.45 72.53 30.45 72.53 30.75 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 97.52 65.84 86.64 91.6 86.64 91.6 84.19 90.22 84.19 90.22 83.09 91.6 83.09 91.6 82.83 90.22 82.83 90.22 81.73 91.6 81.73 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.71 90.22 76.71 90.22 75.61 91.6 75.61 91.6 75.35 90.22 75.35 90.22 74.25 91.6 74.25 91.6 73.99 90.22 73.99 90.22 72.89 91.6 72.89 91.6 72.63 90.22 72.63 90.22 71.53 91.6 71.53 91.6 71.27 90.22 71.27 90.22 70.17 91.6 70.17 91.6 69.91 90.22 69.91 90.22 68.81 91.6 68.81 91.6 68.55 90.22 68.55 90.22 67.45 91.6 67.45 91.6 67.19 90.22 67.19 90.22 66.09 91.6 66.09 91.6 65.83 90.22 65.83 90.22 64.73 91.6 64.73 91.6 63.79 90.22 63.79 90.22 62.69 91.6 62.69 91.6 62.43 90.22 62.43 90.22 61.33 91.6 61.33 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 55.63 90.22 55.63 90.22 54.53 91.6 54.53 91.6 54.27 90.22 54.27 90.22 53.17 91.6 53.17 91.6 52.91 90.22 52.91 90.22 51.81 91.6 51.81 91.6 50.87 90.22 50.87 90.22 49.77 91.6 49.77 91.6 49.51 90.22 49.51 90.22 48.41 91.6 48.41 91.6 48.15 90.22 48.15 90.22 47.05 91.6 47.05 91.6 46.79 90.22 46.79 90.22 45.69 91.6 45.69 91.6 45.43 90.22 45.43 90.22 44.33 91.6 44.33 91.6 44.07 90.22 44.07 90.22 42.97 91.6 42.97 91.6 42.71 90.22 42.71 90.22 41.61 91.6 41.61 91.6 41.35 90.22 41.35 90.22 40.25 91.6 40.25 91.6 39.99 90.22 39.99 90.22 38.89 91.6 38.89 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 33.19 90.22 33.19 90.22 32.09 91.6 32.09 91.6 31.83 90.22 31.83 90.22 30.73 91.6 30.73 91.6 30.47 90.22 30.47 90.22 29.37 91.6 29.37 91.6 29.11 90.22 29.11 90.22 28.01 91.6 28.01 91.6 27.07 90.22 27.07 90.22 25.97 91.6 25.97 91.6 25.03 90.22 25.03 90.22 23.93 91.6 23.93 91.6 23.67 90.22 23.67 90.22 22.57 91.6 22.57 91.6 22.31 90.22 22.31 90.22 21.21 91.6 21.21 91.6 14.15 90.22 14.15 90.22 13.05 91.6 13.05 91.6 12.79 90.22 12.79 90.22 11.69 91.6 11.69 91.6 11.43 90.22 11.43 90.22 10.33 91.6 10.33 91.6 10.07 90.22 10.07 90.22 8.97 91.6 8.97 91.6 0.4 0.4 0.4 0.4 97.52 ; LAYER met5 ; - POLYGON 66.48 96.32 66.48 85.44 94.08 85.44 94.08 77.32 90.88 77.32 90.88 70.92 94.08 70.92 94.08 56.92 90.88 56.92 90.88 50.52 94.08 50.52 94.08 36.52 90.88 36.52 90.88 30.12 94.08 30.12 94.08 16.12 90.88 16.12 90.88 9.72 94.08 9.72 94.08 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 96.32 ; + POLYGON 64.64 96.32 64.64 85.44 90.4 85.44 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 96.32 ; LAYER met1 ; - POLYGON 67.8 97.4 67.8 95.72 67.32 95.72 67.32 94.68 67.8 94.68 67.8 93 67.32 93 67.32 91.96 67.8 91.96 67.8 90.28 67.32 90.28 67.32 89.24 67.8 89.24 67.8 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 94.92 11.4 94.92 10.36 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 65.96 97.4 65.96 95.72 65.48 95.72 65.48 94.68 65.96 94.68 65.96 93 65.48 93 65.48 91.96 65.96 91.96 65.96 90.28 65.48 90.28 65.48 89.24 65.96 89.24 65.96 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 67.91 97.75 67.91 86.87 95.51 86.87 95.51 0.17 0.17 0.17 0.17 97.75 ; + POLYGON 66.07 97.75 66.07 86.87 91.83 86.87 91.83 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; RECT 65.925 97.835 66.095 98.005 ; RECT 65.465 97.835 65.635 98.005 ; RECT 65.005 97.835 65.175 98.005 ; @@ -1435,26 +1427,18 @@ MACRO sb_0__0_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 67.765 95.115 67.935 95.285 ; - RECT 67.305 95.115 67.475 95.285 ; + RECT 65.925 95.115 66.095 95.285 ; + RECT 65.465 95.115 65.635 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 67.765 92.395 67.935 92.565 ; - RECT 67.305 92.395 67.475 92.565 ; + RECT 65.925 92.395 66.095 92.565 ; + RECT 65.465 92.395 65.635 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 67.765 89.675 67.935 89.845 ; - RECT 67.305 89.675 67.475 89.845 ; + RECT 65.925 89.675 66.095 89.845 ; + RECT 65.465 89.675 65.635 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; - RECT 94.445 86.955 94.615 87.125 ; - RECT 93.985 86.955 94.155 87.125 ; - RECT 93.525 86.955 93.695 87.125 ; - RECT 93.065 86.955 93.235 87.125 ; - RECT 92.605 86.955 92.775 87.125 ; - RECT 92.145 86.955 92.315 87.125 ; RECT 91.685 86.955 91.855 87.125 ; RECT 91.225 86.955 91.395 87.125 ; RECT 90.765 86.955 90.935 87.125 ; @@ -1655,138 +1639,130 @@ MACRO sb_0__0_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -1988,31 +1964,31 @@ MACRO sb_0__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 97.845 56.195 97.995 ; - RECT 26.605 97.845 26.755 97.995 ; - RECT 55.125 96.145 55.275 96.295 ; - RECT 44.545 96.145 44.695 96.295 ; - RECT 36.725 96.145 36.875 96.295 ; - RECT 56.045 86.965 56.195 87.115 ; - RECT 26.605 86.965 26.755 87.115 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 97.845 55.275 97.995 ; + RECT 25.685 97.845 25.835 97.995 ; + RECT 46.385 96.145 46.535 96.295 ; + RECT 29.365 96.145 29.515 96.295 ; + RECT 55.125 86.965 55.275 87.115 ; + RECT 25.685 86.965 25.835 87.115 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 97.82 56.22 98.02 ; - RECT 26.58 97.82 26.78 98.02 ; - RECT 93.74 61.78 93.94 61.98 ; - RECT 93.74 47.5 93.94 47.7 ; - RECT 94.2 25.74 94.4 25.94 ; - RECT 94.2 12.14 94.4 12.34 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 97.82 55.3 98.02 ; + RECT 25.66 97.82 25.86 98.02 ; + RECT 90.52 78.78 90.72 78.98 ; + RECT 90.52 70.62 90.72 70.82 ; + RECT 90.52 61.78 90.72 61.98 ; + RECT 90.52 52.26 90.72 52.46 ; + RECT 90.52 46.14 90.72 46.34 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 97.82 56.22 98.02 ; - RECT 26.58 97.82 26.78 98.02 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 97.82 55.3 98.02 ; + RECT 25.66 97.82 25.86 98.02 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 97.92 68.08 97.92 68.08 87.04 95.68 87.04 95.68 0 ; + POLYGON 0 0 0 97.92 66.24 97.92 66.24 87.04 92 87.04 92 0 ; END END sb_0__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef index 9bf316b..c20b096 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 108.8 ; + SIZE 92 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 83.65 10.88 83.79 12.24 ; + RECT 78.59 10.88 78.73 12.24 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 107.44 41.47 108.8 ; + RECT 44.55 107.44 44.69 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 107.44 61.25 108.8 ; + RECT 53.75 107.44 53.89 108.8 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 107.44 52.51 108.8 ; + RECT 57.89 107.44 58.03 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 107.44 60.33 108.8 ; + RECT 46.39 107.44 46.53 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 107.44 44.69 108.8 ; + RECT 39.95 107.44 40.09 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 107.44 62.17 108.8 ; + RECT 27.53 107.44 27.67 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 107.44 18.47 108.8 ; + RECT 8.21 107.44 8.35 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 107.44 40.55 108.8 ; + RECT 28.45 107.44 28.59 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 107.44 39.63 108.8 ; + RECT 29.37 107.44 29.51 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 17.33 107.44 17.63 108.8 ; + RECT 36.65 107.44 36.95 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 54.13 107.44 54.43 108.8 ; + RECT 44.93 107.44 45.23 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 107.44 57.57 108.8 ; + RECT 50.07 107.44 50.21 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 107.44 54.35 108.8 ; + RECT 49.15 107.44 49.29 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 107.44 63.09 108.8 ; + RECT 56.97 107.44 57.11 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 107.44 13.87 108.8 ; + RECT 9.13 107.44 9.27 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.41 107.44 17.55 108.8 ; + RECT 30.29 107.44 30.43 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 107.44 34.11 108.8 ; + RECT 33.51 107.44 33.65 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 63.33 107.44 63.63 108.8 ; + RECT 56.89 107.44 57.19 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 33.89 107.44 34.19 108.8 ; + RECT 21.93 107.44 22.23 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 107.44 35.03 108.8 ; + RECT 52.83 107.44 52.97 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 107.44 51.59 108.8 ; + RECT 60.19 107.44 60.33 108.8 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -539,7 +539,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 37.25 95.68 37.55 ; + RECT 90.62 66.49 92 66.79 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -547,7 +547,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 71.25 95.68 71.55 ; + RECT 90.62 82.81 92 83.11 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -555,7 +555,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 92.33 95.68 92.63 ; + RECT 90.62 92.33 92 92.63 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -563,7 +563,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 84.85 95.68 85.15 ; + RECT 90.62 36.57 92 36.87 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -571,7 +571,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 73.97 95.68 74.27 ; + RECT 90.62 74.65 92 74.95 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -579,7 +579,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 76.69 95.68 76.99 ; + RECT 90.62 77.37 92 77.67 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -587,7 +587,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 67.17 95.68 67.47 ; + RECT 90.62 33.85 92 34.15 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -595,7 +595,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 39.97 95.68 40.27 ; + RECT 90.62 46.09 92 46.39 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -603,7 +603,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 55.61 95.68 55.91 ; + RECT 90.62 56.97 92 57.27 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -611,7 +611,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 75.33 95.68 75.63 ; + RECT 90.62 73.29 92 73.59 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -619,7 +619,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 59.69 95.68 59.99 ; + RECT 90.62 84.17 92 84.47 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -627,7 +627,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 72.61 95.68 72.91 ; + RECT 90.62 90.97 92 91.27 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -635,7 +635,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 78.05 95.68 78.35 ; + RECT 90.62 81.45 92 81.75 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -643,7 +643,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 35.89 95.68 36.19 ; + RECT 90.62 44.73 92 45.03 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -651,7 +651,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 31.81 95.68 32.11 ; + RECT 90.62 31.81 92 32.11 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -659,7 +659,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 41.33 95.68 41.63 ; + RECT 90.62 61.73 92 62.03 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -667,7 +667,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 89.61 95.68 89.91 ; + RECT 90.62 65.13 92 65.43 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -675,7 +675,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 44.05 95.68 44.35 ; + RECT 90.62 48.81 92 49.11 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -683,7 +683,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 80.77 95.68 81.07 ; + RECT 90.62 69.21 92 69.51 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -691,7 +691,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 38.61 95.68 38.91 ; + RECT 90.62 89.61 92 89.91 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_34_[0] @@ -699,7 +699,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.33 10.88 87.47 12.24 ; + RECT 83.65 10.88 83.79 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -707,7 +707,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 88.25 10.88 88.39 12.24 ; + RECT 85.95 10.88 86.09 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] @@ -715,7 +715,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.27 10.88 82.41 12.24 ; + RECT 88.25 10.88 88.39 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -723,7 +723,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.03 10.88 85.17 12.24 ; + RECT 82.73 10.88 82.87 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -731,7 +731,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 91.01 10.88 91.15 12.24 ; + RECT 85.03 10.88 85.17 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -739,7 +739,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 89.17 10.88 89.31 12.24 ; + RECT 87.33 10.88 87.47 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -747,7 +747,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 90.09 10.88 90.23 12.24 ; + RECT 75.83 10.88 75.97 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -755,7 +755,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 86.41 10.88 86.55 12.24 ; + RECT 80.43 10.88 80.57 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -763,7 +763,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -771,7 +771,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -779,7 +779,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -787,7 +787,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -795,7 +795,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -803,7 +803,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -811,7 +811,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -819,7 +819,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -827,7 +827,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -835,7 +835,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 0 18.47 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -843,7 +843,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -851,7 +851,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -867,7 +867,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -875,7 +875,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -883,7 +883,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 0 13.87 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -891,7 +891,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -899,7 +899,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 8.21 0 8.35 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -907,7 +907,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -915,7 +915,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -923,7 +923,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] @@ -931,7 +931,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 86.89 95.68 87.19 ; + RECT 90.62 43.37 92 43.67 ; END END ccff_head[0] PIN chany_top_out[0] @@ -939,15 +939,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 107.44 53.43 108.8 ; + RECT 45.47 107.44 45.61 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 107.44 14.79 108.8 ; + LAYER met4 ; + RECT 12.73 107.44 13.03 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -955,15 +955,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 107.44 65.85 108.8 ; + RECT 47.31 107.44 47.45 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 107.44 16.63 108.8 ; + LAYER met4 ; + RECT 5.37 107.44 5.67 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -971,47 +971,47 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 107.44 64.47 108.8 ; + RECT 56.05 107.44 56.19 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.81 107.44 35.95 108.8 ; + LAYER met4 ; + RECT 46.77 107.44 47.07 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 38.57 107.44 38.71 108.8 ; + LAYER met4 ; + RECT 34.81 107.44 35.11 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.73 107.44 36.87 108.8 ; + LAYER met4 ; + RECT 23.77 107.44 24.07 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 15.57 107.44 15.71 108.8 ; + LAYER met4 ; + RECT 7.21 107.44 7.51 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 37.65 107.44 37.79 108.8 ; + LAYER met4 ; + RECT 32.97 107.44 33.27 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1019,7 +1019,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 107.44 55.27 108.8 ; + RECT 48.23 107.44 48.37 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1027,7 +1027,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 61.49 107.44 61.79 108.8 ; + RECT 48.61 107.44 48.91 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1035,7 +1035,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 107.44 58.49 108.8 ; + RECT 50.99 107.44 51.13 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1043,7 +1043,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 39.41 107.44 39.71 108.8 ; + RECT 31.13 107.44 31.43 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1051,7 +1051,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 15.49 107.44 15.79 108.8 ; + RECT 9.05 107.44 9.35 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1059,7 +1059,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 35.73 107.44 36.03 108.8 ; + RECT 27.45 107.44 27.75 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1067,7 +1067,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 107.44 59.41 108.8 ; + RECT 51.91 107.44 52.05 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1075,7 +1075,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 59.65 107.44 59.95 108.8 ; + RECT 52.29 107.44 52.59 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1083,7 +1083,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 57.81 107.44 58.11 108.8 ; + RECT 50.45 107.44 50.75 108.8 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1091,7 +1091,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 37.57 107.44 37.87 108.8 ; + RECT 29.29 107.44 29.59 108.8 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1099,7 +1099,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 83.49 95.68 83.79 ; + RECT 90.62 70.57 92 70.87 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1107,7 +1107,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 90.97 95.68 91.27 ; + RECT 90.62 55.61 92 55.91 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1115,7 +1115,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 48.13 95.68 48.43 ; + RECT 90.62 71.93 92 72.23 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1123,7 +1123,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 61.05 95.68 61.35 ; + RECT 90.62 54.25 92 54.55 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1131,7 +1131,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 82.13 95.68 82.43 ; + RECT 90.62 37.93 92 38.23 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1139,7 +1139,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 79.41 95.68 79.71 ; + RECT 90.62 80.09 92 80.39 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1147,7 +1147,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 54.25 95.68 54.55 ; + RECT 90.62 50.17 92 50.47 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1155,7 +1155,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 64.45 95.68 64.75 ; + RECT 90.62 63.77 92 64.07 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1163,7 +1163,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 56.97 95.68 57.27 ; + RECT 90.62 42.01 92 42.31 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1171,7 +1171,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 50.85 95.68 51.15 ; + RECT 90.62 51.53 92 51.83 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1179,7 +1179,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 49.49 95.68 49.79 ; + RECT 90.62 52.89 92 53.19 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1187,7 +1187,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 65.81 95.68 66.11 ; + RECT 90.62 39.29 92 39.59 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1195,7 +1195,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 45.41 95.68 45.71 ; + RECT 90.62 78.73 92 79.03 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1203,7 +1203,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 88.25 95.68 88.55 ; + RECT 90.62 67.85 92 68.15 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1211,7 +1211,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 46.77 95.68 47.07 ; + RECT 90.62 35.21 92 35.51 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1219,7 +1219,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 42.69 95.68 42.99 ; + RECT 90.62 40.65 92 40.95 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1227,7 +1227,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 58.33 95.68 58.63 ; + RECT 90.62 58.33 92 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1235,7 +1235,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 52.89 95.68 53.19 ; + RECT 90.62 47.45 92 47.75 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1243,7 +1243,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 62.41 95.68 62.71 ; + RECT 90.62 59.69 92 59.99 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1251,7 +1251,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 69.21 95.68 69.51 ; + RECT 90.62 76.01 92 76.31 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1259,7 +1259,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1267,7 +1267,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1275,15 +1275,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; + LAYER met4 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1291,31 +1291,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 17.41 0 17.55 1.36 ; + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + LAYER met4 ; + RECT 27.45 0 27.75 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + LAYER met4 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1323,15 +1323,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; + LAYER met4 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1339,15 +1339,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; + LAYER met4 ; + RECT 29.29 0 29.59 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1355,31 +1355,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 0 16.63 1.36 ; + LAYER met4 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + LAYER met4 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1387,7 +1387,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1395,7 +1395,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1403,7 +1403,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.57 0 15.71 1.36 ; + RECT 9.13 0 9.27 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1411,7 +1411,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1419,7 +1419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END ccff_tail[0] PIN VDD @@ -1428,57 +1428,57 @@ MACRO sb_0__1_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; + RECT 91.52 84.08 92 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 95.2 89.52 95.68 90 ; + RECT 91.52 89.52 92 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; + RECT 91.52 94.96 92 95.44 ; RECT 0 100.4 0.48 100.88 ; - RECT 67.6 100.4 68.08 100.88 ; + RECT 65.76 100.4 66.24 100.88 ; RECT 0 105.84 0.48 106.32 ; - RECT 67.6 105.84 68.08 106.32 ; + RECT 65.76 105.84 66.24 106.32 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 85.26 10.88 85.86 11.48 ; - RECT 85.26 97.32 85.86 97.92 ; - RECT 11.66 108.2 12.26 108.8 ; - RECT 41.1 108.2 41.7 108.8 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 80.66 10.88 81.26 11.48 ; + RECT 80.66 97.32 81.26 97.92 ; + RECT 10.74 108.2 11.34 108.8 ; + RECT 40.18 108.2 40.78 108.8 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 92.48 22.2 95.68 25.4 ; + RECT 88.8 22.2 92 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 92.48 63 95.68 66.2 ; + RECT 88.8 63 92 66.2 ; END END VDD PIN VSS @@ -1486,54 +1486,54 @@ MACRO sb_0__1_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; - RECT 0 10.64 95.68 11.12 ; + RECT 65.76 5.2 66.24 5.68 ; + RECT 0 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; + RECT 91.52 81.36 92 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 95.2 86.8 95.68 87.28 ; + RECT 91.52 86.8 92 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 0 97.68 95.68 98.16 ; + RECT 91.52 92.24 92 92.72 ; + RECT 0 97.68 92 98.16 ; RECT 0 103.12 0.48 103.6 ; - RECT 67.6 103.12 68.08 103.6 ; - RECT 0 108.56 68.08 108.8 ; + RECT 65.76 103.12 66.24 103.6 ; + RECT 0 108.56 66.24 108.8 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 108.2 26.98 108.8 ; - RECT 55.82 108.2 56.42 108.8 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 108.2 26.06 108.8 ; + RECT 54.9 108.2 55.5 108.8 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 92.48 42.6 95.68 45.8 ; + RECT 88.8 42.6 92 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 92.48 83.4 95.68 86.6 ; + RECT 88.8 83.4 92 86.6 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] @@ -1541,123 +1541,120 @@ MACRO sb_0__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 75.37 96.56 75.51 97.92 ; + RECT 73.53 96.56 73.67 97.92 ; END END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 108.715 68.08 108.885 ; - RECT 67.16 105.995 68.08 106.165 ; + RECT 0 108.715 66.24 108.885 ; + RECT 65.32 105.995 66.24 106.165 ; RECT 0 105.995 3.68 106.165 ; - RECT 67.16 103.275 68.08 103.445 ; + RECT 65.32 103.275 66.24 103.445 ; RECT 0 103.275 3.68 103.445 ; - RECT 67.16 100.555 68.08 100.725 ; + RECT 65.32 100.555 66.24 100.725 ; RECT 0 100.555 3.68 100.725 ; - RECT 65.32 97.835 95.68 98.005 ; + RECT 63.02 97.835 92 98.005 ; RECT 0 97.835 3.68 98.005 ; - RECT 95.22 95.115 95.68 95.285 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 95.22 92.395 95.68 92.565 ; + RECT 91.08 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 95.22 89.675 95.68 89.845 ; + RECT 91.08 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 94.76 86.955 95.68 87.125 ; + RECT 88.32 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 94.76 84.235 95.68 84.405 ; + RECT 88.32 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 94.76 81.515 95.68 81.685 ; + RECT 91.08 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 94.76 78.795 95.68 78.965 ; + RECT 91.08 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 94.76 76.075 95.68 76.245 ; + RECT 91.08 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 94.76 73.355 95.68 73.525 ; + RECT 91.08 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 94.76 70.635 95.68 70.805 ; + RECT 91.08 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 95.22 67.915 95.68 68.085 ; + RECT 91.08 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 94.76 65.195 95.68 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 94.76 62.475 95.68 62.645 ; + RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 94.76 59.755 95.68 59.925 ; + RECT 91.54 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 94.76 57.035 95.68 57.205 ; + RECT 91.54 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 94.76 54.315 95.68 54.485 ; + RECT 91.08 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 94.76 51.595 95.68 51.765 ; + RECT 91.08 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 94.76 48.875 95.68 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 94.76 46.155 95.68 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 94.76 43.435 95.68 43.605 ; + RECT 88.32 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 94.76 40.715 95.68 40.885 ; + RECT 88.32 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 95.22 37.995 95.68 38.165 ; + RECT 91.54 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 95.22 35.275 95.68 35.445 ; + RECT 91.54 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 95.22 32.555 95.68 32.725 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 95.22 29.835 95.68 30.005 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 95.22 27.115 95.68 27.285 ; + RECT 91.08 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 92 24.395 95.68 24.565 ; + RECT 91.08 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 92 21.675 95.68 21.845 ; + RECT 91.08 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 92 18.955 95.68 19.125 ; + RECT 91.08 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 92 16.235 95.68 16.405 ; + RECT 88.32 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 94.76 13.515 95.68 13.685 ; + RECT 88.32 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 95.68 10.965 ; + RECT 63.02 10.795 92 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.78 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met2 ; - RECT 55.98 108.615 56.26 108.985 ; - RECT 26.54 108.615 26.82 108.985 ; - RECT 58.75 106.94 59.01 107.26 ; - RECT 51.85 106.94 52.11 107.26 ; - RECT 64.73 1.54 64.99 1.86 ; - RECT 56.91 1.54 57.17 1.86 ; - RECT 48.63 1.54 48.89 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 67.8 108.52 67.8 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 95.4 97.64 95.4 11.16 91.43 11.16 91.43 12.52 90.73 12.52 90.73 11.16 90.51 11.16 90.51 12.52 89.81 12.52 89.81 11.16 89.59 11.16 89.59 12.52 88.89 12.52 88.89 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.83 11.16 86.83 12.52 86.13 12.52 86.13 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 82.69 11.16 82.69 12.52 81.99 12.52 81.99 11.16 67.8 11.16 67.8 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 0.28 0.28 0.28 108.52 13.45 108.52 13.45 107.16 14.15 107.16 14.15 108.52 14.37 108.52 14.37 107.16 15.07 107.16 15.07 108.52 15.29 108.52 15.29 107.16 15.99 107.16 15.99 108.52 16.21 108.52 16.21 107.16 16.91 107.16 16.91 108.52 17.13 108.52 17.13 107.16 17.83 107.16 17.83 108.52 18.05 108.52 18.05 107.16 18.75 107.16 18.75 108.52 33.69 108.52 33.69 107.16 34.39 107.16 34.39 108.52 34.61 108.52 34.61 107.16 35.31 107.16 35.31 108.52 35.53 108.52 35.53 107.16 36.23 107.16 36.23 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 37.37 108.52 37.37 107.16 38.07 107.16 38.07 108.52 38.29 108.52 38.29 107.16 38.99 107.16 38.99 108.52 39.21 108.52 39.21 107.16 39.91 107.16 39.91 108.52 40.13 108.52 40.13 107.16 40.83 107.16 40.83 108.52 41.05 108.52 41.05 107.16 41.75 107.16 41.75 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 51.17 108.52 51.17 107.16 51.87 107.16 51.87 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 53.93 108.52 53.93 107.16 54.63 107.16 54.63 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 64.05 108.52 64.05 107.16 64.75 107.16 64.75 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 ; + RECT 55.06 108.615 55.34 108.985 ; + RECT 25.62 108.615 25.9 108.985 ; + RECT 83.13 12.42 83.39 12.74 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 65.96 108.52 65.96 97.64 73.25 97.64 73.25 96.28 73.95 96.28 73.95 97.64 91.72 97.64 91.72 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.37 11.16 86.37 12.52 85.67 12.52 85.67 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 83.15 11.16 83.15 12.52 82.45 12.52 82.45 11.16 80.85 11.16 80.85 12.52 80.15 12.52 80.15 11.16 79.01 11.16 79.01 12.52 78.31 12.52 78.31 11.16 76.25 11.16 76.25 12.52 75.55 12.52 75.55 11.16 65.96 11.16 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 108.52 7.93 108.52 7.93 107.16 8.63 107.16 8.63 108.52 8.85 108.52 8.85 107.16 9.55 107.16 9.55 108.52 27.25 108.52 27.25 107.16 27.95 107.16 27.95 108.52 28.17 108.52 28.17 107.16 28.87 107.16 28.87 108.52 29.09 108.52 29.09 107.16 29.79 107.16 29.79 108.52 30.01 108.52 30.01 107.16 30.71 107.16 30.71 108.52 33.23 108.52 33.23 107.16 33.93 107.16 33.93 108.52 39.67 108.52 39.67 107.16 40.37 107.16 40.37 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 52.55 108.52 52.55 107.16 53.25 107.16 53.25 108.52 53.47 108.52 53.47 107.16 54.17 107.16 54.17 108.52 55.77 108.52 55.77 107.16 56.47 107.16 56.47 108.52 56.69 108.52 56.69 107.16 57.39 107.16 57.39 108.52 57.61 108.52 57.61 107.16 58.31 107.16 58.31 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 ; LAYER met4 ; - POLYGON 67.68 108.4 67.68 97.52 84.86 97.52 84.86 96.92 86.26 96.92 86.26 97.52 95.28 97.52 95.28 11.28 86.26 11.28 86.26 11.88 84.86 11.88 84.86 11.28 67.68 11.28 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 108.4 11.26 108.4 11.26 107.8 12.66 107.8 12.66 108.4 15.09 108.4 15.09 107.04 16.19 107.04 16.19 108.4 16.93 108.4 16.93 107.04 18.03 107.04 18.03 108.4 25.98 108.4 25.98 107.8 27.38 107.8 27.38 108.4 33.49 108.4 33.49 107.04 34.59 107.04 34.59 108.4 35.33 108.4 35.33 107.04 36.43 107.04 36.43 108.4 37.17 108.4 37.17 107.04 38.27 107.04 38.27 108.4 39.01 108.4 39.01 107.04 40.11 107.04 40.11 108.4 40.7 108.4 40.7 107.8 42.1 107.8 42.1 108.4 53.73 108.4 53.73 107.04 54.83 107.04 54.83 108.4 55.42 108.4 55.42 107.8 56.82 107.8 56.82 108.4 57.41 108.4 57.41 107.04 58.51 107.04 58.51 108.4 59.25 108.4 59.25 107.04 60.35 107.04 60.35 108.4 61.09 108.4 61.09 107.04 62.19 107.04 62.19 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 ; + POLYGON 65.84 108.4 65.84 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 91.6 97.52 91.6 11.28 81.66 11.28 81.66 11.88 80.26 11.88 80.26 11.28 65.84 11.28 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 108.4 4.97 108.4 4.97 107.04 6.07 107.04 6.07 108.4 6.81 108.4 6.81 107.04 7.91 107.04 7.91 108.4 8.65 108.4 8.65 107.04 9.75 107.04 9.75 108.4 10.34 108.4 10.34 107.8 11.74 107.8 11.74 108.4 12.33 108.4 12.33 107.04 13.43 107.04 13.43 108.4 21.53 108.4 21.53 107.04 22.63 107.04 22.63 108.4 23.37 108.4 23.37 107.04 24.47 107.04 24.47 108.4 25.06 108.4 25.06 107.8 26.46 107.8 26.46 108.4 27.05 108.4 27.05 107.04 28.15 107.04 28.15 108.4 28.89 108.4 28.89 107.04 29.99 107.04 29.99 108.4 30.73 108.4 30.73 107.04 31.83 107.04 31.83 108.4 32.57 108.4 32.57 107.04 33.67 107.04 33.67 108.4 34.41 108.4 34.41 107.04 35.51 107.04 35.51 108.4 36.25 108.4 36.25 107.04 37.35 107.04 37.35 108.4 39.78 108.4 39.78 107.8 41.18 107.8 41.18 108.4 44.53 108.4 44.53 107.04 45.63 107.04 45.63 108.4 46.37 108.4 46.37 107.04 47.47 107.04 47.47 108.4 48.21 108.4 48.21 107.04 49.31 107.04 49.31 108.4 50.05 108.4 50.05 107.04 51.15 107.04 51.15 108.4 51.89 108.4 51.89 107.04 52.99 107.04 52.99 108.4 54.5 108.4 54.5 107.8 55.9 107.8 55.9 108.4 56.49 108.4 56.49 107.04 57.59 107.04 57.59 108.4 ; LAYER met3 ; - POLYGON 56.285 108.965 56.285 108.96 56.5 108.96 56.5 108.64 56.285 108.64 56.285 108.635 55.955 108.635 55.955 108.64 55.74 108.64 55.74 108.96 55.955 108.96 55.955 108.965 ; - POLYGON 26.845 108.965 26.845 108.96 27.06 108.96 27.06 108.64 26.845 108.64 26.845 108.635 26.515 108.635 26.515 108.64 26.3 108.64 26.3 108.96 26.515 108.96 26.515 108.965 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 67.68 108.4 67.68 97.52 95.28 97.52 95.28 93.03 93.9 93.03 93.9 91.93 95.28 91.93 95.28 91.67 93.9 91.67 93.9 90.57 95.28 90.57 95.28 90.31 93.9 90.31 93.9 89.21 95.28 89.21 95.28 88.95 93.9 88.95 93.9 87.85 95.28 87.85 95.28 87.59 93.9 87.59 93.9 86.49 95.28 86.49 95.28 85.55 93.9 85.55 93.9 84.45 95.28 84.45 95.28 84.19 93.9 84.19 93.9 83.09 95.28 83.09 95.28 82.83 93.9 82.83 93.9 81.73 95.28 81.73 95.28 81.47 93.9 81.47 93.9 80.37 95.28 80.37 95.28 80.11 93.9 80.11 93.9 79.01 95.28 79.01 95.28 78.75 93.9 78.75 93.9 77.65 95.28 77.65 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 73.31 93.9 73.31 93.9 72.21 95.28 72.21 95.28 71.95 93.9 71.95 93.9 70.85 95.28 70.85 95.28 69.91 93.9 69.91 93.9 68.81 95.28 68.81 95.28 67.87 93.9 67.87 93.9 66.77 95.28 66.77 95.28 66.51 93.9 66.51 93.9 65.41 95.28 65.41 95.28 65.15 93.9 65.15 93.9 64.05 95.28 64.05 95.28 63.11 93.9 63.11 93.9 62.01 95.28 62.01 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 60.39 93.9 60.39 93.9 59.29 95.28 59.29 95.28 59.03 93.9 59.03 93.9 57.93 95.28 57.93 95.28 57.67 93.9 57.67 93.9 56.57 95.28 56.57 95.28 56.31 93.9 56.31 93.9 55.21 95.28 55.21 95.28 54.95 93.9 54.95 93.9 53.85 95.28 53.85 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 51.55 93.9 51.55 93.9 50.45 95.28 50.45 95.28 50.19 93.9 50.19 93.9 49.09 95.28 49.09 95.28 48.83 93.9 48.83 93.9 47.73 95.28 47.73 95.28 47.47 93.9 47.47 93.9 46.37 95.28 46.37 95.28 46.11 93.9 46.11 93.9 45.01 95.28 45.01 95.28 44.75 93.9 44.75 93.9 43.65 95.28 43.65 95.28 43.39 93.9 43.39 93.9 42.29 95.28 42.29 95.28 42.03 93.9 42.03 93.9 40.93 95.28 40.93 95.28 40.67 93.9 40.67 93.9 39.57 95.28 39.57 95.28 39.31 93.9 39.31 93.9 38.21 95.28 38.21 95.28 37.95 93.9 37.95 93.9 36.85 95.28 36.85 95.28 36.59 93.9 36.59 93.9 35.49 95.28 35.49 95.28 32.51 93.9 32.51 93.9 31.41 95.28 31.41 95.28 11.28 67.68 11.28 67.68 0.4 0.4 0.4 0.4 108.4 ; + POLYGON 55.365 108.965 55.365 108.96 55.58 108.96 55.58 108.64 55.365 108.64 55.365 108.635 55.035 108.635 55.035 108.64 54.82 108.64 54.82 108.96 55.035 108.96 55.035 108.965 ; + POLYGON 25.925 108.965 25.925 108.96 26.14 108.96 26.14 108.64 25.925 108.64 25.925 108.635 25.595 108.635 25.595 108.64 25.38 108.64 25.38 108.96 25.595 108.96 25.595 108.965 ; + POLYGON 90.77 78.35 90.77 78.07 90.22 78.07 90.22 78.05 57.81 78.05 57.81 78.35 ; + POLYGON 90.35 77 90.35 76.68 89.97 76.68 89.97 76.69 75.29 76.69 75.29 76.99 89.97 76.99 89.97 77 ; + POLYGON 90.22 69.51 90.22 68.81 90.31 68.81 90.31 68.53 58.27 68.53 58.27 68.83 90.01 68.83 90.01 69.51 ; + POLYGON 90.77 34.83 90.77 34.55 90.22 34.55 90.22 34.53 32.97 34.53 32.97 34.83 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 65.84 108.4 65.84 97.52 91.6 97.52 91.6 93.03 90.22 93.03 90.22 91.93 91.6 91.93 91.6 91.67 90.22 91.67 90.22 90.57 91.6 90.57 91.6 90.31 90.22 90.31 90.22 89.21 91.6 89.21 91.6 84.87 90.22 84.87 90.22 83.77 91.6 83.77 91.6 83.51 90.22 83.51 90.22 82.41 91.6 82.41 91.6 82.15 90.22 82.15 90.22 81.05 91.6 81.05 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.71 90.22 76.71 90.22 75.61 91.6 75.61 91.6 75.35 90.22 75.35 90.22 74.25 91.6 74.25 91.6 73.99 90.22 73.99 90.22 72.89 91.6 72.89 91.6 72.63 90.22 72.63 90.22 71.53 91.6 71.53 91.6 71.27 90.22 71.27 90.22 70.17 91.6 70.17 91.6 69.91 90.22 69.91 90.22 68.81 91.6 68.81 91.6 68.55 90.22 68.55 90.22 67.45 91.6 67.45 91.6 67.19 90.22 67.19 90.22 66.09 91.6 66.09 91.6 65.83 90.22 65.83 90.22 64.73 91.6 64.73 91.6 64.47 90.22 64.47 90.22 63.37 91.6 63.37 91.6 62.43 90.22 62.43 90.22 61.33 91.6 61.33 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 56.31 90.22 56.31 90.22 55.21 91.6 55.21 91.6 54.95 90.22 54.95 90.22 53.85 91.6 53.85 91.6 53.59 90.22 53.59 90.22 52.49 91.6 52.49 91.6 52.23 90.22 52.23 90.22 51.13 91.6 51.13 91.6 50.87 90.22 50.87 90.22 49.77 91.6 49.77 91.6 49.51 90.22 49.51 90.22 48.41 91.6 48.41 91.6 48.15 90.22 48.15 90.22 47.05 91.6 47.05 91.6 46.79 90.22 46.79 90.22 45.69 91.6 45.69 91.6 45.43 90.22 45.43 90.22 44.33 91.6 44.33 91.6 44.07 90.22 44.07 90.22 42.97 91.6 42.97 91.6 42.71 90.22 42.71 90.22 41.61 91.6 41.61 91.6 41.35 90.22 41.35 90.22 40.25 91.6 40.25 91.6 39.99 90.22 39.99 90.22 38.89 91.6 38.89 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 32.51 90.22 32.51 90.22 31.41 91.6 31.41 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 108.4 ; LAYER met5 ; - POLYGON 66.48 107.2 66.48 96.32 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 12.48 66.48 12.48 66.48 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 107.2 ; + POLYGON 64.64 107.2 64.64 96.32 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 107.2 ; LAYER met1 ; - POLYGON 67.8 108.28 67.8 106.6 67.32 106.6 67.32 105.56 67.8 105.56 67.8 103.88 67.32 103.88 67.32 102.84 67.8 102.84 67.8 101.16 67.32 101.16 67.32 100.12 67.8 100.12 67.8 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; + POLYGON 47.54 98.57 47.54 98.31 47.22 98.31 47.22 98.37 46.145 98.37 46.145 98.325 45.855 98.325 45.855 98.555 46.145 98.555 46.145 98.51 47.22 98.51 47.22 98.57 ; + POLYGON 65.96 108.28 65.96 106.6 65.48 106.6 65.48 105.56 65.96 105.56 65.96 103.88 65.48 103.88 65.48 102.84 65.96 102.84 65.96 101.16 65.48 101.16 65.48 100.12 65.96 100.12 65.96 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; LAYER li1 ; - POLYGON 67.91 108.63 67.91 97.75 95.51 97.75 95.51 11.05 67.91 11.05 67.91 0.17 0.17 0.17 0.17 108.63 ; + POLYGON 66.07 108.63 66.07 97.75 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 108.63 ; LAYER mcon ; - RECT 67.765 108.715 67.935 108.885 ; - RECT 67.305 108.715 67.475 108.885 ; - RECT 66.845 108.715 67.015 108.885 ; - RECT 66.385 108.715 66.555 108.885 ; RECT 65.925 108.715 66.095 108.885 ; RECT 65.465 108.715 65.635 108.885 ; RECT 65.005 108.715 65.175 108.885 ; @@ -1802,26 +1799,19 @@ MACRO sb_0__1_ RECT 1.065 108.715 1.235 108.885 ; RECT 0.605 108.715 0.775 108.885 ; RECT 0.145 108.715 0.315 108.885 ; - RECT 67.765 105.995 67.935 106.165 ; - RECT 67.305 105.995 67.475 106.165 ; + RECT 65.925 105.995 66.095 106.165 ; + RECT 65.465 105.995 65.635 106.165 ; RECT 0.605 105.995 0.775 106.165 ; RECT 0.145 105.995 0.315 106.165 ; - RECT 67.765 103.275 67.935 103.445 ; - RECT 67.305 103.275 67.475 103.445 ; + RECT 65.925 103.275 66.095 103.445 ; + RECT 65.465 103.275 65.635 103.445 ; RECT 0.605 103.275 0.775 103.445 ; RECT 0.145 103.275 0.315 103.445 ; - RECT 67.765 100.555 67.935 100.725 ; - RECT 67.305 100.555 67.475 100.725 ; + RECT 65.925 100.555 66.095 100.725 ; + RECT 65.465 100.555 65.635 100.725 ; RECT 0.605 100.555 0.775 100.725 ; RECT 0.145 100.555 0.315 100.725 ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; + RECT 45.915 98.355 46.085 98.525 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -2022,138 +2012,130 @@ MACRO sb_0__1_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; RECT 91.685 10.795 91.855 10.965 ; RECT 91.225 10.795 91.395 10.965 ; RECT 90.765 10.795 90.935 10.965 ; @@ -2354,22 +2336,18 @@ MACRO sb_0__1_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -2515,36 +2493,36 @@ MACRO sb_0__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 108.725 56.195 108.875 ; - RECT 26.605 108.725 26.755 108.875 ; - RECT 61.105 107.025 61.255 107.175 ; - RECT 38.565 107.025 38.715 107.175 ; - RECT 56.045 97.845 56.195 97.995 ; - RECT 26.605 97.845 26.755 97.995 ; - RECT 56.045 10.805 56.195 10.955 ; - RECT 26.605 10.805 26.755 10.955 ; - RECT 61.105 1.625 61.255 1.775 ; - RECT 42.705 1.625 42.855 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 108.725 55.275 108.875 ; + RECT 25.685 108.725 25.835 108.875 ; + RECT 47.305 98.365 47.455 98.515 ; + RECT 55.125 97.845 55.275 97.995 ; + RECT 25.685 97.845 25.835 97.995 ; + RECT 88.245 12.505 88.395 12.655 ; + RECT 80.425 12.505 80.575 12.655 ; + RECT 55.125 10.805 55.275 10.955 ; + RECT 25.685 10.805 25.835 10.955 ; + RECT 60.185 1.625 60.335 1.775 ; + RECT 47.305 1.625 47.455 1.775 ; + RECT 31.205 1.625 31.355 1.775 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 108.7 56.22 108.9 ; - RECT 26.58 108.7 26.78 108.9 ; - RECT 94.2 88.3 94.4 88.5 ; - RECT 94.2 86.94 94.4 87.14 ; - RECT 94.2 65.86 94.4 66.06 ; - RECT 94.2 49.54 94.4 49.74 ; - RECT 94.2 45.46 94.4 45.66 ; - RECT 94.2 37.3 94.4 37.5 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 108.7 55.3 108.9 ; + RECT 25.66 108.7 25.86 108.9 ; + RECT 90.52 70.62 90.72 70.82 ; + RECT 90.52 52.94 90.72 53.14 ; + RECT 90.06 37.98 90.26 38.18 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 108.7 56.22 108.9 ; - RECT 26.58 108.7 26.78 108.9 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 108.7 55.3 108.9 ; + RECT 25.66 108.7 25.86 108.9 ; + RECT 90.06 36.62 90.26 36.82 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 108.8 68.08 108.8 68.08 97.92 95.68 97.92 95.68 10.88 68.08 10.88 68.08 0 ; + POLYGON 0 0 0 108.8 66.24 108.8 66.24 97.92 92 97.92 92 10.88 66.24 10.88 66.24 0 ; END END sb_0__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef index 9d98cfe..8412b71 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 97.92 ; + SIZE 92 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + LAYER met3 ; + RECT 90.62 17.53 92 17.83 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 71.25 95.68 71.55 ; + RECT 90.62 81.45 92 81.75 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 34.53 95.68 34.83 ; + RECT 90.62 53.57 92 53.87 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 73.97 95.68 74.27 ; + RECT 90.62 80.09 92 80.39 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 81.45 95.68 81.75 ; + RECT 90.62 72.61 92 72.91 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 35.89 95.68 36.19 ; + RECT 90.62 33.85 92 34.15 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 17.53 95.68 17.83 ; + RECT 90.62 22.97 92 23.27 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 40.65 95.68 40.95 ; + RECT 90.62 24.33 92 24.63 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 50.17 95.68 50.47 ; + RECT 90.62 49.49 92 49.79 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 76.69 95.68 76.99 ; + RECT 90.62 77.37 92 77.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -443,7 +443,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 61.05 95.68 61.35 ; + RECT 90.62 59.69 92 59.99 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -451,7 +451,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 72.61 95.68 72.91 ; + RECT 90.62 73.97 92 74.27 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 80.09 95.68 80.39 ; + RECT 90.62 68.53 92 68.83 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 57.65 95.68 57.95 ; + RECT 90.62 50.85 92 51.15 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -475,7 +475,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 67.85 95.68 68.15 ; + RECT 90.62 71.25 92 71.55 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -483,7 +483,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 54.93 95.68 55.23 ; + RECT 90.62 31.13 92 31.43 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 52.89 95.68 53.19 ; + RECT 90.62 55.61 92 55.91 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 59.69 95.68 59.99 ; + RECT 90.62 29.09 92 29.39 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 84.17 95.68 84.47 ; + RECT 90.62 52.21 92 52.51 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 75.33 95.68 75.63 ; + RECT 90.62 56.97 92 57.27 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 62.41 95.68 62.71 ; + RECT 90.62 58.33 92 58.63 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 37.25 95.68 37.55 ; + RECT 90.62 37.93 92 38.23 ; END END right_top_grid_pin_1_[0] PIN right_bottom_grid_pin_34_[0] @@ -539,7 +539,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.33 10.88 87.47 12.24 ; + RECT 83.65 10.88 83.79 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -547,7 +547,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 88.25 10.88 88.39 12.24 ; + RECT 85.95 10.88 86.09 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] @@ -555,7 +555,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.27 10.88 82.41 12.24 ; + RECT 88.25 10.88 88.39 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -563,7 +563,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.03 10.88 85.17 12.24 ; + RECT 82.73 10.88 82.87 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -571,7 +571,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 91.01 10.88 91.15 12.24 ; + RECT 85.03 10.88 85.17 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -579,7 +579,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 89.17 10.88 89.31 12.24 ; + RECT 87.33 10.88 87.47 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -587,7 +587,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 90.09 10.88 90.23 12.24 ; + RECT 75.83 10.88 75.97 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -595,7 +595,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 86.41 10.88 86.55 12.24 ; + RECT 80.43 10.88 80.57 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -603,7 +603,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -611,7 +611,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -619,7 +619,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 0 18.47 1.36 ; + RECT 26.61 0 26.75 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -707,7 +707,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 29.37 0 29.51 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 0 13.87 1.36 ; + RECT 30.29 0 30.43 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 8.21 0 8.35 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,7 +755,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -763,7 +763,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] @@ -771,7 +771,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 42.69 95.68 42.99 ; + RECT 90.62 48.13 92 48.43 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -779,7 +779,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 31.81 95.68 32.11 ; + RECT 90.62 14.13 92 14.43 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -787,7 +787,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 33.17 95.68 33.47 ; + RECT 90.62 32.49 92 32.79 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -795,7 +795,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 29.09 95.68 29.39 ; + RECT 90.62 15.49 92 15.79 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -803,7 +803,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 30.45 95.68 30.75 ; + RECT 90.62 61.05 92 61.35 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -811,7 +811,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 63.77 95.68 64.07 ; + RECT 90.62 21.61 92 21.91 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -819,7 +819,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 19.57 95.68 19.87 ; + RECT 90.62 26.37 92 26.67 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -827,7 +827,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 46.09 95.68 46.39 ; + RECT 90.62 46.77 92 47.07 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -835,7 +835,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 27.73 95.68 28.03 ; + RECT 90.62 41.33 92 41.63 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -843,7 +843,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 48.13 95.68 48.43 ; + RECT 90.62 67.17 92 67.47 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -851,7 +851,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 24.33 95.68 24.63 ; + RECT 90.62 44.05 92 44.35 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -859,7 +859,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 51.53 95.68 51.83 ; + RECT 90.62 36.57 92 36.87 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -867,7 +867,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 22.97 95.68 23.27 ; + RECT 90.62 39.97 92 40.27 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -875,7 +875,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 56.29 95.68 56.59 ; + RECT 90.62 20.25 92 20.55 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -883,7 +883,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 26.37 95.68 26.67 ; + RECT 90.62 27.73 92 28.03 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -891,7 +891,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 44.05 95.68 44.35 ; + RECT 90.62 69.89 92 70.19 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -899,7 +899,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 38.61 95.68 38.91 ; + RECT 90.62 42.69 92 42.99 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -907,7 +907,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 69.89 95.68 70.19 ; + RECT 90.62 75.33 92 75.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -915,7 +915,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 82.81 95.68 83.11 ; + RECT 90.62 45.41 92 45.71 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -923,7 +923,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 65.81 95.68 66.11 ; + RECT 90.62 64.45 92 64.75 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -931,7 +931,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 21.61 95.68 21.91 ; + RECT 90.62 35.21 92 35.51 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -939,7 +939,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -947,7 +947,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -955,15 +955,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; + LAYER met4 ; + RECT 46.77 0 47.07 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -971,31 +971,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 17.41 0 17.55 1.36 ; + LAYER met4 ; + RECT 5.37 0 5.67 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + LAYER met4 ; + RECT 27.45 0 27.75 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + LAYER met4 ; + RECT 48.61 0 48.91 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1003,15 +1003,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; + LAYER met4 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1019,15 +1019,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; + LAYER met4 ; + RECT 29.29 0 29.59 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1035,31 +1035,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 28.45 0 28.59 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; + LAYER met4 ; + RECT 7.21 0 7.51 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 16.49 0 16.63 1.36 ; + LAYER met4 ; + RECT 9.05 0 9.35 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + LAYER met4 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1067,7 +1067,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1075,7 +1075,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1083,7 +1083,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.57 0 15.71 1.36 ; + RECT 9.13 0 9.27 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1091,7 +1091,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1099,7 +1099,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1131,7 +1131,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 94.3 78.73 95.68 79.03 ; + RECT 90.62 78.73 92 79.03 ; END END SC_OUT_BOT PIN VDD @@ -1140,53 +1140,53 @@ MACRO sb_0__2_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 67.6 2.48 68.08 2.96 ; + RECT 65.76 2.48 66.24 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 67.6 7.92 68.08 8.4 ; + RECT 65.76 7.92 66.24 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; + RECT 91.52 84.08 92 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 95.2 89.52 95.68 90 ; + RECT 91.52 89.52 92 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; + RECT 91.52 94.96 92 95.44 ; LAYER met4 ; - RECT 11.66 0 12.26 0.6 ; - RECT 41.1 0 41.7 0.6 ; - RECT 85.26 10.88 85.86 11.48 ; - RECT 11.66 97.32 12.26 97.92 ; - RECT 41.1 97.32 41.7 97.92 ; - RECT 85.26 97.32 85.86 97.92 ; + RECT 10.74 0 11.34 0.6 ; + RECT 40.18 0 40.78 0.6 ; + RECT 80.66 10.88 81.26 11.48 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 40.18 97.32 40.78 97.92 ; + RECT 80.66 97.32 81.26 97.92 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 92.48 22.2 95.68 25.4 ; + RECT 88.8 22.2 92 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 92.48 63 95.68 66.2 ; + RECT 88.8 63 92 66.2 ; END END VDD PIN VSS @@ -1194,160 +1194,151 @@ MACRO sb_0__2_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 68.08 0.24 ; + RECT 0 0 66.24 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 67.6 5.2 68.08 5.68 ; - RECT 0 10.64 95.68 11.12 ; + RECT 65.76 5.2 66.24 5.68 ; + RECT 0 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; + RECT 91.52 81.36 92 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 95.2 86.8 95.68 87.28 ; + RECT 91.52 86.8 92 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 0 97.68 95.68 97.92 ; + RECT 91.52 92.24 92 92.72 ; + RECT 0 97.68 92 97.92 ; LAYER met4 ; - RECT 26.38 0 26.98 0.6 ; - RECT 55.82 0 56.42 0.6 ; - RECT 26.38 97.32 26.98 97.92 ; - RECT 55.82 97.32 56.42 97.92 ; + RECT 25.46 0 26.06 0.6 ; + RECT 54.9 0 55.5 0.6 ; + RECT 25.46 97.32 26.06 97.92 ; + RECT 54.9 97.32 55.5 97.92 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 92.48 42.6 95.68 45.8 ; + RECT 88.8 42.6 92 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 92.48 83.4 95.68 86.6 ; + RECT 88.8 83.4 92 86.6 ; END END VSS OBS LAYER li1 ; - RECT 0 97.835 95.68 98.005 ; - RECT 95.22 95.115 95.68 95.285 ; + RECT 0 97.835 92 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 95.22 92.395 95.68 92.565 ; + RECT 91.54 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 95.22 89.675 95.68 89.845 ; + RECT 91.54 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 94.76 86.955 95.68 87.125 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 94.76 84.235 95.68 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 94.76 81.515 95.68 81.685 ; + RECT 91.08 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 94.76 78.795 95.68 78.965 ; + RECT 91.08 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 94.76 76.075 95.68 76.245 ; + RECT 91.54 76.075 92 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 94.76 73.355 95.68 73.525 ; + RECT 91.54 73.355 92 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 95.22 70.635 95.68 70.805 ; + RECT 91.08 70.635 92 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 95.22 67.915 95.68 68.085 ; + RECT 91.08 67.915 92 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 93.84 65.195 95.68 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 92 62.475 95.68 62.645 ; + RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 92 59.755 95.68 59.925 ; + RECT 91.54 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 94.76 57.035 95.68 57.205 ; + RECT 91.54 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 94.76 54.315 95.68 54.485 ; + RECT 90.16 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 95.22 51.595 95.68 51.765 ; + RECT 90.16 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 94.76 48.875 95.68 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 94.76 46.155 95.68 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 94.76 43.435 95.68 43.605 ; + RECT 91.08 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 94.76 40.715 95.68 40.885 ; + RECT 91.08 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 94.76 37.995 95.68 38.165 ; + RECT 88.32 37.995 92 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 94.76 35.275 95.68 35.445 ; + RECT 88.32 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 94.76 32.555 95.68 32.725 ; + RECT 91.08 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 94.76 29.835 95.68 30.005 ; + RECT 91.08 29.835 92 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 94.76 27.115 95.68 27.285 ; + RECT 91.08 27.115 92 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 94.76 24.395 95.68 24.565 ; + RECT 91.08 24.395 92 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 94.76 21.675 95.68 21.845 ; + RECT 90.16 21.675 92 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 94.76 18.955 95.68 19.125 ; + RECT 90.16 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 94.76 16.235 95.68 16.405 ; + RECT 88.32 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 95.22 13.515 95.68 13.685 ; + RECT 88.32 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 64.86 10.795 95.68 10.965 ; + RECT 63.48 10.795 92 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 67.16 8.075 68.08 8.245 ; + RECT 65.32 8.075 66.24 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 67.16 5.355 68.08 5.525 ; + RECT 65.32 5.355 66.24 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 67.16 2.635 68.08 2.805 ; + RECT 65.78 2.635 66.24 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 68.08 0.085 ; - LAYER met2 ; - RECT 55.98 97.735 56.26 98.105 ; - RECT 26.54 97.735 26.82 98.105 ; - RECT 53.23 1.54 53.49 1.86 ; - RECT 46.79 1.54 47.05 1.86 ; - RECT 38.51 1.54 38.77 1.86 ; - RECT 55.98 -0.185 56.26 0.185 ; - RECT 26.54 -0.185 26.82 0.185 ; - POLYGON 95.4 97.64 95.4 11.16 91.43 11.16 91.43 12.52 90.73 12.52 90.73 11.16 90.51 11.16 90.51 12.52 89.81 12.52 89.81 11.16 89.59 11.16 89.59 12.52 88.89 12.52 88.89 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.83 11.16 86.83 12.52 86.13 12.52 86.13 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 82.69 11.16 82.69 12.52 81.99 12.52 81.99 11.16 67.8 11.16 67.8 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 0.28 0.28 0.28 97.64 ; + RECT 0 -0.085 66.24 0.085 ; LAYER met3 ; - POLYGON 56.285 98.085 56.285 98.08 56.5 98.08 56.5 97.76 56.285 97.76 56.285 97.755 55.955 97.755 55.955 97.76 55.74 97.76 55.74 98.08 55.955 98.08 55.955 98.085 ; - POLYGON 26.845 98.085 26.845 98.08 27.06 98.08 27.06 97.76 26.845 97.76 26.845 97.755 26.515 97.755 26.515 97.76 26.3 97.76 26.3 98.08 26.515 98.08 26.515 98.085 ; - POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; - POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; - POLYGON 95.28 97.52 95.28 84.87 93.9 84.87 93.9 83.77 95.28 83.77 95.28 83.51 93.9 83.51 93.9 82.41 95.28 82.41 95.28 82.15 93.9 82.15 93.9 81.05 95.28 81.05 95.28 80.79 93.9 80.79 93.9 79.69 95.28 79.69 95.28 79.43 93.9 79.43 93.9 78.33 95.28 78.33 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 73.31 93.9 73.31 93.9 72.21 95.28 72.21 95.28 71.95 93.9 71.95 93.9 70.85 95.28 70.85 95.28 70.59 93.9 70.59 93.9 69.49 95.28 69.49 95.28 68.55 93.9 68.55 93.9 67.45 95.28 67.45 95.28 66.51 93.9 66.51 93.9 65.41 95.28 65.41 95.28 64.47 93.9 64.47 93.9 63.37 95.28 63.37 95.28 63.11 93.9 63.11 93.9 62.01 95.28 62.01 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 60.39 93.9 60.39 93.9 59.29 95.28 59.29 95.28 58.35 93.9 58.35 93.9 57.25 95.28 57.25 95.28 56.99 93.9 56.99 93.9 55.89 95.28 55.89 95.28 55.63 93.9 55.63 93.9 54.53 95.28 54.53 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 52.23 93.9 52.23 93.9 51.13 95.28 51.13 95.28 50.87 93.9 50.87 93.9 49.77 95.28 49.77 95.28 48.83 93.9 48.83 93.9 47.73 95.28 47.73 95.28 46.79 93.9 46.79 93.9 45.69 95.28 45.69 95.28 44.75 93.9 44.75 93.9 43.65 95.28 43.65 95.28 43.39 93.9 43.39 93.9 42.29 95.28 42.29 95.28 41.35 93.9 41.35 93.9 40.25 95.28 40.25 95.28 39.31 93.9 39.31 93.9 38.21 95.28 38.21 95.28 37.95 93.9 37.95 93.9 36.85 95.28 36.85 95.28 36.59 93.9 36.59 93.9 35.49 95.28 35.49 95.28 35.23 93.9 35.23 93.9 34.13 95.28 34.13 95.28 33.87 93.9 33.87 93.9 32.77 95.28 32.77 95.28 32.51 93.9 32.51 93.9 31.41 95.28 31.41 95.28 31.15 93.9 31.15 93.9 30.05 95.28 30.05 95.28 29.79 93.9 29.79 93.9 28.69 95.28 28.69 95.28 28.43 93.9 28.43 93.9 27.33 95.28 27.33 95.28 27.07 93.9 27.07 93.9 25.97 95.28 25.97 95.28 25.03 93.9 25.03 93.9 23.93 95.28 23.93 95.28 23.67 93.9 23.67 93.9 22.57 95.28 22.57 95.28 22.31 93.9 22.31 93.9 21.21 95.28 21.21 95.28 20.27 93.9 20.27 93.9 19.17 95.28 19.17 95.28 18.23 93.9 18.23 93.9 17.13 95.28 17.13 95.28 11.28 67.68 11.28 67.68 0.4 0.4 0.4 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 97.52 ; - LAYER met5 ; - POLYGON 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 12.48 66.48 12.48 66.48 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; + POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; + POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; + POLYGON 90.77 57.95 90.77 57.67 90.22 57.67 90.22 57.65 77.13 57.65 77.13 57.95 ; + POLYGON 90.22 22.59 90.22 22.57 90.77 22.57 90.77 22.29 13.19 22.29 13.19 22.59 ; + POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; + POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; + POLYGON 91.6 97.52 91.6 82.15 90.22 82.15 90.22 81.05 91.6 81.05 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.03 90.22 76.03 90.22 74.93 91.6 74.93 91.6 74.67 90.22 74.67 90.22 73.57 91.6 73.57 91.6 73.31 90.22 73.31 90.22 72.21 91.6 72.21 91.6 71.95 90.22 71.95 90.22 70.85 91.6 70.85 91.6 70.59 90.22 70.59 90.22 69.49 91.6 69.49 91.6 69.23 90.22 69.23 90.22 68.13 91.6 68.13 91.6 67.87 90.22 67.87 90.22 66.77 91.6 66.77 91.6 65.15 90.22 65.15 90.22 64.05 91.6 64.05 91.6 61.75 90.22 61.75 90.22 60.65 91.6 60.65 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 56.31 90.22 56.31 90.22 55.21 91.6 55.21 91.6 54.27 90.22 54.27 90.22 53.17 91.6 53.17 91.6 52.91 90.22 52.91 90.22 51.81 91.6 51.81 91.6 51.55 90.22 51.55 90.22 50.45 91.6 50.45 91.6 50.19 90.22 50.19 90.22 49.09 91.6 49.09 91.6 48.83 90.22 48.83 90.22 47.73 91.6 47.73 91.6 47.47 90.22 47.47 90.22 46.37 91.6 46.37 91.6 46.11 90.22 46.11 90.22 45.01 91.6 45.01 91.6 44.75 90.22 44.75 90.22 43.65 91.6 43.65 91.6 43.39 90.22 43.39 90.22 42.29 91.6 42.29 91.6 42.03 90.22 42.03 90.22 40.93 91.6 40.93 91.6 40.67 90.22 40.67 90.22 39.57 91.6 39.57 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 33.19 90.22 33.19 90.22 32.09 91.6 32.09 91.6 31.83 90.22 31.83 90.22 30.73 91.6 30.73 91.6 29.79 90.22 29.79 90.22 28.69 91.6 28.69 91.6 28.43 90.22 28.43 90.22 27.33 91.6 27.33 91.6 27.07 90.22 27.07 90.22 25.97 91.6 25.97 91.6 25.03 90.22 25.03 90.22 23.93 91.6 23.93 91.6 23.67 90.22 23.67 90.22 22.57 91.6 22.57 91.6 22.31 90.22 22.31 90.22 21.21 91.6 21.21 91.6 20.95 90.22 20.95 90.22 19.85 91.6 19.85 91.6 18.23 90.22 18.23 90.22 17.13 91.6 17.13 91.6 16.19 90.22 16.19 90.22 15.09 91.6 15.09 91.6 14.83 90.22 14.83 90.22 13.73 91.6 13.73 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 97.52 ; + LAYER met2 ; + RECT 55.06 97.735 55.34 98.105 ; + RECT 25.62 97.735 25.9 98.105 ; + RECT 55.06 -0.185 55.34 0.185 ; + RECT 25.62 -0.185 25.9 0.185 ; + POLYGON 91.72 97.64 91.72 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.37 11.16 86.37 12.52 85.67 12.52 85.67 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 83.15 11.16 83.15 12.52 82.45 12.52 82.45 11.16 80.85 11.16 80.85 12.52 80.15 12.52 80.15 11.16 76.25 11.16 76.25 12.52 75.55 12.52 75.55 11.16 65.96 11.16 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 97.64 ; LAYER met4 ; - POLYGON 95.28 97.52 95.28 11.28 86.26 11.28 86.26 11.88 84.86 11.88 84.86 11.28 67.68 11.28 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 97.52 11.26 97.52 11.26 96.92 12.66 96.92 12.66 97.52 25.98 97.52 25.98 96.92 27.38 96.92 27.38 97.52 40.7 97.52 40.7 96.92 42.1 96.92 42.1 97.52 55.42 97.52 55.42 96.92 56.82 96.92 56.82 97.52 84.86 97.52 84.86 96.92 86.26 96.92 86.26 97.52 ; + POLYGON 91.6 97.52 91.6 11.28 81.66 11.28 81.66 11.88 80.26 11.88 80.26 11.28 65.84 11.28 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; + LAYER met5 ; + POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; LAYER li1 ; - POLYGON 95.51 97.75 95.51 11.05 67.91 11.05 67.91 0.17 0.17 0.17 0.17 97.75 ; + POLYGON 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -1548,138 +1539,130 @@ MACRO sb_0__2_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; RECT 91.685 10.795 91.855 10.965 ; RECT 91.225 10.795 91.395 10.965 ; RECT 90.765 10.795 90.935 10.965 ; @@ -1880,22 +1863,18 @@ MACRO sb_0__2_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 67.765 8.075 67.935 8.245 ; - RECT 67.305 8.075 67.475 8.245 ; + RECT 65.925 8.075 66.095 8.245 ; + RECT 65.465 8.075 65.635 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 67.765 5.355 67.935 5.525 ; - RECT 67.305 5.355 67.475 5.525 ; + RECT 65.925 5.355 66.095 5.525 ; + RECT 65.465 5.355 65.635 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 67.765 2.635 67.935 2.805 ; - RECT 67.305 2.635 67.475 2.805 ; + RECT 65.925 2.635 66.095 2.805 ; + RECT 65.465 2.635 65.635 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -2041,39 +2020,31 @@ MACRO sb_0__2_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 56.045 97.845 56.195 97.995 ; - RECT 26.605 97.845 26.755 97.995 ; - RECT 82.265 12.505 82.415 12.655 ; - RECT 56.045 10.805 56.195 10.955 ; - RECT 26.605 10.805 26.755 10.955 ; - RECT 55.125 1.625 55.275 1.775 ; - RECT 42.705 1.625 42.855 1.775 ; - RECT 36.265 1.625 36.415 1.775 ; - RECT 34.425 1.625 34.575 1.775 ; - RECT 17.405 1.625 17.555 1.775 ; - RECT 56.045 -0.075 56.195 0.075 ; - RECT 26.605 -0.075 26.755 0.075 ; + RECT 55.125 97.845 55.275 97.995 ; + RECT 25.685 97.845 25.835 97.995 ; + RECT 85.025 12.505 85.175 12.655 ; + RECT 55.125 10.805 55.275 10.955 ; + RECT 25.685 10.805 25.835 10.955 ; + RECT 55.125 -0.075 55.275 0.075 ; + RECT 25.685 -0.075 25.835 0.075 ; LAYER via2 ; - RECT 56.02 97.82 56.22 98.02 ; - RECT 26.58 97.82 26.78 98.02 ; - RECT 93.74 78.78 93.94 78.98 ; + RECT 55.1 97.82 55.3 98.02 ; + RECT 25.66 97.82 25.86 98.02 ; + RECT 90.06 78.78 90.26 78.98 ; RECT 1.28 77.42 1.48 77.62 ; - RECT 94.2 69.94 94.4 70.14 ; - RECT 94.2 61.1 94.4 61.3 ; - RECT 94.2 52.94 94.4 53.14 ; + RECT 90.52 48.18 90.72 48.38 ; RECT 1.28 47.5 1.48 47.7 ; - RECT 94.2 42.74 94.4 42.94 ; - RECT 93.74 34.58 93.94 34.78 ; - RECT 94.2 23.02 94.4 23.22 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 90.52 29.14 90.72 29.34 ; + RECT 90.06 24.38 90.26 24.58 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER via3 ; - RECT 56.02 97.82 56.22 98.02 ; - RECT 26.58 97.82 26.78 98.02 ; - RECT 56.02 -0.1 56.22 0.1 ; - RECT 26.58 -0.1 26.78 0.1 ; + RECT 55.1 97.82 55.3 98.02 ; + RECT 25.66 97.82 25.86 98.02 ; + RECT 55.1 -0.1 55.3 0.1 ; + RECT 25.66 -0.1 25.86 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 97.92 95.68 97.92 95.68 10.88 68.08 10.88 68.08 0 ; + POLYGON 0 0 0 97.92 92 97.92 92 10.88 66.24 10.88 66.24 0 ; END END sb_0__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef index d4402d5..1e482d1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 123.28 BY 97.92 ; + SIZE 117.76 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 55.59 0 55.73 1.36 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 96.56 67.69 97.92 ; + RECT 63.87 96.56 64.01 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,15 +379,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; + LAYER met4 ; + RECT 67.93 96.56 68.23 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 96.56 80.57 97.92 ; + RECT 78.13 96.56 78.27 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 96.56 60.79 97.92 ; + RECT 58.35 96.56 58.49 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.99 96.56 74.13 97.92 ; + RECT 68.93 96.56 69.07 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 96.56 58.95 97.92 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.83 96.56 75.97 97.92 ; + RECT 73.53 96.56 73.67 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; + RECT 56.51 96.56 56.65 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,15 +443,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 96.56 71.37 97.92 ; + RECT 77.21 96.56 77.35 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 66.09 96.56 66.39 97.92 ; + LAYER met2 ; + RECT 66.17 96.56 66.31 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,15 +459,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; + RECT 43.63 96.56 43.77 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 86.41 96.56 86.55 97.92 ; + LAYER met4 ; + RECT 63.33 96.56 63.63 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; + RECT 49.61 96.56 49.75 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 96.56 63.09 97.92 ; + RECT 83.19 96.56 83.33 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 96.56 66.77 97.92 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.35 96.56 81.49 97.92 ; + RECT 79.05 96.56 79.19 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.91 96.56 75.05 97.92 ; + RECT 67.09 96.56 67.23 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 44.55 96.56 44.69 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 96.56 51.59 97.92 ; + RECT 60.65 96.56 60.79 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,7 +531,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 85.68 18.01 87.04 ; + RECT 9.13 85.68 9.27 87.04 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,7 +539,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 85.68 12.95 87.04 ; + RECT 6.83 85.68 6.97 87.04 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] @@ -547,7 +547,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 85.68 8.35 87.04 ; + RECT 12.81 85.68 12.95 87.04 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 85.68 12.03 87.04 ; + RECT 27.99 96.56 28.13 97.92 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 85.68 6.51 87.04 ; + RECT 14.19 85.68 14.33 87.04 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 85.68 11.11 87.04 ; + RECT 7.75 85.68 7.89 87.04 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,7 +579,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 85.68 7.43 87.04 ; + RECT 16.03 85.68 16.17 87.04 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] @@ -587,7 +587,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 85.68 5.59 87.04 ; + RECT 28.91 96.56 29.05 97.92 ; END END top_left_grid_pin_49_[0] PIN chanx_right_in[0] @@ -595,7 +595,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 76.69 123.28 76.99 ; + RECT 116.38 73.29 117.76 73.59 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -603,7 +603,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 25.69 123.28 25.99 ; + RECT 116.38 71.93 117.76 72.23 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -611,7 +611,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 13.45 123.28 13.75 ; + RECT 116.38 9.37 117.76 9.67 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -619,7 +619,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 39.29 123.28 39.59 ; + RECT 116.38 21.61 117.76 21.91 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -627,7 +627,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 37.93 123.28 38.23 ; + RECT 116.38 76.01 117.76 76.31 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -635,7 +635,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 40.65 123.28 40.95 ; + RECT 116.38 22.97 117.76 23.27 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -643,7 +643,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 27.05 123.28 27.35 ; + RECT 116.38 42.01 117.76 42.31 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -651,7 +651,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 52.89 123.28 53.19 ; + RECT 116.38 36.57 117.76 36.87 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -659,7 +659,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 75.33 123.28 75.63 ; + RECT 116.38 24.33 117.76 24.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -667,7 +667,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 46.09 123.28 46.39 ; + RECT 116.38 44.73 117.76 45.03 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -675,7 +675,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 44.73 123.28 45.03 ; + RECT 116.38 54.93 117.76 55.23 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -683,7 +683,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 21.61 123.28 21.91 ; + RECT 116.38 31.13 117.76 31.43 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -691,7 +691,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 10.73 123.28 11.03 ; + RECT 116.38 12.09 117.76 12.39 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -699,7 +699,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 70.57 123.28 70.87 ; + RECT 116.38 83.49 117.76 83.79 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -707,7 +707,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 61.73 123.28 62.03 ; + RECT 116.38 77.37 117.76 77.67 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -715,7 +715,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 71.93 123.28 72.23 ; + RECT 116.38 26.37 117.76 26.67 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -723,7 +723,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 22.97 123.28 23.27 ; + RECT 116.38 32.49 117.76 32.79 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -731,7 +731,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 9.37 123.28 9.67 ; + RECT 116.38 10.73 117.76 11.03 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -739,7 +739,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 31.13 123.28 31.43 ; + RECT 116.38 35.21 117.76 35.51 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -747,7 +747,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 28.41 123.28 28.71 ; + RECT 116.38 28.41 117.76 28.71 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_1_[0] @@ -755,7 +755,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 60.37 123.28 60.67 ; + RECT 116.38 74.65 117.76 74.95 ; END END right_bottom_grid_pin_1_[0] PIN right_bottom_grid_pin_3_[0] @@ -763,7 +763,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 56.97 123.28 57.27 ; + RECT 116.38 59.69 117.76 59.99 ; END END right_bottom_grid_pin_3_[0] PIN right_bottom_grid_pin_5_[0] @@ -771,7 +771,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 66.49 123.28 66.79 ; + RECT 116.38 66.49 117.76 66.79 ; END END right_bottom_grid_pin_5_[0] PIN right_bottom_grid_pin_7_[0] @@ -779,7 +779,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 43.37 123.28 43.67 ; + RECT 116.38 50.17 117.76 50.47 ; END END right_bottom_grid_pin_7_[0] PIN right_bottom_grid_pin_9_[0] @@ -787,7 +787,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 69.21 123.28 69.51 ; + RECT 116.38 61.73 117.76 62.03 ; END END right_bottom_grid_pin_9_[0] PIN right_bottom_grid_pin_11_[0] @@ -795,7 +795,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 55.61 123.28 55.91 ; + RECT 116.38 48.81 117.76 49.11 ; END END right_bottom_grid_pin_11_[0] PIN chanx_left_in[0] @@ -803,7 +803,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 11.41 1.38 11.71 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -811,7 +811,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -819,7 +819,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 10.05 1.38 10.35 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -827,7 +827,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -835,7 +835,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -843,7 +843,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -851,7 +851,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -859,7 +859,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 83.49 1.38 83.79 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -867,7 +867,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -875,7 +875,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -883,7 +883,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -891,7 +891,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -899,7 +899,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -907,7 +907,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -915,7 +915,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -923,7 +923,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -931,7 +931,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -939,7 +939,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -947,7 +947,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -955,7 +955,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_1_[0] @@ -963,7 +963,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 63.77 1.38 64.07 ; END END left_bottom_grid_pin_1_[0] PIN left_bottom_grid_pin_3_[0] @@ -971,7 +971,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 31.13 1.38 31.43 ; END END left_bottom_grid_pin_3_[0] PIN left_bottom_grid_pin_5_[0] @@ -979,7 +979,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 43.37 1.38 43.67 ; END END left_bottom_grid_pin_5_[0] PIN left_bottom_grid_pin_7_[0] @@ -987,7 +987,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 54.25 1.38 54.55 ; END END left_bottom_grid_pin_7_[0] PIN left_bottom_grid_pin_9_[0] @@ -995,7 +995,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 61.73 1.38 62.03 ; END END left_bottom_grid_pin_9_[0] PIN left_bottom_grid_pin_11_[0] @@ -1003,7 +1003,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; + RECT 0 37.25 1.38 37.55 ; END END left_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -1011,7 +1011,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 12.09 123.28 12.39 ; + RECT 116.38 13.45 117.76 13.75 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1019,7 +1019,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.59 96.56 55.73 97.92 ; + RECT 79.97 96.56 80.11 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1027,7 +1027,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.51 96.56 79.65 97.92 ; + RECT 62.49 96.56 62.63 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1035,7 +1035,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 96.56 59.87 97.92 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1043,7 +1043,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 96.56 77.81 97.92 ; + RECT 75.37 96.56 75.51 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1051,7 +1051,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 96.56 72.29 97.92 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1059,7 +1059,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 96.56 82.87 97.92 ; + RECT 76.29 96.56 76.43 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1067,7 +1067,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; + RECT 57.43 96.56 57.57 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1075,7 +1075,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 96.56 68.61 97.92 ; + RECT 69.85 96.56 69.99 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1083,7 +1083,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1091,7 +1091,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 96.56 84.71 97.92 ; + RECT 71.23 96.56 71.37 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1099,7 +1099,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; + RECT 61.57 96.56 61.71 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1107,7 +1107,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.85 96.56 69.99 97.92 ; + RECT 64.79 96.56 64.93 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1115,7 +1115,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.49 96.56 85.63 97.92 ; + RECT 84.11 96.56 84.25 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1123,7 +1123,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.79 96.56 87.93 97.92 ; + RECT 68.01 96.56 68.15 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1131,7 +1131,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 96.56 35.03 97.92 ; + RECT 34.43 96.56 34.57 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1139,7 +1139,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.75 96.56 76.89 97.92 ; + RECT 72.61 96.56 72.75 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1147,7 +1147,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 96.56 36.87 97.92 ; + RECT 50.53 96.56 50.67 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1155,7 +1155,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.07 96.56 73.21 97.92 ; + RECT 74.45 96.56 74.59 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1171,7 +1171,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.59 96.56 78.73 97.92 ; + RECT 82.27 96.56 82.41 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1179,7 +1179,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 81.45 123.28 81.75 ; + RECT 116.38 56.97 117.76 57.27 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1187,7 +1187,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 65.13 123.28 65.43 ; + RECT 116.38 67.85 117.76 68.15 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1195,7 +1195,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 80.09 123.28 80.39 ; + RECT 116.38 43.37 117.76 43.67 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1203,7 +1203,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 58.33 123.28 58.63 ; + RECT 116.38 80.09 117.76 80.39 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1211,7 +1211,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 24.33 123.28 24.63 ; + RECT 116.38 33.85 117.76 34.15 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1219,7 +1219,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 63.77 123.28 64.07 ; + RECT 116.38 82.13 117.76 82.43 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1227,7 +1227,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 78.73 123.28 79.03 ; + RECT 116.38 39.29 117.76 39.59 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1235,7 +1235,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 42.01 123.28 42.31 ; + RECT 116.38 53.57 117.76 53.87 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1243,7 +1243,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 54.25 123.28 54.55 ; + RECT 116.38 47.45 117.76 47.75 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1251,7 +1251,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 73.97 123.28 74.27 ; + RECT 116.38 78.73 117.76 79.03 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1259,7 +1259,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 47.45 123.28 47.75 ; + RECT 116.38 46.09 117.76 46.39 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1267,7 +1267,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 82.81 123.28 83.11 ; + RECT 116.38 69.21 117.76 69.51 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1275,7 +1275,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 32.49 123.28 32.79 ; + RECT 116.38 40.65 117.76 40.95 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1283,7 +1283,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 35.21 123.28 35.51 ; + RECT 116.38 37.93 117.76 38.23 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1291,7 +1291,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 33.85 123.28 34.15 ; + RECT 116.38 29.77 117.76 30.07 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1299,7 +1299,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 51.53 123.28 51.83 ; + RECT 116.38 52.21 117.76 52.51 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1307,7 +1307,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 48.81 123.28 49.11 ; + RECT 116.38 58.33 117.76 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1315,7 +1315,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 50.17 123.28 50.47 ; + RECT 116.38 63.09 117.76 63.39 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1323,7 +1323,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 67.85 123.28 68.15 ; + RECT 116.38 70.57 117.76 70.87 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1331,7 +1331,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 29.77 123.28 30.07 ; + RECT 116.38 65.13 117.76 65.43 ; END END chanx_right_out[19] PIN chanx_left_out[0] @@ -1339,7 +1339,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1347,7 +1347,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1355,7 +1355,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1363,7 +1363,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1371,7 +1371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1379,7 +1379,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 82.13 1.38 82.43 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1387,7 +1387,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1395,7 +1395,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1403,7 +1403,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 19.57 1.38 19.87 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1411,7 +1411,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1419,7 +1419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1427,7 +1427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1435,7 +1435,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1443,7 +1443,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1451,7 +1451,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1459,7 +1459,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1467,7 +1467,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1475,7 +1475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 8.69 1.38 8.99 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1483,7 +1483,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1491,7 +1491,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1499,7 +1499,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; + RECT 0 16.85 1.38 17.15 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1507,7 +1507,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 35.89 1.38 36.19 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1515,15 +1515,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 63.33 96.56 63.63 97.92 ; + RECT 58.73 96.56 59.03 97.92 ; END END SC_IN_BOT PIN SC_OUT_TOP DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 61.49 96.56 61.79 97.92 ; + LAYER met2 ; + RECT 54.21 96.56 54.35 97.92 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1531,7 +1531,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 120.91 85.68 121.05 87.04 ; + RECT 115.39 85.68 115.53 87.04 ; END END SC_OUT_BOT PIN VDD @@ -1540,53 +1540,53 @@ MACRO sb_1__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 122.8 2.48 123.28 2.96 ; + RECT 117.28 2.48 117.76 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 122.8 7.92 123.28 8.4 ; + RECT 117.28 7.92 117.76 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 122.8 13.36 123.28 13.84 ; + RECT 117.28 13.36 117.76 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 122.8 18.8 123.28 19.28 ; + RECT 117.28 18.8 117.76 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 122.8 24.24 123.28 24.72 ; + RECT 117.28 24.24 117.76 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 122.8 29.68 123.28 30.16 ; + RECT 117.28 29.68 117.76 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 122.8 35.12 123.28 35.6 ; + RECT 117.28 35.12 117.76 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 122.8 40.56 123.28 41.04 ; + RECT 117.28 40.56 117.76 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 122.8 46 123.28 46.48 ; + RECT 117.28 46 117.76 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 122.8 51.44 123.28 51.92 ; + RECT 117.28 51.44 117.76 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 122.8 56.88 123.28 57.36 ; + RECT 117.28 56.88 117.76 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 122.8 62.32 123.28 62.8 ; + RECT 117.28 62.32 117.76 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 122.8 67.76 123.28 68.24 ; + RECT 117.28 67.76 117.76 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 122.8 73.2 123.28 73.68 ; + RECT 117.28 73.2 117.76 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 122.8 78.64 123.28 79.12 ; + RECT 117.28 78.64 117.76 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 122.8 84.08 123.28 84.56 ; - RECT 27.6 89.52 28.08 90 ; - RECT 95.2 89.52 95.68 90 ; - RECT 27.6 94.96 28.08 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; + RECT 117.28 84.08 117.76 84.56 ; + RECT 25.76 89.52 26.24 90 ; + RECT 91.52 89.52 92 90 ; + RECT 25.76 94.96 26.24 95.44 ; + RECT 91.52 94.96 92 95.44 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 112.86 0 113.46 0.6 ; - RECT 112.86 86.44 113.46 87.04 ; - RECT 39.26 97.32 39.86 97.92 ; - RECT 68.7 97.32 69.3 97.92 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 106.42 0 107.02 0.6 ; + RECT 106.42 86.44 107.02 87.04 ; + RECT 36.5 97.32 37.1 97.92 ; + RECT 65.94 97.32 66.54 97.92 ; LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 120.08 11.32 123.28 14.52 ; + RECT 114.56 11.32 117.76 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 120.08 52.12 123.28 55.32 ; + RECT 114.56 52.12 117.76 55.32 ; END END VDD PIN VSS @@ -1594,53 +1594,53 @@ MACRO sb_1__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 123.28 0.24 ; + RECT 0 0 117.76 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 122.8 5.2 123.28 5.68 ; + RECT 117.28 5.2 117.76 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 122.8 10.64 123.28 11.12 ; + RECT 117.28 10.64 117.76 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 122.8 16.08 123.28 16.56 ; + RECT 117.28 16.08 117.76 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 122.8 21.52 123.28 22 ; + RECT 117.28 21.52 117.76 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 122.8 26.96 123.28 27.44 ; + RECT 117.28 26.96 117.76 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 122.8 32.4 123.28 32.88 ; + RECT 117.28 32.4 117.76 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 122.8 37.84 123.28 38.32 ; + RECT 117.28 37.84 117.76 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 122.8 43.28 123.28 43.76 ; + RECT 117.28 43.28 117.76 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 122.8 48.72 123.28 49.2 ; + RECT 117.28 48.72 117.76 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 122.8 54.16 123.28 54.64 ; + RECT 117.28 54.16 117.76 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 122.8 59.6 123.28 60.08 ; + RECT 117.28 59.6 117.76 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 122.8 65.04 123.28 65.52 ; + RECT 117.28 65.04 117.76 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 122.8 70.48 123.28 70.96 ; + RECT 117.28 70.48 117.76 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 122.8 75.92 123.28 76.4 ; + RECT 117.28 75.92 117.76 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 122.8 81.36 123.28 81.84 ; - RECT 0 86.8 123.28 87.28 ; - RECT 27.6 92.24 28.08 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 27.6 97.68 95.68 97.92 ; + RECT 117.28 81.36 117.76 81.84 ; + RECT 0 86.8 117.76 87.28 ; + RECT 25.76 92.24 26.24 92.72 ; + RECT 91.52 92.24 92 92.72 ; + RECT 25.76 97.68 92 97.92 ; LAYER met4 ; - RECT 9.82 0 10.42 0.6 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 86.44 10.42 87.04 ; - RECT 53.98 97.32 54.58 97.92 ; - RECT 83.42 97.32 84.02 97.92 ; + RECT 10.74 0 11.34 0.6 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 86.44 11.34 87.04 ; + RECT 51.22 97.32 51.82 97.92 ; + RECT 80.66 97.32 81.26 97.92 ; LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 120.08 31.72 123.28 34.92 ; + RECT 114.56 31.72 117.76 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 120.08 72.52 123.28 75.72 ; + RECT 114.56 72.52 117.76 75.72 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] @@ -1656,186 +1656,117 @@ MACRO sb_1__0_ USE CLOCK ; PORT LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; + RECT 55.13 96.56 55.27 97.92 ; END END prog_clk__FEEDTHRU_2[0] - PIN Test_en__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.77 0 70.91 1.36 ; - END - END Test_en__FEEDTHRU_0[0] - PIN Test_en__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 85.68 2.37 87.04 ; - END - END Test_en__FEEDTHRU_1[0] - PIN Test_en__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 119.99 85.68 120.13 87.04 ; - END - END Test_en__FEEDTHRU_2[0] - PIN clk__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; - END - END clk__FEEDTHRU_0[0] - PIN clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 116.31 85.68 116.45 87.04 ; - END - END clk__FEEDTHRU_1[0] - PIN clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; - END - END clk__FEEDTHRU_2[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 85.68 9.27 87.04 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.81 96.56 35.95 97.92 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 27.6 97.835 95.68 98.005 ; - RECT 94.76 95.115 95.68 95.285 ; - RECT 27.6 95.115 31.28 95.285 ; - RECT 94.76 92.395 95.68 92.565 ; - RECT 27.6 92.395 29.44 92.565 ; - RECT 94.76 89.675 95.68 89.845 ; - RECT 27.6 89.675 29.44 89.845 ; - RECT 92.92 86.955 123.28 87.125 ; + RECT 25.76 97.835 92 98.005 ; + RECT 91.54 95.115 92 95.285 ; + RECT 25.76 95.115 29.44 95.285 ; + RECT 91.08 92.395 92 92.565 ; + RECT 25.76 92.395 29.44 92.565 ; + RECT 91.08 89.675 92 89.845 ; + RECT 25.76 89.675 29.44 89.845 ; + RECT 89.24 86.955 117.76 87.125 ; RECT 0 86.955 29.44 87.125 ; - RECT 122.36 84.235 123.28 84.405 ; + RECT 116.84 84.235 117.76 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 122.36 81.515 123.28 81.685 ; + RECT 116.84 81.515 117.76 81.685 ; RECT 0 81.515 1.84 81.685 ; - RECT 122.36 78.795 123.28 78.965 ; + RECT 116.84 78.795 117.76 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 122.36 76.075 123.28 76.245 ; + RECT 116.84 76.075 117.76 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 122.36 73.355 123.28 73.525 ; + RECT 116.84 73.355 117.76 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 122.36 70.635 123.28 70.805 ; + RECT 116.84 70.635 117.76 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 122.36 67.915 123.28 68.085 ; + RECT 116.84 67.915 117.76 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 122.36 65.195 123.28 65.365 ; + RECT 116.84 65.195 117.76 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 122.36 62.475 123.28 62.645 ; + RECT 116.84 62.475 117.76 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 122.36 59.755 123.28 59.925 ; + RECT 116.84 59.755 117.76 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 122.36 57.035 123.28 57.205 ; + RECT 116.84 57.035 117.76 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 122.36 54.315 123.28 54.485 ; + RECT 116.84 54.315 117.76 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 122.36 51.595 123.28 51.765 ; + RECT 116.84 51.595 117.76 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 122.36 48.875 123.28 49.045 ; + RECT 116.84 48.875 117.76 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 122.36 46.155 123.28 46.325 ; + RECT 116.84 46.155 117.76 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 122.36 43.435 123.28 43.605 ; + RECT 116.84 43.435 117.76 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 122.36 40.715 123.28 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 122.36 37.995 123.28 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 122.36 35.275 123.28 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 122.36 32.555 123.28 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 122.36 29.835 123.28 30.005 ; + RECT 116.84 40.715 117.76 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 114.08 37.995 117.76 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 114.08 35.275 117.76 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 116.84 32.555 117.76 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 115.92 29.835 117.76 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 121.44 27.115 123.28 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 121.44 24.395 123.28 24.565 ; + RECT 115.92 27.115 117.76 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 116.84 24.395 117.76 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 122.36 21.675 123.28 21.845 ; + RECT 117.3 21.675 117.76 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 122.82 18.955 123.28 19.125 ; + RECT 117.3 18.955 117.76 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 122.82 16.235 123.28 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 122.82 13.515 123.28 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 122.82 10.795 123.28 10.965 ; + RECT 117.3 16.235 117.76 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 117.3 13.515 117.76 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 117.3 10.795 117.76 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 121.44 8.075 123.28 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 121.44 5.355 123.28 5.525 ; + RECT 117.3 8.075 117.76 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 115.92 5.355 117.76 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 122.82 2.635 123.28 2.805 ; + RECT 115.92 2.635 117.76 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 123.28 0.085 ; + RECT 0 -0.085 117.76 0.085 ; LAYER met2 ; - RECT 83.58 97.735 83.86 98.105 ; - RECT 54.14 97.735 54.42 98.105 ; - RECT 36.21 96.06 36.47 96.38 ; - RECT 9.98 86.855 10.26 87.225 ; - RECT 17.35 85.18 17.61 85.5 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - RECT 9.98 -0.185 10.26 0.185 ; - POLYGON 95.4 97.64 95.4 86.76 116.03 86.76 116.03 85.4 116.73 85.4 116.73 86.76 119.71 86.76 119.71 85.4 120.41 85.4 120.41 86.76 120.63 86.76 120.63 85.4 121.33 85.4 121.33 86.76 123 86.76 123 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 0.28 0.28 0.28 86.76 1.95 86.76 1.95 85.4 2.65 85.4 2.65 86.76 5.17 86.76 5.17 85.4 5.87 85.4 5.87 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 7.93 86.76 7.93 85.4 8.63 85.4 8.63 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 11.61 86.76 11.61 85.4 12.31 85.4 12.31 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 17.59 86.76 17.59 85.4 18.29 85.4 18.29 86.76 27.88 86.76 27.88 97.64 34.61 97.64 34.61 96.28 35.31 96.28 35.31 97.64 35.53 97.64 35.53 96.28 36.23 96.28 36.23 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 55.31 97.64 55.31 96.28 56.01 96.28 56.01 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.53 97.64 58.53 96.28 59.23 96.28 59.23 97.64 59.45 97.64 59.45 96.28 60.15 96.28 60.15 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 71.87 97.64 71.87 96.28 72.57 96.28 72.57 97.64 72.79 97.64 72.79 96.28 73.49 96.28 73.49 97.64 73.71 97.64 73.71 96.28 74.41 96.28 74.41 97.64 74.63 97.64 74.63 96.28 75.33 96.28 75.33 97.64 75.55 97.64 75.55 96.28 76.25 96.28 76.25 97.64 76.47 97.64 76.47 96.28 77.17 96.28 77.17 97.64 77.39 97.64 77.39 96.28 78.09 96.28 78.09 97.64 78.31 97.64 78.31 96.28 79.01 96.28 79.01 97.64 79.23 97.64 79.23 96.28 79.93 96.28 79.93 97.64 80.15 97.64 80.15 96.28 80.85 96.28 80.85 97.64 81.07 97.64 81.07 96.28 81.77 96.28 81.77 97.64 82.45 97.64 82.45 96.28 83.15 96.28 83.15 97.64 84.29 97.64 84.29 96.28 84.99 96.28 84.99 97.64 85.21 97.64 85.21 96.28 85.91 96.28 85.91 97.64 86.13 97.64 86.13 96.28 86.83 96.28 86.83 97.64 87.51 97.64 87.51 96.28 88.21 96.28 88.21 97.64 ; + RECT 80.82 97.735 81.1 98.105 ; + RECT 51.38 97.735 51.66 98.105 ; + POLYGON 74.13 96.63 74.13 96.38 74.19 96.38 74.19 96.06 73.93 96.06 73.93 96.28 73.95 96.28 73.95 96.63 ; + RECT 78.53 96.06 78.79 96.38 ; + RECT 64.27 96.06 64.53 96.38 ; + RECT 55.53 96.06 55.79 96.38 ; + RECT 10.9 86.855 11.18 87.225 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + RECT 10.9 -0.185 11.18 0.185 ; + POLYGON 91.72 97.64 91.72 86.76 115.11 86.76 115.11 85.4 115.81 85.4 115.81 86.76 117.48 86.76 117.48 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 7.47 86.76 7.47 85.4 8.17 85.4 8.17 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 15.75 86.76 15.75 85.4 16.45 85.4 16.45 86.76 26.04 86.76 26.04 97.64 27.71 97.64 27.71 96.28 28.41 96.28 28.41 97.64 28.63 97.64 28.63 96.28 29.33 96.28 29.33 97.64 34.15 97.64 34.15 96.28 34.85 96.28 34.85 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 56.23 97.64 56.23 96.28 56.93 96.28 56.93 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.89 97.64 65.89 96.28 66.59 96.28 66.59 97.64 66.81 97.64 66.81 96.28 67.51 96.28 67.51 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 68.65 97.64 68.65 96.28 69.35 96.28 69.35 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 72.33 97.64 72.33 96.28 73.03 96.28 73.03 97.64 73.25 97.64 73.25 96.28 73.95 96.28 73.95 97.64 74.17 97.64 74.17 96.28 74.87 96.28 74.87 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 76.01 97.64 76.01 96.28 76.71 96.28 76.71 97.64 76.93 97.64 76.93 96.28 77.63 96.28 77.63 97.64 77.85 97.64 77.85 96.28 78.55 96.28 78.55 97.64 78.77 97.64 78.77 96.28 79.47 96.28 79.47 97.64 79.69 97.64 79.69 96.28 80.39 96.28 80.39 97.64 81.99 97.64 81.99 96.28 82.69 96.28 82.69 97.64 82.91 97.64 82.91 96.28 83.61 96.28 83.61 97.64 83.83 97.64 83.83 96.28 84.53 96.28 84.53 97.64 ; LAYER met4 ; - POLYGON 95.28 97.52 95.28 86.64 112.46 86.64 112.46 86.04 113.86 86.04 113.86 86.64 122.88 86.64 122.88 0.4 113.86 0.4 113.86 1 112.46 1 112.46 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 10.82 0.4 10.82 1 9.42 1 9.42 0.4 0.4 0.4 0.4 86.64 9.42 86.64 9.42 86.04 10.82 86.04 10.82 86.64 28 86.64 28 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.69 97.52 65.69 96.16 66.79 96.16 66.79 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; + POLYGON 91.6 97.52 91.6 86.64 106.02 86.64 106.02 86.04 107.42 86.04 107.42 86.64 117.36 86.64 117.36 0.4 107.42 0.4 107.42 1 106.02 1 106.02 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 26.16 86.64 26.16 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 58.33 97.52 58.33 96.16 59.43 96.16 59.43 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 67.53 97.52 67.53 96.16 68.63 96.16 68.63 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; LAYER met3 ; - POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; - POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; - POLYGON 10.285 87.205 10.285 87.2 10.5 87.2 10.5 86.88 10.285 86.88 10.285 86.875 9.955 86.875 9.955 86.88 9.74 86.88 9.74 87.2 9.955 87.2 9.955 87.205 ; - POLYGON 11.65 67.47 11.65 67.17 1.99 67.17 1.99 66.49 1.78 66.49 1.78 67.19 1.69 67.19 1.69 67.47 ; - POLYGON 87.55 64.75 87.55 64.45 1.78 64.45 1.78 64.47 1.23 64.47 1.23 64.75 ; - POLYGON 78.35 56.59 78.35 56.29 1.99 56.29 1.99 55.61 1.78 55.61 1.78 56.31 1.69 56.31 1.69 56.59 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 10.285 0.165 10.285 0.16 10.5 0.16 10.5 -0.16 10.285 -0.16 10.285 -0.165 9.955 -0.165 9.955 -0.16 9.74 -0.16 9.74 0.16 9.955 0.16 9.955 0.165 ; - POLYGON 95.28 97.52 95.28 86.64 122.88 86.64 122.88 83.51 121.5 83.51 121.5 82.41 122.88 82.41 122.88 82.15 121.5 82.15 121.5 81.05 122.88 81.05 122.88 80.79 121.5 80.79 121.5 79.69 122.88 79.69 122.88 79.43 121.5 79.43 121.5 78.33 122.88 78.33 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 72.63 121.5 72.63 121.5 71.53 122.88 71.53 122.88 71.27 121.5 71.27 121.5 70.17 122.88 70.17 122.88 69.91 121.5 69.91 121.5 68.81 122.88 68.81 122.88 68.55 121.5 68.55 121.5 67.45 122.88 67.45 122.88 67.19 121.5 67.19 121.5 66.09 122.88 66.09 122.88 65.83 121.5 65.83 121.5 64.73 122.88 64.73 122.88 64.47 121.5 64.47 121.5 63.37 122.88 63.37 122.88 62.43 121.5 62.43 121.5 61.33 122.88 61.33 122.88 61.07 121.5 61.07 121.5 59.97 122.88 59.97 122.88 59.03 121.5 59.03 121.5 57.93 122.88 57.93 122.88 57.67 121.5 57.67 121.5 56.57 122.88 56.57 122.88 56.31 121.5 56.31 121.5 55.21 122.88 55.21 122.88 54.95 121.5 54.95 121.5 53.85 122.88 53.85 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 52.23 121.5 52.23 121.5 51.13 122.88 51.13 122.88 50.87 121.5 50.87 121.5 49.77 122.88 49.77 122.88 49.51 121.5 49.51 121.5 48.41 122.88 48.41 122.88 48.15 121.5 48.15 121.5 47.05 122.88 47.05 122.88 46.79 121.5 46.79 121.5 45.69 122.88 45.69 122.88 45.43 121.5 45.43 121.5 44.33 122.88 44.33 122.88 44.07 121.5 44.07 121.5 42.97 122.88 42.97 122.88 42.71 121.5 42.71 121.5 41.61 122.88 41.61 122.88 41.35 121.5 41.35 121.5 40.25 122.88 40.25 122.88 39.99 121.5 39.99 121.5 38.89 122.88 38.89 122.88 38.63 121.5 38.63 121.5 37.53 122.88 37.53 122.88 35.91 121.5 35.91 121.5 34.81 122.88 34.81 122.88 34.55 121.5 34.55 121.5 33.45 122.88 33.45 122.88 33.19 121.5 33.19 121.5 32.09 122.88 32.09 122.88 31.83 121.5 31.83 121.5 30.73 122.88 30.73 122.88 30.47 121.5 30.47 121.5 29.37 122.88 29.37 122.88 29.11 121.5 29.11 121.5 28.01 122.88 28.01 122.88 27.75 121.5 27.75 121.5 26.65 122.88 26.65 122.88 26.39 121.5 26.39 121.5 25.29 122.88 25.29 122.88 25.03 121.5 25.03 121.5 23.93 122.88 23.93 122.88 23.67 121.5 23.67 121.5 22.57 122.88 22.57 122.88 22.31 121.5 22.31 121.5 21.21 122.88 21.21 122.88 14.15 121.5 14.15 121.5 13.05 122.88 13.05 122.88 12.79 121.5 12.79 121.5 11.69 122.88 11.69 122.88 11.43 121.5 11.43 121.5 10.33 122.88 10.33 122.88 10.07 121.5 10.07 121.5 8.97 122.88 8.97 122.88 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 28 86.64 28 97.52 ; + POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; + POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; + POLYGON 2.03 78.36 2.03 78.35 5.21 78.35 5.21 78.05 2.03 78.05 2.03 78.04 1.65 78.04 1.65 78.36 ; + POLYGON 2.005 77.005 2.005 77 2.03 77 2.03 76.68 2.005 76.68 2.005 76.675 1.275 76.675 1.275 77.005 ; + RECT 1.69 73.97 2.45 74.27 ; + POLYGON 87.55 23.95 87.55 23.65 1.78 23.65 1.78 23.67 1.23 23.67 1.23 23.95 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ; + POLYGON 91.6 97.52 91.6 86.64 117.36 86.64 117.36 84.19 115.98 84.19 115.98 83.09 117.36 83.09 117.36 82.83 115.98 82.83 115.98 81.73 117.36 81.73 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 79.43 115.98 79.43 115.98 78.33 117.36 78.33 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.71 115.98 76.71 115.98 75.61 117.36 75.61 117.36 75.35 115.98 75.35 115.98 74.25 117.36 74.25 117.36 73.99 115.98 73.99 115.98 72.89 117.36 72.89 117.36 72.63 115.98 72.63 115.98 71.53 117.36 71.53 117.36 71.27 115.98 71.27 115.98 70.17 117.36 70.17 117.36 69.91 115.98 69.91 115.98 68.81 117.36 68.81 117.36 68.55 115.98 68.55 115.98 67.45 117.36 67.45 117.36 67.19 115.98 67.19 115.98 66.09 117.36 66.09 117.36 65.83 115.98 65.83 115.98 64.73 117.36 64.73 117.36 63.79 115.98 63.79 115.98 62.69 117.36 62.69 117.36 62.43 115.98 62.43 115.98 61.33 117.36 61.33 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 55.63 115.98 55.63 115.98 54.53 117.36 54.53 117.36 54.27 115.98 54.27 115.98 53.17 117.36 53.17 117.36 52.91 115.98 52.91 115.98 51.81 117.36 51.81 117.36 50.87 115.98 50.87 115.98 49.77 117.36 49.77 117.36 49.51 115.98 49.51 115.98 48.41 117.36 48.41 117.36 48.15 115.98 48.15 115.98 47.05 117.36 47.05 117.36 46.79 115.98 46.79 115.98 45.69 117.36 45.69 117.36 45.43 115.98 45.43 115.98 44.33 117.36 44.33 117.36 44.07 115.98 44.07 115.98 42.97 117.36 42.97 117.36 42.71 115.98 42.71 115.98 41.61 117.36 41.61 117.36 41.35 115.98 41.35 115.98 40.25 117.36 40.25 117.36 39.99 115.98 39.99 115.98 38.89 117.36 38.89 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 33.19 115.98 33.19 115.98 32.09 117.36 32.09 117.36 31.83 115.98 31.83 115.98 30.73 117.36 30.73 117.36 30.47 115.98 30.47 115.98 29.37 117.36 29.37 117.36 29.11 115.98 29.11 115.98 28.01 117.36 28.01 117.36 27.07 115.98 27.07 115.98 25.97 117.36 25.97 117.36 25.03 115.98 25.03 115.98 23.93 117.36 23.93 117.36 23.67 115.98 23.67 115.98 22.57 117.36 22.57 117.36 22.31 115.98 22.31 115.98 21.21 117.36 21.21 117.36 14.15 115.98 14.15 115.98 13.05 117.36 13.05 117.36 12.79 115.98 12.79 115.98 11.69 117.36 11.69 117.36 11.43 115.98 11.43 115.98 10.33 117.36 10.33 117.36 10.07 115.98 10.07 115.98 8.97 117.36 8.97 117.36 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 26.16 86.64 26.16 97.52 ; LAYER met5 ; - POLYGON 94.08 96.32 94.08 85.44 121.68 85.44 121.68 77.32 118.48 77.32 118.48 70.92 121.68 70.92 121.68 56.92 118.48 56.92 118.48 50.52 121.68 50.52 121.68 36.52 118.48 36.52 118.48 30.12 121.68 30.12 121.68 16.12 118.48 16.12 118.48 9.72 121.68 9.72 121.68 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 29.2 85.44 29.2 96.32 ; + POLYGON 90.4 96.32 90.4 85.44 116.16 85.44 116.16 77.32 112.96 77.32 112.96 70.92 116.16 70.92 116.16 56.92 112.96 56.92 112.96 50.52 116.16 50.52 116.16 36.52 112.96 36.52 112.96 30.12 116.16 30.12 116.16 16.12 112.96 16.12 112.96 9.72 116.16 9.72 116.16 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; LAYER met1 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 27.88 87.56 27.88 89.24 28.36 89.24 28.36 90.28 27.88 90.28 27.88 91.96 28.36 91.96 28.36 93 27.88 93 27.88 94.68 28.36 94.68 28.36 95.72 27.88 95.72 27.88 97.4 ; - POLYGON 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 122.52 11.4 122.52 10.36 123 10.36 123 8.68 122.52 8.68 122.52 7.64 123 7.64 123 5.96 122.52 5.96 122.52 4.92 123 4.92 123 3.24 122.52 3.24 122.52 2.2 123 2.2 123 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 ; + POLYGON 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 117 11.4 117 10.36 117.48 10.36 117.48 8.68 117 8.68 117 7.64 117.48 7.64 117.48 5.96 117 5.96 117 4.92 117.48 4.92 117.48 3.24 117 3.24 117 2.2 117.48 2.2 117.48 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 95.51 97.75 95.51 86.87 123.11 86.87 123.11 0.17 0.17 0.17 0.17 86.87 27.77 86.87 27.77 97.75 ; + POLYGON 91.83 97.75 91.83 86.87 117.59 86.87 117.59 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; LAYER mcon ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -1976,30 +1907,22 @@ MACRO sb_1__0_ RECT 28.665 97.835 28.835 98.005 ; RECT 28.205 97.835 28.375 98.005 ; RECT 27.745 97.835 27.915 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; - RECT 28.205 95.115 28.375 95.285 ; - RECT 27.745 95.115 27.915 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; - RECT 28.205 92.395 28.375 92.565 ; - RECT 27.745 92.395 27.915 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; - RECT 28.205 89.675 28.375 89.845 ; - RECT 27.745 89.675 27.915 89.845 ; - RECT 122.965 86.955 123.135 87.125 ; - RECT 122.505 86.955 122.675 87.125 ; - RECT 122.045 86.955 122.215 87.125 ; - RECT 121.585 86.955 121.755 87.125 ; - RECT 121.125 86.955 121.295 87.125 ; - RECT 120.665 86.955 120.835 87.125 ; - RECT 120.205 86.955 120.375 87.125 ; - RECT 119.745 86.955 119.915 87.125 ; - RECT 119.285 86.955 119.455 87.125 ; - RECT 118.825 86.955 118.995 87.125 ; - RECT 118.365 86.955 118.535 87.125 ; - RECT 117.905 86.955 118.075 87.125 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; + RECT 26.365 95.115 26.535 95.285 ; + RECT 25.905 95.115 26.075 95.285 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; + RECT 26.365 92.395 26.535 92.565 ; + RECT 25.905 92.395 26.075 92.565 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; + RECT 26.365 89.675 26.535 89.845 ; + RECT 25.905 89.675 26.075 89.845 ; RECT 117.445 86.955 117.615 87.125 ; RECT 116.985 86.955 117.155 87.125 ; RECT 116.525 86.955 116.695 87.125 ; @@ -2256,142 +2179,130 @@ MACRO sb_1__0_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 122.965 84.235 123.135 84.405 ; - RECT 122.505 84.235 122.675 84.405 ; + RECT 117.445 84.235 117.615 84.405 ; + RECT 116.985 84.235 117.155 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 122.965 81.515 123.135 81.685 ; - RECT 122.505 81.515 122.675 81.685 ; + RECT 117.445 81.515 117.615 81.685 ; + RECT 116.985 81.515 117.155 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 122.965 78.795 123.135 78.965 ; - RECT 122.505 78.795 122.675 78.965 ; + RECT 117.445 78.795 117.615 78.965 ; + RECT 116.985 78.795 117.155 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 122.965 76.075 123.135 76.245 ; - RECT 122.505 76.075 122.675 76.245 ; + RECT 117.445 76.075 117.615 76.245 ; + RECT 116.985 76.075 117.155 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 122.965 73.355 123.135 73.525 ; - RECT 122.505 73.355 122.675 73.525 ; + RECT 117.445 73.355 117.615 73.525 ; + RECT 116.985 73.355 117.155 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 122.965 70.635 123.135 70.805 ; - RECT 122.505 70.635 122.675 70.805 ; + RECT 117.445 70.635 117.615 70.805 ; + RECT 116.985 70.635 117.155 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 122.965 67.915 123.135 68.085 ; - RECT 122.505 67.915 122.675 68.085 ; + RECT 117.445 67.915 117.615 68.085 ; + RECT 116.985 67.915 117.155 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 122.965 65.195 123.135 65.365 ; - RECT 122.505 65.195 122.675 65.365 ; + RECT 117.445 65.195 117.615 65.365 ; + RECT 116.985 65.195 117.155 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 122.965 62.475 123.135 62.645 ; - RECT 122.505 62.475 122.675 62.645 ; + RECT 117.445 62.475 117.615 62.645 ; + RECT 116.985 62.475 117.155 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 122.965 59.755 123.135 59.925 ; - RECT 122.505 59.755 122.675 59.925 ; + RECT 117.445 59.755 117.615 59.925 ; + RECT 116.985 59.755 117.155 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 122.965 57.035 123.135 57.205 ; - RECT 122.505 57.035 122.675 57.205 ; + RECT 117.445 57.035 117.615 57.205 ; + RECT 116.985 57.035 117.155 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 122.965 54.315 123.135 54.485 ; - RECT 122.505 54.315 122.675 54.485 ; + RECT 117.445 54.315 117.615 54.485 ; + RECT 116.985 54.315 117.155 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 122.965 51.595 123.135 51.765 ; - RECT 122.505 51.595 122.675 51.765 ; + RECT 117.445 51.595 117.615 51.765 ; + RECT 116.985 51.595 117.155 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 122.965 48.875 123.135 49.045 ; - RECT 122.505 48.875 122.675 49.045 ; + RECT 117.445 48.875 117.615 49.045 ; + RECT 116.985 48.875 117.155 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 122.965 46.155 123.135 46.325 ; - RECT 122.505 46.155 122.675 46.325 ; + RECT 117.445 46.155 117.615 46.325 ; + RECT 116.985 46.155 117.155 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 122.965 43.435 123.135 43.605 ; - RECT 122.505 43.435 122.675 43.605 ; + RECT 117.445 43.435 117.615 43.605 ; + RECT 116.985 43.435 117.155 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 122.965 40.715 123.135 40.885 ; - RECT 122.505 40.715 122.675 40.885 ; + RECT 117.445 40.715 117.615 40.885 ; + RECT 116.985 40.715 117.155 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 122.965 37.995 123.135 38.165 ; - RECT 122.505 37.995 122.675 38.165 ; + RECT 117.445 37.995 117.615 38.165 ; + RECT 116.985 37.995 117.155 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 122.965 35.275 123.135 35.445 ; - RECT 122.505 35.275 122.675 35.445 ; + RECT 117.445 35.275 117.615 35.445 ; + RECT 116.985 35.275 117.155 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 122.965 32.555 123.135 32.725 ; - RECT 122.505 32.555 122.675 32.725 ; + RECT 117.445 32.555 117.615 32.725 ; + RECT 116.985 32.555 117.155 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 122.965 29.835 123.135 30.005 ; - RECT 122.505 29.835 122.675 30.005 ; + RECT 117.445 29.835 117.615 30.005 ; + RECT 116.985 29.835 117.155 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 122.965 27.115 123.135 27.285 ; - RECT 122.505 27.115 122.675 27.285 ; + RECT 117.445 27.115 117.615 27.285 ; + RECT 116.985 27.115 117.155 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 122.965 24.395 123.135 24.565 ; - RECT 122.505 24.395 122.675 24.565 ; + RECT 117.445 24.395 117.615 24.565 ; + RECT 116.985 24.395 117.155 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 122.965 21.675 123.135 21.845 ; - RECT 122.505 21.675 122.675 21.845 ; + RECT 117.445 21.675 117.615 21.845 ; + RECT 116.985 21.675 117.155 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 122.965 18.955 123.135 19.125 ; - RECT 122.505 18.955 122.675 19.125 ; + RECT 117.445 18.955 117.615 19.125 ; + RECT 116.985 18.955 117.155 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 122.965 16.235 123.135 16.405 ; - RECT 122.505 16.235 122.675 16.405 ; + RECT 117.445 16.235 117.615 16.405 ; + RECT 116.985 16.235 117.155 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 122.965 13.515 123.135 13.685 ; - RECT 122.505 13.515 122.675 13.685 ; + RECT 117.445 13.515 117.615 13.685 ; + RECT 116.985 13.515 117.155 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 122.965 10.795 123.135 10.965 ; - RECT 122.505 10.795 122.675 10.965 ; + RECT 117.445 10.795 117.615 10.965 ; + RECT 116.985 10.795 117.155 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 122.965 8.075 123.135 8.245 ; - RECT 122.505 8.075 122.675 8.245 ; + RECT 117.445 8.075 117.615 8.245 ; + RECT 116.985 8.075 117.155 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 122.965 5.355 123.135 5.525 ; - RECT 122.505 5.355 122.675 5.525 ; + RECT 117.445 5.355 117.615 5.525 ; + RECT 116.985 5.355 117.155 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 122.965 2.635 123.135 2.805 ; - RECT 122.505 2.635 122.675 2.805 ; + RECT 117.445 2.635 117.615 2.805 ; + RECT 116.985 2.635 117.155 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 122.965 -0.085 123.135 0.085 ; - RECT 122.505 -0.085 122.675 0.085 ; - RECT 122.045 -0.085 122.215 0.085 ; - RECT 121.585 -0.085 121.755 0.085 ; - RECT 121.125 -0.085 121.295 0.085 ; - RECT 120.665 -0.085 120.835 0.085 ; - RECT 120.205 -0.085 120.375 0.085 ; - RECT 119.745 -0.085 119.915 0.085 ; - RECT 119.285 -0.085 119.455 0.085 ; - RECT 118.825 -0.085 118.995 0.085 ; - RECT 118.365 -0.085 118.535 0.085 ; - RECT 117.905 -0.085 118.075 0.085 ; RECT 117.445 -0.085 117.615 0.085 ; RECT 116.985 -0.085 117.155 0.085 ; RECT 116.525 -0.085 116.695 0.085 ; @@ -2649,48 +2560,46 @@ MACRO sb_1__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 63.865 96.145 64.015 96.295 ; - RECT 83.645 86.965 83.795 87.115 ; - RECT 54.205 86.965 54.355 87.115 ; - RECT 10.045 86.965 10.195 87.115 ; - RECT 119.985 85.265 120.135 85.415 ; - RECT 17.865 85.265 18.015 85.415 ; - RECT 5.445 85.265 5.595 85.415 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; - RECT 10.045 -0.075 10.195 0.075 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 53.285 96.145 53.435 96.295 ; + RECT 47.305 96.145 47.455 96.295 ; + RECT 27.985 96.145 28.135 96.295 ; + RECT 80.885 86.965 81.035 87.115 ; + RECT 51.445 86.965 51.595 87.115 ; + RECT 10.965 86.965 11.115 87.115 ; + RECT 14.185 85.265 14.335 85.415 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; + RECT 10.965 -0.075 11.115 0.075 ; LAYER via2 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 86.94 10.22 87.14 ; - RECT 1.28 82.86 1.48 83.06 ; - RECT 1.74 75.38 1.94 75.58 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 86.94 11.14 87.14 ; + RECT 1.74 82.18 1.94 82.38 ; RECT 1.28 65.18 1.48 65.38 ; - RECT 121.8 48.86 122 49.06 ; - RECT 1.74 46.14 1.94 46.34 ; - RECT 121.8 43.42 122 43.62 ; - RECT 121.34 35.26 121.54 35.46 ; - RECT 121.8 31.18 122 31.38 ; - RECT 1.74 28.46 1.94 28.66 ; - RECT 121.8 23.02 122 23.22 ; - RECT 1.28 20.3 1.48 20.5 ; - RECT 1.74 11.46 1.94 11.66 ; - RECT 121.8 10.78 122 10.98 ; - RECT 121.8 9.42 122 9.62 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; - RECT 10.02 -0.1 10.22 0.1 ; + RECT 1.74 58.38 1.94 58.58 ; + RECT 1.28 52.26 1.48 52.46 ; + RECT 1.74 49.54 1.94 49.74 ; + RECT 116.28 48.86 116.48 49.06 ; + RECT 116.28 39.34 116.48 39.54 ; + RECT 116.28 29.82 116.48 30.02 ; + RECT 116.28 23.02 116.48 23.22 ; + RECT 1.28 19.62 1.48 19.82 ; + RECT 1.28 16.9 1.48 17.1 ; + RECT 1.28 15.54 1.48 15.74 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; + RECT 10.94 -0.1 11.14 0.1 ; LAYER via3 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 86.94 10.22 87.14 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; - RECT 10.02 -0.1 10.22 0.1 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 86.94 11.14 87.14 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; + RECT 10.94 -0.1 11.14 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 87.04 27.6 87.04 27.6 97.92 95.68 97.92 95.68 87.04 123.28 87.04 123.28 0 ; + POLYGON 0 0 0 87.04 25.76 87.04 25.76 97.92 92 97.92 92 87.04 117.76 87.04 117.76 0 ; END END sb_1__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef index 4cec805..f33057f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 123.28 BY 108.8 ; + SIZE 117.76 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 55.59 0 55.73 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 107.44 67.69 108.8 ; + RECT 63.87 107.44 64.01 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,15 +379,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 107.44 47.45 108.8 ; + RECT 59.27 107.44 59.41 108.8 ; END END chany_top_in[1] PIN chany_top_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 65.71 107.44 65.85 108.8 ; + LAYER met4 ; + RECT 67.93 107.44 68.23 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 107.44 80.57 108.8 ; + RECT 78.13 107.44 78.27 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 107.44 60.79 108.8 ; + RECT 58.35 107.44 58.49 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.99 107.44 74.13 108.8 ; + RECT 68.93 107.44 69.07 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 107.44 58.95 108.8 ; + RECT 46.39 107.44 46.53 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.83 107.44 75.97 108.8 ; + RECT 73.53 107.44 73.67 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 107.44 52.51 108.8 ; + RECT 56.51 107.44 56.65 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,15 +443,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 107.44 71.37 108.8 ; + RECT 77.21 107.44 77.35 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 66.09 107.44 66.39 108.8 ; + LAYER met2 ; + RECT 66.17 107.44 66.31 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,15 +459,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 107.44 50.67 108.8 ; + RECT 43.63 107.44 43.77 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 86.41 107.44 86.55 108.8 ; + LAYER met4 ; + RECT 63.33 107.44 63.63 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 107.44 62.17 108.8 ; + RECT 49.61 107.44 49.75 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 107.44 63.09 108.8 ; + RECT 83.19 107.44 83.33 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 107.44 66.77 108.8 ; + RECT 45.47 107.44 45.61 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.35 107.44 81.49 108.8 ; + RECT 79.05 107.44 79.19 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.91 107.44 75.05 108.8 ; + RECT 67.09 107.44 67.23 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 107.44 48.37 108.8 ; + RECT 44.55 107.44 44.69 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 107.44 51.59 108.8 ; + RECT 60.65 107.44 60.79 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,7 +531,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 96.56 18.01 97.92 ; + RECT 9.13 96.56 9.27 97.92 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,7 +539,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 96.56 12.95 97.92 ; + RECT 6.83 96.56 6.97 97.92 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] @@ -547,7 +547,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 96.56 8.35 97.92 ; + RECT 12.81 96.56 12.95 97.92 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 96.56 12.03 97.92 ; + RECT 27.99 107.44 28.13 108.8 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 96.56 6.51 97.92 ; + RECT 14.19 96.56 14.33 97.92 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 96.56 11.11 97.92 ; + RECT 7.75 96.56 7.89 97.92 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,7 +579,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 96.56 7.43 97.92 ; + RECT 16.03 96.56 16.17 97.92 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] @@ -587,7 +587,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 96.56 5.59 97.92 ; + RECT 28.91 107.44 29.05 108.8 ; END END top_left_grid_pin_49_[0] PIN chanx_right_in[0] @@ -595,7 +595,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 37.25 123.28 37.55 ; + RECT 116.38 66.49 117.76 66.79 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -603,7 +603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 71.25 123.28 71.55 ; + RECT 116.38 82.81 117.76 83.11 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -611,7 +611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 92.33 123.28 92.63 ; + RECT 116.38 92.33 117.76 92.63 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -619,7 +619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 84.85 123.28 85.15 ; + RECT 116.38 36.57 117.76 36.87 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -627,7 +627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 73.97 123.28 74.27 ; + RECT 116.38 74.65 117.76 74.95 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -635,7 +635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 76.69 123.28 76.99 ; + RECT 116.38 77.37 117.76 77.67 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -643,7 +643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 67.17 123.28 67.47 ; + RECT 116.38 33.85 117.76 34.15 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -651,7 +651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 39.97 123.28 40.27 ; + RECT 116.38 46.09 117.76 46.39 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -659,7 +659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 55.61 123.28 55.91 ; + RECT 116.38 56.97 117.76 57.27 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -667,7 +667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 75.33 123.28 75.63 ; + RECT 116.38 73.29 117.76 73.59 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -675,7 +675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 59.69 123.28 59.99 ; + RECT 116.38 84.17 117.76 84.47 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -683,7 +683,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 72.61 123.28 72.91 ; + RECT 116.38 90.97 117.76 91.27 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -691,7 +691,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 78.05 123.28 78.35 ; + RECT 116.38 81.45 117.76 81.75 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -699,7 +699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 35.89 123.28 36.19 ; + RECT 116.38 44.73 117.76 45.03 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -707,7 +707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 31.81 123.28 32.11 ; + RECT 116.38 31.81 117.76 32.11 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -715,7 +715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 41.33 123.28 41.63 ; + RECT 116.38 61.73 117.76 62.03 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -723,7 +723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 89.61 123.28 89.91 ; + RECT 116.38 65.13 117.76 65.43 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -731,7 +731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 44.05 123.28 44.35 ; + RECT 116.38 48.81 117.76 49.11 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -739,7 +739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 80.77 123.28 81.07 ; + RECT 116.38 69.21 117.76 69.51 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -747,7 +747,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 38.61 123.28 38.91 ; + RECT 116.38 89.61 117.76 89.91 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_34_[0] @@ -755,7 +755,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 114.93 10.88 115.07 12.24 ; + RECT 109.41 10.88 109.55 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -763,7 +763,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 115.85 10.88 115.99 12.24 ; + RECT 111.71 10.88 111.85 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] @@ -771,7 +771,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 109.87 10.88 110.01 12.24 ; + RECT 114.01 10.88 114.15 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -779,7 +779,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 112.63 10.88 112.77 12.24 ; + RECT 108.49 10.88 108.63 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -787,7 +787,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 118.61 10.88 118.75 12.24 ; + RECT 110.79 10.88 110.93 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -795,7 +795,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 116.77 10.88 116.91 12.24 ; + RECT 113.09 10.88 113.23 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -803,7 +803,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 117.69 10.88 117.83 12.24 ; + RECT 101.59 10.88 101.73 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -811,7 +811,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 114.01 10.88 114.15 12.24 ; + RECT 106.19 10.88 106.33 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -819,7 +819,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -827,7 +827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 68.93 0 69.07 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -835,7 +835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 0 80.57 1.36 ; + RECT 79.05 0 79.19 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -843,7 +843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 69.85 0 69.99 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -851,7 +851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -859,7 +859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 0 64.47 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -867,7 +867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -875,7 +875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -883,7 +883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -891,7 +891,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -899,7 +899,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 68.01 0 68.15 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -907,7 +907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; + RECT 70.77 0 70.91 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -915,7 +915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -923,7 +923,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -931,7 +931,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.35 0 81.49 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -939,7 +939,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -947,7 +947,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -955,7 +955,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 0 63.55 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -963,7 +963,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -971,23 +971,23 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.59 0 78.73 1.36 ; + RECT 72.61 0 72.75 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 11.43 10.88 11.57 12.24 ; + LAYER met4 ; + RECT 12.73 10.88 13.03 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; + LAYER met4 ; + RECT 9.05 10.88 9.35 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -995,7 +995,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.35 10.88 12.49 12.24 ; + RECT 27.99 0 28.13 1.36 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -1003,7 +1003,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 10.88 14.33 12.24 ; + RECT 7.29 10.88 7.43 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -1011,7 +1011,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] @@ -1019,23 +1019,23 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 10.88 18.01 12.24 ; + RECT 15.11 10.88 15.25 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 10.88 5.67 12.24 ; + LAYER met2 ; + RECT 8.21 10.88 8.35 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 11.81 10.88 12.11 12.24 ; + LAYER met2 ; + RECT 10.05 10.88 10.19 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -1043,7 +1043,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -1051,7 +1051,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 84.17 1.38 84.47 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -1067,7 +1067,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -1075,7 +1075,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -1083,7 +1083,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -1091,7 +1091,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 90.97 1.38 91.27 ; + RECT 0 89.61 1.38 89.91 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -1099,7 +1099,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -1107,7 +1107,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -1115,7 +1115,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 84.17 1.38 84.47 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -1123,7 +1123,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 88.25 1.38 88.55 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -1131,7 +1131,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 86.89 1.38 87.19 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -1139,7 +1139,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 92.33 1.38 92.63 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -1147,7 +1147,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -1155,7 +1155,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 86.89 1.38 87.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -1163,7 +1163,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -1171,7 +1171,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -1179,7 +1179,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -1187,7 +1187,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -1195,7 +1195,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_34_[0] @@ -1203,7 +1203,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; + RECT 28.91 0 29.05 1.36 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] @@ -1211,7 +1211,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 10.88 13.41 12.24 ; + RECT 12.81 10.88 12.95 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -1227,7 +1227,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 10.88 6.05 12.24 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1235,15 +1235,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 10.88 7.89 12.24 ; + RECT 6.37 10.88 6.51 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; + LAYER met4 ; + RECT 4.45 10.88 4.75 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -1251,7 +1251,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; + RECT 11.89 10.88 12.03 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1259,7 +1259,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 10.88 6.97 12.24 ; + RECT 16.03 10.88 16.17 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1267,7 +1267,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 86.89 123.28 87.19 ; + RECT 116.38 43.37 117.76 43.67 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1275,7 +1275,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.59 107.44 55.73 108.8 ; + RECT 79.97 107.44 80.11 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1283,7 +1283,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.51 107.44 79.65 108.8 ; + RECT 62.49 107.44 62.63 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1291,7 +1291,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 107.44 59.87 108.8 ; + RECT 47.31 107.44 47.45 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1299,7 +1299,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 107.44 77.81 108.8 ; + RECT 75.37 107.44 75.51 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1307,7 +1307,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 107.44 72.29 108.8 ; + RECT 52.37 107.44 52.51 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1315,7 +1315,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 107.44 82.87 108.8 ; + RECT 76.29 107.44 76.43 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1323,7 +1323,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 107.44 64.01 108.8 ; + RECT 57.43 107.44 57.57 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1331,7 +1331,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 107.44 68.61 108.8 ; + RECT 69.85 107.44 69.99 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1339,7 +1339,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 107.44 49.29 108.8 ; + RECT 48.23 107.44 48.37 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1347,7 +1347,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 107.44 84.71 108.8 ; + RECT 71.23 107.44 71.37 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1355,7 +1355,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 107.44 64.93 108.8 ; + RECT 61.57 107.44 61.71 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1363,7 +1363,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.85 107.44 69.99 108.8 ; + RECT 64.79 107.44 64.93 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1371,7 +1371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.49 107.44 85.63 108.8 ; + RECT 84.11 107.44 84.25 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1379,7 +1379,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.79 107.44 87.93 108.8 ; + RECT 68.01 107.44 68.15 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1387,7 +1387,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 107.44 35.03 108.8 ; + RECT 34.43 107.44 34.57 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1395,7 +1395,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.75 107.44 76.89 108.8 ; + RECT 72.61 107.44 72.75 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1403,7 +1403,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 107.44 36.87 108.8 ; + RECT 50.53 107.44 50.67 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1411,7 +1411,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.07 107.44 73.21 108.8 ; + RECT 74.45 107.44 74.59 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1427,7 +1427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.59 107.44 78.73 108.8 ; + RECT 82.27 107.44 82.41 108.8 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1435,7 +1435,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 83.49 123.28 83.79 ; + RECT 116.38 70.57 117.76 70.87 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1443,7 +1443,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 90.97 123.28 91.27 ; + RECT 116.38 55.61 117.76 55.91 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1451,7 +1451,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 48.13 123.28 48.43 ; + RECT 116.38 71.93 117.76 72.23 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1459,7 +1459,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 61.05 123.28 61.35 ; + RECT 116.38 54.25 117.76 54.55 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1467,7 +1467,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 82.13 123.28 82.43 ; + RECT 116.38 37.93 117.76 38.23 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1475,7 +1475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 79.41 123.28 79.71 ; + RECT 116.38 80.09 117.76 80.39 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1483,7 +1483,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 54.25 123.28 54.55 ; + RECT 116.38 50.17 117.76 50.47 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1491,7 +1491,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 64.45 123.28 64.75 ; + RECT 116.38 63.77 117.76 64.07 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1499,7 +1499,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 56.97 123.28 57.27 ; + RECT 116.38 42.01 117.76 42.31 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1507,7 +1507,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 50.85 123.28 51.15 ; + RECT 116.38 51.53 117.76 51.83 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1515,7 +1515,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 49.49 123.28 49.79 ; + RECT 116.38 52.89 117.76 53.19 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1523,7 +1523,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 65.81 123.28 66.11 ; + RECT 116.38 39.29 117.76 39.59 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1531,7 +1531,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 45.41 123.28 45.71 ; + RECT 116.38 78.73 117.76 79.03 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1539,7 +1539,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 88.25 123.28 88.55 ; + RECT 116.38 67.85 117.76 68.15 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1547,7 +1547,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 46.77 123.28 47.07 ; + RECT 116.38 35.21 117.76 35.51 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1555,7 +1555,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 42.69 123.28 42.99 ; + RECT 116.38 40.65 117.76 40.95 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1563,7 +1563,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 58.33 123.28 58.63 ; + RECT 116.38 58.33 117.76 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1571,7 +1571,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 52.89 123.28 53.19 ; + RECT 116.38 47.45 117.76 47.75 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1579,7 +1579,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 62.41 123.28 62.71 ; + RECT 116.38 59.69 117.76 59.99 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1587,7 +1587,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 69.21 123.28 69.51 ; + RECT 116.38 76.01 117.76 76.31 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1595,7 +1595,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1603,7 +1603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 45.01 0 45.15 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1611,7 +1611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1619,7 +1619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.51 0 79.65 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1627,7 +1627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1635,7 +1635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.79 0 87.93 1.36 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1643,7 +1643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1651,7 +1651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 0 77.81 1.36 ; + RECT 73.53 0 73.67 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1659,7 +1659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.49 0 85.63 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1667,7 +1667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.07 0 73.21 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1675,7 +1675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1683,7 +1683,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.75 0 76.89 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1691,7 +1691,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 79.97 0 80.11 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1699,7 +1699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 88.71 0 88.85 1.36 ; + RECT 76.29 0 76.43 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1707,7 +1707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1715,7 +1715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 89.63 0 89.77 1.36 ; + RECT 88.25 0 88.39 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1723,7 +1723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 0 84.71 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1731,7 +1731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 87.33 0 87.47 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1739,7 +1739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1747,7 +1747,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 90.55 0 90.69 1.36 ; + RECT 89.17 0 89.31 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1755,7 +1755,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1763,7 +1763,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1771,7 +1771,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1779,7 +1779,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.17 1.38 67.47 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1787,7 +1787,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1795,7 +1795,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 88.25 1.38 88.55 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1803,7 +1803,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1811,7 +1811,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1819,7 +1819,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1827,7 +1827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1835,7 +1835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1843,7 +1843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1851,7 +1851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1859,7 +1859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 90.97 1.38 91.27 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1867,7 +1867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1875,7 +1875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1883,7 +1883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1891,7 +1891,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1899,7 +1899,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1907,7 +1907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1915,7 +1915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; + RECT 0 76.69 1.38 76.99 ; END END ccff_tail[0] PIN VDD @@ -1923,58 +1923,58 @@ MACRO sb_1__1_ USE POWER ; PORT LAYER met1 ; - RECT 27.6 2.48 28.08 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; - RECT 27.6 7.92 28.08 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 25.76 2.48 26.24 2.96 ; + RECT 91.52 2.48 92 2.96 ; + RECT 25.76 7.92 26.24 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 122.8 13.36 123.28 13.84 ; + RECT 117.28 13.36 117.76 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 122.8 18.8 123.28 19.28 ; + RECT 117.28 18.8 117.76 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 122.8 24.24 123.28 24.72 ; + RECT 117.28 24.24 117.76 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 122.8 29.68 123.28 30.16 ; + RECT 117.28 29.68 117.76 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 122.8 35.12 123.28 35.6 ; + RECT 117.28 35.12 117.76 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 122.8 40.56 123.28 41.04 ; + RECT 117.28 40.56 117.76 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 122.8 46 123.28 46.48 ; + RECT 117.28 46 117.76 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 122.8 51.44 123.28 51.92 ; + RECT 117.28 51.44 117.76 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 122.8 56.88 123.28 57.36 ; + RECT 117.28 56.88 117.76 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 122.8 62.32 123.28 62.8 ; + RECT 117.28 62.32 117.76 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 122.8 67.76 123.28 68.24 ; + RECT 117.28 67.76 117.76 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 122.8 73.2 123.28 73.68 ; + RECT 117.28 73.2 117.76 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 122.8 78.64 123.28 79.12 ; + RECT 117.28 78.64 117.76 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 122.8 84.08 123.28 84.56 ; + RECT 117.28 84.08 117.76 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 122.8 89.52 123.28 90 ; + RECT 117.28 89.52 117.76 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 122.8 94.96 123.28 95.44 ; - RECT 27.6 100.4 28.08 100.88 ; - RECT 95.2 100.4 95.68 100.88 ; - RECT 27.6 105.84 28.08 106.32 ; - RECT 95.2 105.84 95.68 106.32 ; + RECT 117.28 94.96 117.76 95.44 ; + RECT 25.76 100.4 26.24 100.88 ; + RECT 91.52 100.4 92 100.88 ; + RECT 25.76 105.84 26.24 106.32 ; + RECT 91.52 105.84 92 106.32 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 112.86 10.88 113.46 11.48 ; - RECT 112.86 97.32 113.46 97.92 ; - RECT 39.26 108.2 39.86 108.8 ; - RECT 68.7 108.2 69.3 108.8 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 106.42 10.88 107.02 11.48 ; + RECT 106.42 97.32 107.02 97.92 ; + RECT 36.5 108.2 37.1 108.8 ; + RECT 65.94 108.2 66.54 108.8 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 120.08 22.2 123.28 25.4 ; + RECT 114.56 22.2 117.76 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 120.08 63 123.28 66.2 ; + RECT 114.56 63 117.76 66.2 ; END END VDD PIN VSS @@ -1982,56 +1982,56 @@ MACRO sb_1__1_ USE GROUND ; PORT LAYER met1 ; - RECT 27.6 0 95.68 0.24 ; - RECT 27.6 5.2 28.08 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; - RECT 0 10.64 123.28 11.12 ; + RECT 25.76 0 92 0.24 ; + RECT 25.76 5.2 26.24 5.68 ; + RECT 91.52 5.2 92 5.68 ; + RECT 0 10.64 117.76 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 122.8 16.08 123.28 16.56 ; + RECT 117.28 16.08 117.76 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 122.8 21.52 123.28 22 ; + RECT 117.28 21.52 117.76 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 122.8 26.96 123.28 27.44 ; + RECT 117.28 26.96 117.76 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 122.8 32.4 123.28 32.88 ; + RECT 117.28 32.4 117.76 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 122.8 37.84 123.28 38.32 ; + RECT 117.28 37.84 117.76 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 122.8 43.28 123.28 43.76 ; + RECT 117.28 43.28 117.76 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 122.8 48.72 123.28 49.2 ; + RECT 117.28 48.72 117.76 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 122.8 54.16 123.28 54.64 ; + RECT 117.28 54.16 117.76 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 122.8 59.6 123.28 60.08 ; + RECT 117.28 59.6 117.76 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 122.8 65.04 123.28 65.52 ; + RECT 117.28 65.04 117.76 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 122.8 70.48 123.28 70.96 ; + RECT 117.28 70.48 117.76 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 122.8 75.92 123.28 76.4 ; + RECT 117.28 75.92 117.76 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 122.8 81.36 123.28 81.84 ; + RECT 117.28 81.36 117.76 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 122.8 86.8 123.28 87.28 ; + RECT 117.28 86.8 117.76 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 122.8 92.24 123.28 92.72 ; - RECT 0 97.68 123.28 98.16 ; - RECT 27.6 103.12 28.08 103.6 ; - RECT 95.2 103.12 95.68 103.6 ; - RECT 27.6 108.56 95.68 108.8 ; + RECT 117.28 92.24 117.76 92.72 ; + RECT 0 97.68 117.76 98.16 ; + RECT 25.76 103.12 26.24 103.6 ; + RECT 91.52 103.12 92 103.6 ; + RECT 25.76 108.56 92 108.8 ; LAYER met4 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 10.88 10.42 11.48 ; - RECT 9.82 97.32 10.42 97.92 ; - RECT 53.98 108.2 54.58 108.8 ; - RECT 83.42 108.2 84.02 108.8 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 10.88 11.34 11.48 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 51.22 108.2 51.82 108.8 ; + RECT 80.66 108.2 81.26 108.8 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 120.08 42.6 123.28 45.8 ; + RECT 114.56 42.6 117.76 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 120.08 83.4 123.28 86.6 ; + RECT 114.56 83.4 117.76 86.6 ; END END VSS PIN prog_clk__FEEDTHRU_1[0] @@ -2039,7 +2039,7 @@ MACRO sb_1__1_ USE CLOCK ; PORT LAYER met2 ; - RECT 57.43 107.44 57.57 108.8 ; + RECT 55.13 107.44 55.27 108.8 ; END END prog_clk__FEEDTHRU_1[0] PIN Test_en__FEEDTHRU_0[0] @@ -2047,7 +2047,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 10.88 2.37 12.24 ; + RECT 2.23 96.56 2.37 97.92 ; END END Test_en__FEEDTHRU_0[0] PIN Test_en__FEEDTHRU_1[0] @@ -2055,15 +2055,31 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; + RECT 2.23 10.88 2.37 12.24 ; END END Test_en__FEEDTHRU_1[0] + PIN clk__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 96.56 3.29 97.92 ; + END + END clk__FEEDTHRU_0[0] + PIN clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 10.88 3.29 12.24 ; + END + END clk__FEEDTHRU_1[0] PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 18.33 10.88 18.47 12.24 ; END END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] @@ -2071,138 +2087,131 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 107.44 35.95 108.8 ; + RECT 99.29 96.56 99.43 97.92 ; END END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 27.6 108.715 95.68 108.885 ; - RECT 94.76 105.995 95.68 106.165 ; - RECT 27.6 105.995 31.28 106.165 ; - RECT 94.76 103.275 95.68 103.445 ; - RECT 27.6 103.275 31.28 103.445 ; - RECT 94.76 100.555 95.68 100.725 ; - RECT 27.6 100.555 31.28 100.725 ; - RECT 92.92 97.835 123.28 98.005 ; + RECT 25.76 108.715 92 108.885 ; + RECT 91.54 105.995 92 106.165 ; + RECT 25.76 105.995 29.44 106.165 ; + RECT 91.08 103.275 92 103.445 ; + RECT 25.76 103.275 27.6 103.445 ; + RECT 91.08 100.555 92 100.725 ; + RECT 25.76 100.555 29.44 100.725 ; + RECT 89.24 97.835 117.76 98.005 ; RECT 0 97.835 29.44 98.005 ; - RECT 122.36 95.115 123.28 95.285 ; + RECT 116.84 95.115 117.76 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 122.36 92.395 123.28 92.565 ; - RECT 0 92.395 1.84 92.565 ; - RECT 122.36 89.675 123.28 89.845 ; + RECT 114.08 92.395 117.76 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 114.08 89.675 117.76 89.845 ; RECT 0 89.675 1.84 89.845 ; - RECT 122.36 86.955 123.28 87.125 ; + RECT 117.3 86.955 117.76 87.125 ; RECT 0 86.955 1.84 87.125 ; - RECT 122.82 84.235 123.28 84.405 ; + RECT 117.3 84.235 117.76 84.405 ; RECT 0 84.235 1.84 84.405 ; - RECT 122.36 81.515 123.28 81.685 ; + RECT 115.92 81.515 117.76 81.685 ; RECT 0 81.515 1.84 81.685 ; - RECT 122.36 78.795 123.28 78.965 ; + RECT 115.92 78.795 117.76 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 122.36 76.075 123.28 76.245 ; + RECT 116.84 76.075 117.76 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 122.36 73.355 123.28 73.525 ; + RECT 116.84 73.355 117.76 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 122.36 70.635 123.28 70.805 ; + RECT 116.84 70.635 117.76 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 122.36 67.915 123.28 68.085 ; + RECT 116.84 67.915 117.76 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 122.36 65.195 123.28 65.365 ; + RECT 116.84 65.195 117.76 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 122.36 62.475 123.28 62.645 ; + RECT 116.84 62.475 117.76 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 122.36 59.755 123.28 59.925 ; + RECT 116.84 59.755 117.76 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 122.36 57.035 123.28 57.205 ; + RECT 116.84 57.035 117.76 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 122.36 54.315 123.28 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 122.36 51.595 123.28 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 122.36 48.875 123.28 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 122.36 46.155 123.28 46.325 ; + RECT 116.84 54.315 117.76 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 116.84 51.595 117.76 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 116.84 48.875 117.76 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 116.84 46.155 117.76 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 122.36 43.435 123.28 43.605 ; + RECT 116.84 43.435 117.76 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 122.36 40.715 123.28 40.885 ; + RECT 116.84 40.715 117.76 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 122.36 37.995 123.28 38.165 ; + RECT 116.84 37.995 117.76 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 122.36 35.275 123.28 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 122.82 32.555 123.28 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 122.82 29.835 123.28 30.005 ; + RECT 116.84 35.275 117.76 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 116.84 32.555 117.76 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 116.84 29.835 117.76 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 122.82 27.115 123.28 27.285 ; + RECT 114.08 27.115 117.76 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 119.6 24.395 123.28 24.565 ; + RECT 114.08 24.395 117.76 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 119.6 21.675 123.28 21.845 ; + RECT 116.84 21.675 117.76 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 122.36 18.955 123.28 19.125 ; + RECT 116.84 18.955 117.76 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 122.82 16.235 123.28 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 122.36 13.515 123.28 13.685 ; + RECT 116.84 16.235 117.76 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 117.3 13.515 117.76 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 92.92 10.795 123.28 10.965 ; - RECT 0 10.795 31.28 10.965 ; - RECT 94.76 8.075 95.68 8.245 ; - RECT 27.6 8.075 31.28 8.245 ; - RECT 94.76 5.355 95.68 5.525 ; - RECT 27.6 5.355 31.28 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; - RECT 27.6 2.635 31.28 2.805 ; - RECT 27.6 -0.085 95.68 0.085 ; + RECT 88.78 10.795 117.76 10.965 ; + RECT 0 10.795 29.44 10.965 ; + RECT 91.08 8.075 92 8.245 ; + RECT 25.76 8.075 29.44 8.245 ; + RECT 91.08 5.355 92 5.525 ; + RECT 25.76 5.355 29.44 5.525 ; + RECT 91.08 2.635 92 2.805 ; + RECT 25.76 2.635 29.44 2.805 ; + RECT 25.76 -0.085 92 0.085 ; LAYER met2 ; - RECT 83.58 108.615 83.86 108.985 ; - RECT 54.14 108.615 54.42 108.985 ; - RECT 82.21 106.94 82.47 107.26 ; - RECT 69.33 106.94 69.59 107.26 ; - RECT 9.98 97.735 10.26 98.105 ; - RECT 9.98 10.695 10.26 11.065 ; - RECT 90.95 1.54 91.21 1.86 ; - RECT 84.97 1.54 85.23 1.86 ; - RECT 53.23 1.54 53.49 1.86 ; - RECT 49.55 1.54 49.81 1.86 ; - RECT 35.29 1.54 35.55 1.86 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - POLYGON 95.4 108.52 95.4 97.64 123 97.64 123 11.16 119.03 11.16 119.03 12.52 118.33 12.52 118.33 11.16 118.11 11.16 118.11 12.52 117.41 12.52 117.41 11.16 117.19 11.16 117.19 12.52 116.49 12.52 116.49 11.16 116.27 11.16 116.27 12.52 115.57 12.52 115.57 11.16 115.35 11.16 115.35 12.52 114.65 12.52 114.65 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.05 11.16 113.05 12.52 112.35 12.52 112.35 11.16 110.29 11.16 110.29 12.52 109.59 12.52 109.59 11.16 95.4 11.16 95.4 0.28 90.97 0.28 90.97 1.64 90.27 1.64 90.27 0.28 90.05 0.28 90.05 1.64 89.35 1.64 89.35 0.28 89.13 0.28 89.13 1.64 88.43 1.64 88.43 0.28 88.21 0.28 88.21 1.64 87.51 1.64 87.51 0.28 85.91 0.28 85.91 1.64 85.21 1.64 85.21 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 5.17 97.64 5.17 96.28 5.87 96.28 5.87 97.64 6.09 97.64 6.09 96.28 6.79 96.28 6.79 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 10.69 97.64 10.69 96.28 11.39 96.28 11.39 97.64 11.61 97.64 11.61 96.28 12.31 96.28 12.31 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 17.59 97.64 17.59 96.28 18.29 96.28 18.29 97.64 27.88 97.64 27.88 108.52 34.61 108.52 34.61 107.16 35.31 107.16 35.31 108.52 35.53 108.52 35.53 107.16 36.23 107.16 36.23 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 51.17 108.52 51.17 107.16 51.87 107.16 51.87 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 55.31 108.52 55.31 107.16 56.01 107.16 56.01 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.53 108.52 58.53 107.16 59.23 107.16 59.23 108.52 59.45 108.52 59.45 107.16 60.15 107.16 60.15 108.52 60.37 108.52 60.37 107.16 61.07 107.16 61.07 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 66.35 108.52 66.35 107.16 67.05 107.16 67.05 108.52 67.27 108.52 67.27 107.16 67.97 107.16 67.97 108.52 68.19 108.52 68.19 107.16 68.89 107.16 68.89 108.52 69.57 108.52 69.57 107.16 70.27 107.16 70.27 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 71.87 108.52 71.87 107.16 72.57 107.16 72.57 108.52 72.79 108.52 72.79 107.16 73.49 107.16 73.49 108.52 73.71 108.52 73.71 107.16 74.41 107.16 74.41 108.52 74.63 108.52 74.63 107.16 75.33 107.16 75.33 108.52 75.55 108.52 75.55 107.16 76.25 107.16 76.25 108.52 76.47 108.52 76.47 107.16 77.17 107.16 77.17 108.52 77.39 108.52 77.39 107.16 78.09 107.16 78.09 108.52 78.31 108.52 78.31 107.16 79.01 107.16 79.01 108.52 79.23 108.52 79.23 107.16 79.93 107.16 79.93 108.52 80.15 108.52 80.15 107.16 80.85 107.16 80.85 108.52 81.07 108.52 81.07 107.16 81.77 107.16 81.77 108.52 82.45 108.52 82.45 107.16 83.15 107.16 83.15 108.52 84.29 108.52 84.29 107.16 84.99 107.16 84.99 108.52 85.21 108.52 85.21 107.16 85.91 107.16 85.91 108.52 86.13 108.52 86.13 107.16 86.83 107.16 86.83 108.52 87.51 108.52 87.51 107.16 88.21 107.16 88.21 108.52 ; + RECT 80.82 108.615 81.1 108.985 ; + RECT 51.38 108.615 51.66 108.985 ; + RECT 74.85 106.94 75.11 107.26 ; + RECT 66.57 106.94 66.83 107.26 ; + RECT 65.19 106.94 65.45 107.26 ; + RECT 46.79 106.94 47.05 107.26 ; + RECT 10.9 97.735 11.18 98.105 ; + RECT 107.97 12.42 108.23 12.74 ; + RECT 10.9 10.695 11.18 11.065 ; + RECT 68.41 1.54 68.67 1.86 ; + RECT 57.37 1.54 57.63 1.86 ; + RECT 50.93 1.54 51.19 1.86 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + POLYGON 91.72 108.52 91.72 97.64 99.01 97.64 99.01 96.28 99.71 96.28 99.71 97.64 117.48 97.64 117.48 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.51 11.16 113.51 12.52 112.81 12.52 112.81 11.16 112.13 11.16 112.13 12.52 111.43 12.52 111.43 11.16 111.21 11.16 111.21 12.52 110.51 12.52 110.51 11.16 109.83 11.16 109.83 12.52 109.13 12.52 109.13 11.16 108.91 11.16 108.91 12.52 108.21 12.52 108.21 11.16 106.61 11.16 106.61 12.52 105.91 12.52 105.91 11.16 102.01 11.16 102.01 12.52 101.31 12.52 101.31 11.16 91.72 11.16 91.72 0.28 89.59 0.28 89.59 1.64 88.89 1.64 88.89 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 18.75 11.16 18.75 12.52 18.05 12.52 18.05 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 2.87 97.64 2.87 96.28 3.57 96.28 3.57 97.64 6.55 97.64 6.55 96.28 7.25 96.28 7.25 97.64 7.47 97.64 7.47 96.28 8.17 96.28 8.17 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 13.91 97.64 13.91 96.28 14.61 96.28 14.61 97.64 15.75 97.64 15.75 96.28 16.45 96.28 16.45 97.64 26.04 97.64 26.04 108.52 27.71 108.52 27.71 107.16 28.41 107.16 28.41 108.52 28.63 108.52 28.63 107.16 29.33 107.16 29.33 108.52 34.15 108.52 34.15 107.16 34.85 107.16 34.85 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 49.33 108.52 49.33 107.16 50.03 107.16 50.03 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 56.23 108.52 56.23 107.16 56.93 107.16 56.93 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 60.37 108.52 60.37 107.16 61.07 107.16 61.07 108.52 61.29 108.52 61.29 107.16 61.99 107.16 61.99 108.52 62.21 108.52 62.21 107.16 62.91 107.16 62.91 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.89 108.52 65.89 107.16 66.59 107.16 66.59 108.52 66.81 108.52 66.81 107.16 67.51 107.16 67.51 108.52 67.73 108.52 67.73 107.16 68.43 107.16 68.43 108.52 68.65 108.52 68.65 107.16 69.35 107.16 69.35 108.52 69.57 108.52 69.57 107.16 70.27 107.16 70.27 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 72.33 108.52 72.33 107.16 73.03 107.16 73.03 108.52 73.25 108.52 73.25 107.16 73.95 107.16 73.95 108.52 74.17 108.52 74.17 107.16 74.87 107.16 74.87 108.52 75.09 108.52 75.09 107.16 75.79 107.16 75.79 108.52 76.01 108.52 76.01 107.16 76.71 107.16 76.71 108.52 76.93 108.52 76.93 107.16 77.63 107.16 77.63 108.52 77.85 108.52 77.85 107.16 78.55 107.16 78.55 108.52 78.77 108.52 78.77 107.16 79.47 107.16 79.47 108.52 79.69 108.52 79.69 107.16 80.39 107.16 80.39 108.52 81.99 108.52 81.99 107.16 82.69 107.16 82.69 108.52 82.91 108.52 82.91 107.16 83.61 107.16 83.61 108.52 83.83 108.52 83.83 107.16 84.53 107.16 84.53 108.52 ; LAYER met4 ; - POLYGON 95.28 108.4 95.28 97.52 112.46 97.52 112.46 96.92 113.86 96.92 113.86 97.52 122.88 97.52 122.88 11.28 113.86 11.28 113.86 11.88 112.46 11.88 112.46 11.28 95.28 11.28 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 28 97.52 28 108.4 38.86 108.4 38.86 107.8 40.26 107.8 40.26 108.4 53.58 108.4 53.58 107.8 54.98 107.8 54.98 108.4 65.69 108.4 65.69 107.04 66.79 107.04 66.79 108.4 68.3 108.4 68.3 107.8 69.7 107.8 69.7 108.4 83.02 108.4 83.02 107.8 84.42 107.8 84.42 108.4 ; + POLYGON 91.6 108.4 91.6 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 67.53 108.4 67.53 107.04 68.63 107.04 68.63 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; LAYER met3 ; - POLYGON 83.885 108.965 83.885 108.96 84.1 108.96 84.1 108.64 83.885 108.64 83.885 108.635 83.555 108.635 83.555 108.64 83.34 108.64 83.34 108.96 83.555 108.96 83.555 108.965 ; - POLYGON 54.445 108.965 54.445 108.96 54.66 108.96 54.66 108.64 54.445 108.64 54.445 108.635 54.115 108.635 54.115 108.64 53.9 108.64 53.9 108.96 54.115 108.96 54.115 108.965 ; - POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; - POLYGON 7.05 83.79 7.05 83.49 1.99 83.49 1.99 82.81 1.78 82.81 1.78 83.51 1.69 83.51 1.69 83.79 ; - POLYGON 10.27 74.27 10.27 73.97 1.99 73.97 1.99 73.29 1.78 73.29 1.78 73.99 1.69 73.99 1.69 74.27 ; - POLYGON 7.97 58.63 7.97 58.33 1.99 58.33 1.99 57.65 1.78 57.65 1.78 58.35 1.69 58.35 1.69 58.63 ; - POLYGON 2.03 47.08 2.03 47.07 57.19 47.07 57.19 46.77 2.03 46.77 2.03 46.76 1.65 46.76 1.65 47.08 ; - POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 95.28 108.4 95.28 97.52 122.88 97.52 122.88 93.03 121.5 93.03 121.5 91.93 122.88 91.93 122.88 91.67 121.5 91.67 121.5 90.57 122.88 90.57 122.88 90.31 121.5 90.31 121.5 89.21 122.88 89.21 122.88 88.95 121.5 88.95 121.5 87.85 122.88 87.85 122.88 87.59 121.5 87.59 121.5 86.49 122.88 86.49 122.88 85.55 121.5 85.55 121.5 84.45 122.88 84.45 122.88 84.19 121.5 84.19 121.5 83.09 122.88 83.09 122.88 82.83 121.5 82.83 121.5 81.73 122.88 81.73 122.88 81.47 121.5 81.47 121.5 80.37 122.88 80.37 122.88 80.11 121.5 80.11 121.5 79.01 122.88 79.01 122.88 78.75 121.5 78.75 121.5 77.65 122.88 77.65 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 73.31 121.5 73.31 121.5 72.21 122.88 72.21 122.88 71.95 121.5 71.95 121.5 70.85 122.88 70.85 122.88 69.91 121.5 69.91 121.5 68.81 122.88 68.81 122.88 67.87 121.5 67.87 121.5 66.77 122.88 66.77 122.88 66.51 121.5 66.51 121.5 65.41 122.88 65.41 122.88 65.15 121.5 65.15 121.5 64.05 122.88 64.05 122.88 63.11 121.5 63.11 121.5 62.01 122.88 62.01 122.88 61.75 121.5 61.75 121.5 60.65 122.88 60.65 122.88 60.39 121.5 60.39 121.5 59.29 122.88 59.29 122.88 59.03 121.5 59.03 121.5 57.93 122.88 57.93 122.88 57.67 121.5 57.67 121.5 56.57 122.88 56.57 122.88 56.31 121.5 56.31 121.5 55.21 122.88 55.21 122.88 54.95 121.5 54.95 121.5 53.85 122.88 53.85 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 51.55 121.5 51.55 121.5 50.45 122.88 50.45 122.88 50.19 121.5 50.19 121.5 49.09 122.88 49.09 122.88 48.83 121.5 48.83 121.5 47.73 122.88 47.73 122.88 47.47 121.5 47.47 121.5 46.37 122.88 46.37 122.88 46.11 121.5 46.11 121.5 45.01 122.88 45.01 122.88 44.75 121.5 44.75 121.5 43.65 122.88 43.65 122.88 43.39 121.5 43.39 121.5 42.29 122.88 42.29 122.88 42.03 121.5 42.03 121.5 40.93 122.88 40.93 122.88 40.67 121.5 40.67 121.5 39.57 122.88 39.57 122.88 39.31 121.5 39.31 121.5 38.21 122.88 38.21 122.88 37.95 121.5 37.95 121.5 36.85 122.88 36.85 122.88 36.59 121.5 36.59 121.5 35.49 122.88 35.49 122.88 32.51 121.5 32.51 121.5 31.41 122.88 31.41 122.88 11.28 95.28 11.28 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 97.52 28 97.52 28 108.4 ; + POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; + POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; + POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; + POLYGON 15.79 87.87 15.79 87.57 1.78 87.57 1.78 87.59 1.23 87.59 1.23 87.87 ; + POLYGON 116.11 72.92 116.11 72.6 115.73 72.6 115.73 72.61 107.49 72.61 107.49 72.91 115.73 72.91 115.73 72.92 ; + POLYGON 17.63 66.11 17.63 65.81 1.78 65.81 1.78 65.83 1.23 65.83 1.23 66.11 ; + POLYGON 2.005 57.965 2.005 57.96 2.03 57.96 2.03 57.64 2.005 57.64 2.005 57.635 1.275 57.635 1.275 57.965 ; + POLYGON 19.01 46.39 19.01 46.09 1.78 46.09 1.78 46.11 1.23 46.11 1.23 46.39 ; + POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 91.6 108.4 91.6 97.52 117.36 97.52 117.36 93.03 115.98 93.03 115.98 91.93 117.36 91.93 117.36 91.67 115.98 91.67 115.98 90.57 117.36 90.57 117.36 90.31 115.98 90.31 115.98 89.21 117.36 89.21 117.36 84.87 115.98 84.87 115.98 83.77 117.36 83.77 117.36 83.51 115.98 83.51 115.98 82.41 117.36 82.41 117.36 82.15 115.98 82.15 115.98 81.05 117.36 81.05 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 79.43 115.98 79.43 115.98 78.33 117.36 78.33 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.71 115.98 76.71 115.98 75.61 117.36 75.61 117.36 75.35 115.98 75.35 115.98 74.25 117.36 74.25 117.36 73.99 115.98 73.99 115.98 72.89 117.36 72.89 117.36 72.63 115.98 72.63 115.98 71.53 117.36 71.53 117.36 71.27 115.98 71.27 115.98 70.17 117.36 70.17 117.36 69.91 115.98 69.91 115.98 68.81 117.36 68.81 117.36 68.55 115.98 68.55 115.98 67.45 117.36 67.45 117.36 67.19 115.98 67.19 115.98 66.09 117.36 66.09 117.36 65.83 115.98 65.83 115.98 64.73 117.36 64.73 117.36 64.47 115.98 64.47 115.98 63.37 117.36 63.37 117.36 62.43 115.98 62.43 115.98 61.33 117.36 61.33 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 56.31 115.98 56.31 115.98 55.21 117.36 55.21 117.36 54.95 115.98 54.95 115.98 53.85 117.36 53.85 117.36 53.59 115.98 53.59 115.98 52.49 117.36 52.49 117.36 52.23 115.98 52.23 115.98 51.13 117.36 51.13 117.36 50.87 115.98 50.87 115.98 49.77 117.36 49.77 117.36 49.51 115.98 49.51 115.98 48.41 117.36 48.41 117.36 48.15 115.98 48.15 115.98 47.05 117.36 47.05 117.36 46.79 115.98 46.79 115.98 45.69 117.36 45.69 117.36 45.43 115.98 45.43 115.98 44.33 117.36 44.33 117.36 44.07 115.98 44.07 115.98 42.97 117.36 42.97 117.36 42.71 115.98 42.71 115.98 41.61 117.36 41.61 117.36 41.35 115.98 41.35 115.98 40.25 117.36 40.25 117.36 39.99 115.98 39.99 115.98 38.89 117.36 38.89 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 32.51 115.98 32.51 115.98 31.41 117.36 31.41 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 97.52 26.16 97.52 26.16 108.4 ; LAYER met5 ; - POLYGON 94.08 107.2 94.08 96.32 121.68 96.32 121.68 88.2 118.48 88.2 118.48 81.8 121.68 81.8 121.68 67.8 118.48 67.8 118.48 61.4 121.68 61.4 121.68 47.4 118.48 47.4 118.48 41 121.68 41 121.68 27 118.48 27 118.48 20.6 121.68 20.6 121.68 12.48 94.08 12.48 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 29.2 96.32 29.2 107.2 ; + POLYGON 90.4 107.2 90.4 96.32 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; LAYER met1 ; - POLYGON 68.7 98.57 68.7 98.31 68.38 98.31 68.38 98.37 61.325 98.37 61.325 98.325 61.035 98.325 61.035 98.555 61.325 98.555 61.325 98.51 68.38 98.51 68.38 98.57 ; - POLYGON 95.4 108.28 95.4 106.6 94.92 106.6 94.92 105.56 95.4 105.56 95.4 103.88 94.92 103.88 94.92 102.84 95.4 102.84 95.4 101.16 94.92 101.16 94.92 100.12 95.4 100.12 95.4 98.44 27.88 98.44 27.88 100.12 28.36 100.12 28.36 101.16 27.88 101.16 27.88 102.84 28.36 102.84 28.36 103.88 27.88 103.88 27.88 105.56 28.36 105.56 28.36 106.6 27.88 106.6 27.88 108.28 ; - POLYGON 123 97.4 123 95.72 122.52 95.72 122.52 94.68 123 94.68 123 93 122.52 93 122.52 91.96 123 91.96 123 90.28 122.52 90.28 122.52 89.24 123 89.24 123 87.56 122.52 87.56 122.52 86.52 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; + POLYGON 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 ; + POLYGON 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; LAYER li1 ; - POLYGON 95.51 108.63 95.51 97.75 123.11 97.75 123.11 11.05 95.51 11.05 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 27.77 97.75 27.77 108.63 ; + POLYGON 91.83 108.63 91.83 97.75 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; LAYER mcon ; - RECT 95.365 108.715 95.535 108.885 ; - RECT 94.905 108.715 95.075 108.885 ; - RECT 94.445 108.715 94.615 108.885 ; - RECT 93.985 108.715 94.155 108.885 ; - RECT 93.525 108.715 93.695 108.885 ; - RECT 93.065 108.715 93.235 108.885 ; - RECT 92.605 108.715 92.775 108.885 ; - RECT 92.145 108.715 92.315 108.885 ; RECT 91.685 108.715 91.855 108.885 ; RECT 91.225 108.715 91.395 108.885 ; RECT 90.765 108.715 90.935 108.885 ; @@ -2343,31 +2352,22 @@ MACRO sb_1__1_ RECT 28.665 108.715 28.835 108.885 ; RECT 28.205 108.715 28.375 108.885 ; RECT 27.745 108.715 27.915 108.885 ; - RECT 95.365 105.995 95.535 106.165 ; - RECT 94.905 105.995 95.075 106.165 ; - RECT 28.205 105.995 28.375 106.165 ; - RECT 27.745 105.995 27.915 106.165 ; - RECT 95.365 103.275 95.535 103.445 ; - RECT 94.905 103.275 95.075 103.445 ; - RECT 28.205 103.275 28.375 103.445 ; - RECT 27.745 103.275 27.915 103.445 ; - RECT 95.365 100.555 95.535 100.725 ; - RECT 94.905 100.555 95.075 100.725 ; - RECT 28.205 100.555 28.375 100.725 ; - RECT 27.745 100.555 27.915 100.725 ; - RECT 61.095 98.355 61.265 98.525 ; - RECT 122.965 97.835 123.135 98.005 ; - RECT 122.505 97.835 122.675 98.005 ; - RECT 122.045 97.835 122.215 98.005 ; - RECT 121.585 97.835 121.755 98.005 ; - RECT 121.125 97.835 121.295 98.005 ; - RECT 120.665 97.835 120.835 98.005 ; - RECT 120.205 97.835 120.375 98.005 ; - RECT 119.745 97.835 119.915 98.005 ; - RECT 119.285 97.835 119.455 98.005 ; - RECT 118.825 97.835 118.995 98.005 ; - RECT 118.365 97.835 118.535 98.005 ; - RECT 117.905 97.835 118.075 98.005 ; + RECT 27.285 108.715 27.455 108.885 ; + RECT 26.825 108.715 26.995 108.885 ; + RECT 26.365 108.715 26.535 108.885 ; + RECT 25.905 108.715 26.075 108.885 ; + RECT 91.685 105.995 91.855 106.165 ; + RECT 91.225 105.995 91.395 106.165 ; + RECT 26.365 105.995 26.535 106.165 ; + RECT 25.905 105.995 26.075 106.165 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 91.685 100.555 91.855 100.725 ; + RECT 91.225 100.555 91.395 100.725 ; + RECT 26.365 100.555 26.535 100.725 ; + RECT 25.905 100.555 26.075 100.725 ; RECT 117.445 97.835 117.615 98.005 ; RECT 116.985 97.835 117.155 98.005 ; RECT 116.525 97.835 116.695 98.005 ; @@ -2624,142 +2624,130 @@ MACRO sb_1__1_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 122.965 95.115 123.135 95.285 ; - RECT 122.505 95.115 122.675 95.285 ; + RECT 117.445 95.115 117.615 95.285 ; + RECT 116.985 95.115 117.155 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 122.965 92.395 123.135 92.565 ; - RECT 122.505 92.395 122.675 92.565 ; + RECT 117.445 92.395 117.615 92.565 ; + RECT 116.985 92.395 117.155 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 122.965 89.675 123.135 89.845 ; - RECT 122.505 89.675 122.675 89.845 ; + RECT 117.445 89.675 117.615 89.845 ; + RECT 116.985 89.675 117.155 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 122.965 86.955 123.135 87.125 ; - RECT 122.505 86.955 122.675 87.125 ; + RECT 117.445 86.955 117.615 87.125 ; + RECT 116.985 86.955 117.155 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 122.965 84.235 123.135 84.405 ; - RECT 122.505 84.235 122.675 84.405 ; + RECT 117.445 84.235 117.615 84.405 ; + RECT 116.985 84.235 117.155 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 122.965 81.515 123.135 81.685 ; - RECT 122.505 81.515 122.675 81.685 ; + RECT 117.445 81.515 117.615 81.685 ; + RECT 116.985 81.515 117.155 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 122.965 78.795 123.135 78.965 ; - RECT 122.505 78.795 122.675 78.965 ; + RECT 117.445 78.795 117.615 78.965 ; + RECT 116.985 78.795 117.155 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 122.965 76.075 123.135 76.245 ; - RECT 122.505 76.075 122.675 76.245 ; + RECT 117.445 76.075 117.615 76.245 ; + RECT 116.985 76.075 117.155 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 122.965 73.355 123.135 73.525 ; - RECT 122.505 73.355 122.675 73.525 ; + RECT 117.445 73.355 117.615 73.525 ; + RECT 116.985 73.355 117.155 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 122.965 70.635 123.135 70.805 ; - RECT 122.505 70.635 122.675 70.805 ; + RECT 117.445 70.635 117.615 70.805 ; + RECT 116.985 70.635 117.155 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 122.965 67.915 123.135 68.085 ; - RECT 122.505 67.915 122.675 68.085 ; + RECT 117.445 67.915 117.615 68.085 ; + RECT 116.985 67.915 117.155 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 122.965 65.195 123.135 65.365 ; - RECT 122.505 65.195 122.675 65.365 ; + RECT 117.445 65.195 117.615 65.365 ; + RECT 116.985 65.195 117.155 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 122.965 62.475 123.135 62.645 ; - RECT 122.505 62.475 122.675 62.645 ; + RECT 117.445 62.475 117.615 62.645 ; + RECT 116.985 62.475 117.155 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 122.965 59.755 123.135 59.925 ; - RECT 122.505 59.755 122.675 59.925 ; + RECT 117.445 59.755 117.615 59.925 ; + RECT 116.985 59.755 117.155 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 122.965 57.035 123.135 57.205 ; - RECT 122.505 57.035 122.675 57.205 ; + RECT 117.445 57.035 117.615 57.205 ; + RECT 116.985 57.035 117.155 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 122.965 54.315 123.135 54.485 ; - RECT 122.505 54.315 122.675 54.485 ; + RECT 117.445 54.315 117.615 54.485 ; + RECT 116.985 54.315 117.155 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 122.965 51.595 123.135 51.765 ; - RECT 122.505 51.595 122.675 51.765 ; + RECT 117.445 51.595 117.615 51.765 ; + RECT 116.985 51.595 117.155 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 122.965 48.875 123.135 49.045 ; - RECT 122.505 48.875 122.675 49.045 ; + RECT 117.445 48.875 117.615 49.045 ; + RECT 116.985 48.875 117.155 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 122.965 46.155 123.135 46.325 ; - RECT 122.505 46.155 122.675 46.325 ; + RECT 117.445 46.155 117.615 46.325 ; + RECT 116.985 46.155 117.155 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 122.965 43.435 123.135 43.605 ; - RECT 122.505 43.435 122.675 43.605 ; + RECT 117.445 43.435 117.615 43.605 ; + RECT 116.985 43.435 117.155 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 122.965 40.715 123.135 40.885 ; - RECT 122.505 40.715 122.675 40.885 ; + RECT 117.445 40.715 117.615 40.885 ; + RECT 116.985 40.715 117.155 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 122.965 37.995 123.135 38.165 ; - RECT 122.505 37.995 122.675 38.165 ; + RECT 117.445 37.995 117.615 38.165 ; + RECT 116.985 37.995 117.155 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 122.965 35.275 123.135 35.445 ; - RECT 122.505 35.275 122.675 35.445 ; + RECT 117.445 35.275 117.615 35.445 ; + RECT 116.985 35.275 117.155 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 122.965 32.555 123.135 32.725 ; - RECT 122.505 32.555 122.675 32.725 ; + RECT 117.445 32.555 117.615 32.725 ; + RECT 116.985 32.555 117.155 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 122.965 29.835 123.135 30.005 ; - RECT 122.505 29.835 122.675 30.005 ; + RECT 117.445 29.835 117.615 30.005 ; + RECT 116.985 29.835 117.155 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 122.965 27.115 123.135 27.285 ; - RECT 122.505 27.115 122.675 27.285 ; + RECT 117.445 27.115 117.615 27.285 ; + RECT 116.985 27.115 117.155 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 122.965 24.395 123.135 24.565 ; - RECT 122.505 24.395 122.675 24.565 ; + RECT 117.445 24.395 117.615 24.565 ; + RECT 116.985 24.395 117.155 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 122.965 21.675 123.135 21.845 ; - RECT 122.505 21.675 122.675 21.845 ; + RECT 117.445 21.675 117.615 21.845 ; + RECT 116.985 21.675 117.155 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 122.965 18.955 123.135 19.125 ; - RECT 122.505 18.955 122.675 19.125 ; + RECT 117.445 18.955 117.615 19.125 ; + RECT 116.985 18.955 117.155 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 122.965 16.235 123.135 16.405 ; - RECT 122.505 16.235 122.675 16.405 ; + RECT 117.445 16.235 117.615 16.405 ; + RECT 116.985 16.235 117.155 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 122.965 13.515 123.135 13.685 ; - RECT 122.505 13.515 122.675 13.685 ; + RECT 117.445 13.515 117.615 13.685 ; + RECT 116.985 13.515 117.155 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 122.965 10.795 123.135 10.965 ; - RECT 122.505 10.795 122.675 10.965 ; - RECT 122.045 10.795 122.215 10.965 ; - RECT 121.585 10.795 121.755 10.965 ; - RECT 121.125 10.795 121.295 10.965 ; - RECT 120.665 10.795 120.835 10.965 ; - RECT 120.205 10.795 120.375 10.965 ; - RECT 119.745 10.795 119.915 10.965 ; - RECT 119.285 10.795 119.455 10.965 ; - RECT 118.825 10.795 118.995 10.965 ; - RECT 118.365 10.795 118.535 10.965 ; - RECT 117.905 10.795 118.075 10.965 ; RECT 117.445 10.795 117.615 10.965 ; RECT 116.985 10.795 117.155 10.965 ; RECT 116.525 10.795 116.695 10.965 ; @@ -3016,26 +3004,18 @@ MACRO sb_1__1_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; - RECT 28.205 8.075 28.375 8.245 ; - RECT 27.745 8.075 27.915 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; - RECT 28.205 5.355 28.375 5.525 ; - RECT 27.745 5.355 27.915 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; - RECT 28.205 2.635 28.375 2.805 ; - RECT 27.745 2.635 27.915 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; + RECT 26.365 8.075 26.535 8.245 ; + RECT 25.905 8.075 26.075 8.245 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; + RECT 26.365 5.355 26.535 5.525 ; + RECT 25.905 5.355 26.075 5.525 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; + RECT 26.365 2.635 26.535 2.805 ; + RECT 25.905 2.635 26.075 2.805 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -3176,59 +3156,56 @@ MACRO sb_1__1_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; LAYER via ; - RECT 83.645 108.725 83.795 108.875 ; - RECT 54.205 108.725 54.355 108.875 ; - RECT 87.785 107.025 87.935 107.175 ; - RECT 35.805 107.025 35.955 107.175 ; - RECT 68.465 98.365 68.615 98.515 ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 10.045 97.845 10.195 97.995 ; - RECT 17.865 96.145 18.015 96.295 ; - RECT 12.805 96.145 12.955 96.295 ; - RECT 112.625 12.505 112.775 12.655 ; - RECT 4.065 12.505 4.215 12.655 ; - RECT 83.645 10.805 83.795 10.955 ; - RECT 54.205 10.805 54.355 10.955 ; - RECT 10.045 10.805 10.195 10.955 ; - RECT 88.705 1.625 88.855 1.775 ; - RECT 79.505 1.625 79.655 1.775 ; - RECT 63.405 1.625 63.555 1.775 ; - RECT 50.985 1.625 51.135 1.775 ; - RECT 48.225 1.625 48.375 1.775 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; + RECT 80.885 108.725 81.035 108.875 ; + RECT 51.445 108.725 51.595 108.875 ; + RECT 63.865 107.025 64.015 107.175 ; + RECT 49.605 107.025 49.755 107.175 ; + RECT 43.625 107.025 43.775 107.175 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 10.965 97.845 11.115 97.995 ; + RECT 14.185 96.145 14.335 96.295 ; + RECT 9.125 96.145 9.275 96.295 ; + RECT 114.005 12.505 114.155 12.655 ; + RECT 4.985 12.505 5.135 12.655 ; + RECT 80.885 10.805 81.035 10.955 ; + RECT 51.445 10.805 51.595 10.955 ; + RECT 10.965 10.805 11.115 10.955 ; + RECT 69.845 1.625 69.995 1.775 ; + RECT 65.245 1.625 65.395 1.775 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; - RECT 83.62 108.7 83.82 108.9 ; - RECT 54.18 108.7 54.38 108.9 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.28 89.66 1.48 89.86 ; - RECT 121.8 83.54 122 83.74 ; - RECT 121.8 76.74 122 76.94 ; - RECT 121.8 71.3 122 71.5 ; - RECT 1.28 69.26 1.48 69.46 ; - RECT 1.28 65.86 1.48 66.06 ; - RECT 121.34 64.5 121.54 64.7 ; - RECT 1.28 60.42 1.48 60.62 ; - RECT 121.8 55.66 122 55.86 ; - RECT 121.34 52.94 121.54 53.14 ; - RECT 121.8 45.46 122 45.66 ; - RECT 1.28 40.7 1.48 40.9 ; - RECT 121.8 31.86 122 32.06 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 108.7 81.06 108.9 ; + RECT 51.42 108.7 51.62 108.9 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 1.28 85.58 1.48 85.78 ; + RECT 1.74 80.14 1.94 80.34 ; + RECT 1.74 61.1 1.94 61.3 ; + RECT 1.28 59.06 1.48 59.26 ; + RECT 116.28 54.3 116.48 54.5 ; + RECT 115.82 47.5 116.02 47.7 ; + RECT 1.28 33.22 1.48 33.42 ; + RECT 116.28 31.86 116.48 32.06 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; - RECT 83.62 108.7 83.82 108.9 ; - RECT 54.18 108.7 54.38 108.9 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.74 36.62 1.94 36.82 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 108.7 81.06 108.9 ; + RECT 51.42 108.7 51.62 108.9 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 1.74 53.62 1.94 53.82 ; + RECT 115.82 43.42 116.02 43.62 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER OVERLAP ; - POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 27.6 97.92 27.6 108.8 95.68 108.8 95.68 97.92 123.28 97.92 123.28 10.88 95.68 10.88 95.68 0 ; + POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 97.92 117.76 97.92 117.76 10.88 92 10.88 92 0 ; END END sb_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef index 99a1413..115f31a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 123.28 BY 97.92 ; + SIZE 117.76 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 55.59 0 55.73 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 71.25 123.28 71.55 ; + RECT 116.38 81.45 117.76 81.75 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -379,7 +379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 34.53 123.28 34.83 ; + RECT 116.38 53.57 117.76 53.87 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -387,7 +387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 73.97 123.28 74.27 ; + RECT 116.38 80.09 117.76 80.39 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -395,7 +395,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 81.45 123.28 81.75 ; + RECT 116.38 72.61 117.76 72.91 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -403,7 +403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 35.89 123.28 36.19 ; + RECT 116.38 33.85 117.76 34.15 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 17.53 123.28 17.83 ; + RECT 116.38 22.97 117.76 23.27 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 40.65 123.28 40.95 ; + RECT 116.38 24.33 117.76 24.63 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 50.17 123.28 50.47 ; + RECT 116.38 49.49 117.76 49.79 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 76.69 123.28 76.99 ; + RECT 116.38 77.37 117.76 77.67 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -443,7 +443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 61.05 123.28 61.35 ; + RECT 116.38 59.69 117.76 59.99 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -451,7 +451,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 72.61 123.28 72.91 ; + RECT 116.38 73.97 117.76 74.27 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -459,7 +459,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 80.09 123.28 80.39 ; + RECT 116.38 68.53 117.76 68.83 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -467,7 +467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 57.65 123.28 57.95 ; + RECT 116.38 50.85 117.76 51.15 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -475,7 +475,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 67.85 123.28 68.15 ; + RECT 116.38 71.25 117.76 71.55 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -483,7 +483,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 54.93 123.28 55.23 ; + RECT 116.38 31.13 117.76 31.43 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -491,7 +491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 52.89 123.28 53.19 ; + RECT 116.38 55.61 117.76 55.91 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -499,7 +499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 59.69 123.28 59.99 ; + RECT 116.38 29.09 117.76 29.39 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 84.17 123.28 84.47 ; + RECT 116.38 52.21 117.76 52.51 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 75.33 123.28 75.63 ; + RECT 116.38 56.97 117.76 57.27 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 62.41 123.28 62.71 ; + RECT 116.38 58.33 117.76 58.63 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 37.25 123.28 37.55 ; + RECT 116.38 37.93 117.76 38.23 ; END END right_top_grid_pin_1_[0] PIN right_bottom_grid_pin_34_[0] @@ -539,7 +539,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 114.93 10.88 115.07 12.24 ; + RECT 109.41 10.88 109.55 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -547,7 +547,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 115.85 10.88 115.99 12.24 ; + RECT 111.71 10.88 111.85 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] @@ -555,7 +555,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 109.87 10.88 110.01 12.24 ; + RECT 114.01 10.88 114.15 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -563,7 +563,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 112.63 10.88 112.77 12.24 ; + RECT 108.49 10.88 108.63 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -571,7 +571,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 118.61 10.88 118.75 12.24 ; + RECT 110.79 10.88 110.93 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -579,7 +579,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 116.77 10.88 116.91 12.24 ; + RECT 113.09 10.88 113.23 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -587,7 +587,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 117.69 10.88 117.83 12.24 ; + RECT 101.59 10.88 101.73 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -595,7 +595,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 114.01 10.88 114.15 12.24 ; + RECT 106.19 10.88 106.33 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -603,7 +603,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -611,7 +611,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 68.93 0 69.07 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -619,7 +619,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 0 80.57 1.36 ; + RECT 79.05 0 79.19 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 69.85 0 69.99 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 0 64.47 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 68.01 0 68.15 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; + RECT 70.77 0 70.91 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -699,7 +699,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -707,7 +707,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.35 0 81.49 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 0 63.55 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,23 +755,23 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.59 0 78.73 1.36 ; + RECT 72.61 0 72.75 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 11.43 10.88 11.57 12.24 ; + LAYER met4 ; + RECT 12.73 10.88 13.03 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; + LAYER met4 ; + RECT 9.05 10.88 9.35 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -779,7 +779,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.35 10.88 12.49 12.24 ; + RECT 27.99 0 28.13 1.36 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -787,7 +787,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 10.88 14.33 12.24 ; + RECT 7.29 10.88 7.43 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -795,7 +795,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] @@ -803,23 +803,23 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 10.88 18.01 12.24 ; + RECT 15.11 10.88 15.25 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 10.88 5.67 12.24 ; + LAYER met2 ; + RECT 8.21 10.88 8.35 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 11.81 10.88 12.11 12.24 ; + LAYER met2 ; + RECT 10.05 10.88 10.19 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -827,7 +827,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -835,7 +835,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -843,7 +843,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -851,7 +851,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -859,7 +859,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -867,7 +867,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -875,7 +875,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -883,7 +883,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -891,7 +891,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -899,7 +899,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -907,7 +907,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -915,7 +915,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -923,7 +923,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -931,7 +931,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -939,7 +939,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -947,7 +947,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -955,7 +955,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -963,7 +963,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -971,7 +971,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -987,7 +987,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 61.05 1.38 61.35 ; END END left_top_grid_pin_1_[0] PIN left_bottom_grid_pin_34_[0] @@ -995,7 +995,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; + RECT 28.91 0 29.05 1.36 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] @@ -1003,7 +1003,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 10.88 13.41 12.24 ; + RECT 12.81 10.88 12.95 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -1019,7 +1019,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 10.88 6.05 12.24 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1027,15 +1027,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 10.88 7.89 12.24 ; + RECT 6.37 10.88 6.51 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; + LAYER met4 ; + RECT 4.45 10.88 4.75 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -1043,7 +1043,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; + RECT 11.89 10.88 12.03 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1051,7 +1051,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 10.88 6.97 12.24 ; + RECT 16.03 10.88 16.17 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1059,7 +1059,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 42.69 123.28 42.99 ; + RECT 116.38 48.13 117.76 48.43 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -1067,7 +1067,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 31.81 123.28 32.11 ; + RECT 116.38 14.13 117.76 14.43 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1075,7 +1075,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 33.17 123.28 33.47 ; + RECT 116.38 32.49 117.76 32.79 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1083,7 +1083,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 29.09 123.28 29.39 ; + RECT 116.38 15.49 117.76 15.79 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1091,7 +1091,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 30.45 123.28 30.75 ; + RECT 116.38 61.05 117.76 61.35 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1099,7 +1099,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 63.77 123.28 64.07 ; + RECT 116.38 21.61 117.76 21.91 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1107,7 +1107,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 19.57 123.28 19.87 ; + RECT 116.38 26.37 117.76 26.67 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1115,7 +1115,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 46.09 123.28 46.39 ; + RECT 116.38 46.77 117.76 47.07 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1123,7 +1123,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 27.73 123.28 28.03 ; + RECT 116.38 41.33 117.76 41.63 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1131,7 +1131,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 48.13 123.28 48.43 ; + RECT 116.38 67.17 117.76 67.47 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1139,7 +1139,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 24.33 123.28 24.63 ; + RECT 116.38 44.05 117.76 44.35 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1147,7 +1147,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 51.53 123.28 51.83 ; + RECT 116.38 36.57 117.76 36.87 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1155,7 +1155,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 22.97 123.28 23.27 ; + RECT 116.38 39.97 117.76 40.27 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1163,7 +1163,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 56.29 123.28 56.59 ; + RECT 116.38 20.25 117.76 20.55 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1171,7 +1171,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 26.37 123.28 26.67 ; + RECT 116.38 27.73 117.76 28.03 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1179,7 +1179,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 44.05 123.28 44.35 ; + RECT 116.38 69.89 117.76 70.19 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1187,7 +1187,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 38.61 123.28 38.91 ; + RECT 116.38 42.69 117.76 42.99 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1195,7 +1195,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 69.89 123.28 70.19 ; + RECT 116.38 75.33 117.76 75.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1203,7 +1203,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 82.81 123.28 83.11 ; + RECT 116.38 45.41 117.76 45.71 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1211,7 +1211,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 65.81 123.28 66.11 ; + RECT 116.38 64.45 117.76 64.75 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1219,7 +1219,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 121.9 21.61 123.28 21.91 ; + RECT 116.38 35.21 117.76 35.51 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1227,7 +1227,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1235,7 +1235,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 45.01 0 45.15 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1243,7 +1243,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1251,7 +1251,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.51 0 79.65 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1259,7 +1259,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1267,7 +1267,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 87.79 0 87.93 1.36 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1275,7 +1275,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1283,7 +1283,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 0 77.81 1.36 ; + RECT 73.53 0 73.67 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1291,7 +1291,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 85.49 0 85.63 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1299,7 +1299,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.07 0 73.21 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1307,7 +1307,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 56.05 0 56.19 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1315,7 +1315,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.75 0 76.89 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1323,7 +1323,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 79.97 0 80.11 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1331,7 +1331,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 88.71 0 88.85 1.36 ; + RECT 76.29 0 76.43 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1339,7 +1339,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1347,7 +1347,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 89.63 0 89.77 1.36 ; + RECT 88.25 0 88.39 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1355,7 +1355,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 0 84.71 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1363,7 +1363,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 87.33 0 87.47 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1371,7 +1371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1379,7 +1379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 90.55 0 90.69 1.36 ; + RECT 89.17 0 89.31 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1387,7 +1387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1403,7 +1403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1411,7 +1411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1419,7 +1419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1427,7 +1427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1435,7 +1435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1443,7 +1443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1451,7 +1451,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1459,7 +1459,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1467,7 +1467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1475,7 +1475,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1483,7 +1483,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1491,7 +1491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1499,7 +1499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1507,7 +1507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1515,7 +1515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1523,7 +1523,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1531,7 +1531,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1539,7 +1539,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1547,7 +1547,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 14.81 1.38 15.11 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1555,7 +1555,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 96.56 64.47 97.92 ; + RECT 62.49 96.56 62.63 97.92 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1563,7 +1563,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 96.56 63.55 97.92 ; + RECT 60.65 96.56 60.79 97.92 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1571,7 +1571,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 96.56 62.63 97.92 ; + RECT 59.73 96.56 59.87 97.92 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1579,7 +1579,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 96.56 61.71 97.92 ; + RECT 58.81 96.56 58.95 97.92 ; END END SC_OUT_BOT PIN VDD @@ -1587,54 +1587,54 @@ MACRO sb_1__2_ USE POWER ; PORT LAYER met1 ; - RECT 27.6 2.48 28.08 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; - RECT 27.6 7.92 28.08 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 25.76 2.48 26.24 2.96 ; + RECT 91.52 2.48 92 2.96 ; + RECT 25.76 7.92 26.24 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 122.8 13.36 123.28 13.84 ; + RECT 117.28 13.36 117.76 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 122.8 18.8 123.28 19.28 ; + RECT 117.28 18.8 117.76 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 122.8 24.24 123.28 24.72 ; + RECT 117.28 24.24 117.76 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 122.8 29.68 123.28 30.16 ; + RECT 117.28 29.68 117.76 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 122.8 35.12 123.28 35.6 ; + RECT 117.28 35.12 117.76 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 122.8 40.56 123.28 41.04 ; + RECT 117.28 40.56 117.76 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 122.8 46 123.28 46.48 ; + RECT 117.28 46 117.76 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 122.8 51.44 123.28 51.92 ; + RECT 117.28 51.44 117.76 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 122.8 56.88 123.28 57.36 ; + RECT 117.28 56.88 117.76 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 122.8 62.32 123.28 62.8 ; + RECT 117.28 62.32 117.76 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 122.8 67.76 123.28 68.24 ; + RECT 117.28 67.76 117.76 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 122.8 73.2 123.28 73.68 ; + RECT 117.28 73.2 117.76 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 122.8 78.64 123.28 79.12 ; + RECT 117.28 78.64 117.76 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 122.8 84.08 123.28 84.56 ; + RECT 117.28 84.08 117.76 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 122.8 89.52 123.28 90 ; + RECT 117.28 89.52 117.76 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 122.8 94.96 123.28 95.44 ; + RECT 117.28 94.96 117.76 95.44 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 112.86 10.88 113.46 11.48 ; - RECT 39.26 97.32 39.86 97.92 ; - RECT 68.7 97.32 69.3 97.92 ; - RECT 112.86 97.32 113.46 97.92 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 106.42 10.88 107.02 11.48 ; + RECT 36.5 97.32 37.1 97.92 ; + RECT 65.94 97.32 66.54 97.92 ; + RECT 106.42 97.32 107.02 97.92 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 120.08 22.2 123.28 25.4 ; + RECT 114.56 22.2 117.76 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 120.08 63 123.28 66.2 ; + RECT 114.56 63 117.76 66.2 ; END END VDD PIN VSS @@ -1642,191 +1642,211 @@ MACRO sb_1__2_ USE GROUND ; PORT LAYER met1 ; - RECT 27.6 0 95.68 0.24 ; - RECT 27.6 5.2 28.08 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; - RECT 0 10.64 123.28 11.12 ; + RECT 25.76 0 92 0.24 ; + RECT 25.76 5.2 26.24 5.68 ; + RECT 91.52 5.2 92 5.68 ; + RECT 0 10.64 117.76 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 122.8 16.08 123.28 16.56 ; + RECT 117.28 16.08 117.76 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 122.8 21.52 123.28 22 ; + RECT 117.28 21.52 117.76 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 122.8 26.96 123.28 27.44 ; + RECT 117.28 26.96 117.76 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 122.8 32.4 123.28 32.88 ; + RECT 117.28 32.4 117.76 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 122.8 37.84 123.28 38.32 ; + RECT 117.28 37.84 117.76 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 122.8 43.28 123.28 43.76 ; + RECT 117.28 43.28 117.76 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 122.8 48.72 123.28 49.2 ; + RECT 117.28 48.72 117.76 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 122.8 54.16 123.28 54.64 ; + RECT 117.28 54.16 117.76 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 122.8 59.6 123.28 60.08 ; + RECT 117.28 59.6 117.76 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 122.8 65.04 123.28 65.52 ; + RECT 117.28 65.04 117.76 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 122.8 70.48 123.28 70.96 ; + RECT 117.28 70.48 117.76 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 122.8 75.92 123.28 76.4 ; + RECT 117.28 75.92 117.76 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 122.8 81.36 123.28 81.84 ; + RECT 117.28 81.36 117.76 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 122.8 86.8 123.28 87.28 ; + RECT 117.28 86.8 117.76 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 122.8 92.24 123.28 92.72 ; - RECT 0 97.68 123.28 97.92 ; + RECT 117.28 92.24 117.76 92.72 ; + RECT 0 97.68 117.76 97.92 ; LAYER met4 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 10.88 10.42 11.48 ; - RECT 9.82 97.32 10.42 97.92 ; - RECT 53.98 97.32 54.58 97.92 ; - RECT 83.42 97.32 84.02 97.92 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 10.88 11.34 11.48 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 51.22 97.32 51.82 97.92 ; + RECT 80.66 97.32 81.26 97.92 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 120.08 42.6 123.28 45.8 ; + RECT 114.56 42.6 117.76 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 120.08 83.4 123.28 86.6 ; + RECT 114.56 83.4 117.76 86.6 ; END END VSS - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + PIN Test_en__FEEDTHRU_0[0] DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 63.87 96.56 64.01 97.92 ; END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + END Test_en__FEEDTHRU_0[0] + PIN Test_en__FEEDTHRU_1[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 121.9 14.13 123.28 14.43 ; + LAYER met2 ; + RECT 2.23 10.88 2.37 12.24 ; END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + END Test_en__FEEDTHRU_1[0] + PIN Test_en__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 105.27 10.88 105.41 12.24 ; + END + END Test_en__FEEDTHRU_2[0] + PIN clk__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 61.57 96.56 61.71 97.92 ; + END + END clk__FEEDTHRU_0[0] + PIN clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 10.88 3.29 12.24 ; + END + END clk__FEEDTHRU_1[0] + PIN clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 115.39 10.88 115.53 12.24 ; + END + END clk__FEEDTHRU_2[0] OBS LAYER li1 ; - RECT 0 97.835 123.28 98.005 ; - RECT 122.82 95.115 123.28 95.285 ; + RECT 0 97.835 117.76 98.005 ; + RECT 117.3 95.115 117.76 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 122.82 92.395 123.28 92.565 ; + RECT 117.3 92.395 117.76 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 122.82 89.675 123.28 89.845 ; + RECT 117.3 89.675 117.76 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 122.82 86.955 123.28 87.125 ; + RECT 116.84 86.955 117.76 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 122.36 84.235 123.28 84.405 ; + RECT 116.84 84.235 117.76 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 122.36 81.515 123.28 81.685 ; + RECT 117.3 81.515 117.76 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 122.82 78.795 123.28 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 121.44 76.075 123.28 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 119.6 73.355 123.28 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 119.6 70.635 123.28 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 122.36 67.915 123.28 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 119.6 65.195 123.28 65.365 ; + RECT 114.08 78.795 117.76 78.965 ; + RECT 0 78.795 3.68 78.965 ; + RECT 114.08 76.075 117.76 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 116.84 73.355 117.76 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 116.84 70.635 117.76 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 116.84 67.915 117.76 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 114.08 65.195 117.76 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 119.6 62.475 123.28 62.645 ; + RECT 114.08 62.475 117.76 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 122.36 59.755 123.28 59.925 ; + RECT 116.84 59.755 117.76 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 122.36 57.035 123.28 57.205 ; + RECT 114.08 57.035 117.76 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 122.36 54.315 123.28 54.485 ; + RECT 114.08 54.315 117.76 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 122.36 51.595 123.28 51.765 ; + RECT 116.84 51.595 117.76 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 122.36 48.875 123.28 49.045 ; + RECT 116.84 48.875 117.76 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 122.36 46.155 123.28 46.325 ; + RECT 116.84 46.155 117.76 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 122.36 43.435 123.28 43.605 ; + RECT 116.84 43.435 117.76 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 122.36 40.715 123.28 40.885 ; + RECT 116.84 40.715 117.76 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 122.36 37.995 123.28 38.165 ; + RECT 116.84 37.995 117.76 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 122.36 35.275 123.28 35.445 ; + RECT 116.84 35.275 117.76 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 122.36 32.555 123.28 32.725 ; + RECT 116.84 32.555 117.76 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 122.36 29.835 123.28 30.005 ; + RECT 116.84 29.835 117.76 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 122.36 27.115 123.28 27.285 ; + RECT 116.84 27.115 117.76 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 122.36 24.395 123.28 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 122.36 21.675 123.28 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 122.36 18.955 123.28 19.125 ; + RECT 116.84 24.395 117.76 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 116.84 21.675 117.76 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 116.84 18.955 117.76 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 122.36 16.235 123.28 16.405 ; + RECT 116.84 16.235 117.76 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 122.36 13.515 123.28 13.685 ; + RECT 116.84 13.515 117.76 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 92.92 10.795 123.28 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 94.76 8.075 95.68 8.245 ; - RECT 27.6 8.075 29.44 8.245 ; - RECT 94.76 5.355 95.68 5.525 ; - RECT 27.6 5.355 31.28 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; - RECT 27.6 2.635 31.28 2.805 ; - RECT 27.6 -0.085 95.68 0.085 ; + RECT 88.78 10.795 117.76 10.965 ; + RECT 0 10.795 27.6 10.965 ; + RECT 91.08 8.075 92 8.245 ; + RECT 25.76 8.075 29.44 8.245 ; + RECT 91.08 5.355 92 5.525 ; + RECT 25.76 5.355 29.44 5.525 ; + RECT 91.08 2.635 92 2.805 ; + RECT 25.76 2.635 29.44 2.805 ; + RECT 25.76 -0.085 92 0.085 ; LAYER met2 ; - RECT 83.58 97.735 83.86 98.105 ; - RECT 54.14 97.735 54.42 98.105 ; - RECT 9.98 97.735 10.26 98.105 ; - RECT 9.98 10.695 10.26 11.065 ; - RECT 62.89 1.54 63.15 1.86 ; - RECT 61.05 1.54 61.31 1.86 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - POLYGON 123 97.64 123 11.16 119.03 11.16 119.03 12.52 118.33 12.52 118.33 11.16 118.11 11.16 118.11 12.52 117.41 12.52 117.41 11.16 117.19 11.16 117.19 12.52 116.49 12.52 116.49 11.16 116.27 11.16 116.27 12.52 115.57 12.52 115.57 11.16 115.35 11.16 115.35 12.52 114.65 12.52 114.65 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.05 11.16 113.05 12.52 112.35 12.52 112.35 11.16 110.29 11.16 110.29 12.52 109.59 12.52 109.59 11.16 95.4 11.16 95.4 0.28 90.97 0.28 90.97 1.64 90.27 1.64 90.27 0.28 90.05 0.28 90.05 1.64 89.35 1.64 89.35 0.28 89.13 0.28 89.13 1.64 88.43 1.64 88.43 0.28 88.21 0.28 88.21 1.64 87.51 1.64 87.51 0.28 85.91 0.28 85.91 1.64 85.21 1.64 85.21 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 0.28 11.16 0.28 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.13 97.64 63.13 96.28 63.83 96.28 63.83 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 ; + RECT 80.82 97.735 81.1 98.105 ; + RECT 51.38 97.735 51.66 98.105 ; + RECT 10.9 97.735 11.18 98.105 ; + RECT 115.79 12.42 116.05 12.74 ; + RECT 14.59 12.42 14.85 12.74 ; + RECT 5.39 12.42 5.65 12.74 ; + RECT 10.9 10.695 11.18 11.065 ; + RECT 72.09 1.54 72.35 1.86 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + POLYGON 117.48 97.64 117.48 11.16 115.81 11.16 115.81 12.52 115.11 12.52 115.11 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.51 11.16 113.51 12.52 112.81 12.52 112.81 11.16 112.13 11.16 112.13 12.52 111.43 12.52 111.43 11.16 111.21 11.16 111.21 12.52 110.51 12.52 110.51 11.16 109.83 11.16 109.83 12.52 109.13 12.52 109.13 11.16 108.91 11.16 108.91 12.52 108.21 12.52 108.21 11.16 106.61 11.16 106.61 12.52 105.91 12.52 105.91 11.16 105.69 11.16 105.69 12.52 104.99 12.52 104.99 11.16 102.01 11.16 102.01 12.52 101.31 12.52 101.31 11.16 91.72 11.16 91.72 0.28 89.59 0.28 89.59 1.64 88.89 1.64 88.89 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 58.53 97.64 58.53 96.28 59.23 96.28 59.23 97.64 59.45 97.64 59.45 96.28 60.15 96.28 60.15 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 ; LAYER met3 ; - POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; - POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; - POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; - POLYGON 2.91 60.67 2.91 60.37 1.99 60.37 1.99 59.69 1.78 59.69 1.78 60.39 1.69 60.39 1.69 60.67 ; - POLYGON 70.99 59.31 70.99 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; - POLYGON 2.005 53.885 2.005 53.88 2.03 53.88 2.03 53.56 2.005 53.56 2.005 53.555 1.275 53.555 1.275 53.885 ; - POLYGON 121.5 43.67 121.5 43.65 122.97 43.65 122.97 43.37 118.99 43.37 118.99 43.67 ; - POLYGON 1.545 17.165 1.545 17.15 30.51 17.15 30.51 16.85 1.545 16.85 1.545 16.835 1.215 16.835 1.215 17.165 ; - POLYGON 121.63 17.16 121.63 16.84 121.25 16.84 121.25 16.85 91.39 16.85 91.39 17.15 121.25 17.15 121.25 17.16 ; - POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 122.88 97.52 122.88 84.87 121.5 84.87 121.5 83.77 122.88 83.77 122.88 83.51 121.5 83.51 121.5 82.41 122.88 82.41 122.88 82.15 121.5 82.15 121.5 81.05 122.88 81.05 122.88 80.79 121.5 80.79 121.5 79.69 122.88 79.69 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 73.31 121.5 73.31 121.5 72.21 122.88 72.21 122.88 71.95 121.5 71.95 121.5 70.85 122.88 70.85 122.88 70.59 121.5 70.59 121.5 69.49 122.88 69.49 122.88 68.55 121.5 68.55 121.5 67.45 122.88 67.45 122.88 66.51 121.5 66.51 121.5 65.41 122.88 65.41 122.88 64.47 121.5 64.47 121.5 63.37 122.88 63.37 122.88 63.11 121.5 63.11 121.5 62.01 122.88 62.01 122.88 61.75 121.5 61.75 121.5 60.65 122.88 60.65 122.88 60.39 121.5 60.39 121.5 59.29 122.88 59.29 122.88 58.35 121.5 58.35 121.5 57.25 122.88 57.25 122.88 56.99 121.5 56.99 121.5 55.89 122.88 55.89 122.88 55.63 121.5 55.63 121.5 54.53 122.88 54.53 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 52.23 121.5 52.23 121.5 51.13 122.88 51.13 122.88 50.87 121.5 50.87 121.5 49.77 122.88 49.77 122.88 48.83 121.5 48.83 121.5 47.73 122.88 47.73 122.88 46.79 121.5 46.79 121.5 45.69 122.88 45.69 122.88 44.75 121.5 44.75 121.5 43.65 122.88 43.65 122.88 43.39 121.5 43.39 121.5 42.29 122.88 42.29 122.88 41.35 121.5 41.35 121.5 40.25 122.88 40.25 122.88 39.31 121.5 39.31 121.5 38.21 122.88 38.21 122.88 37.95 121.5 37.95 121.5 36.85 122.88 36.85 122.88 36.59 121.5 36.59 121.5 35.49 122.88 35.49 122.88 35.23 121.5 35.23 121.5 34.13 122.88 34.13 122.88 33.87 121.5 33.87 121.5 32.77 122.88 32.77 122.88 32.51 121.5 32.51 121.5 31.41 122.88 31.41 122.88 31.15 121.5 31.15 121.5 30.05 122.88 30.05 122.88 29.79 121.5 29.79 121.5 28.69 122.88 28.69 122.88 28.43 121.5 28.43 121.5 27.33 122.88 27.33 122.88 27.07 121.5 27.07 121.5 25.97 122.88 25.97 122.88 25.03 121.5 25.03 121.5 23.93 122.88 23.93 122.88 23.67 121.5 23.67 121.5 22.57 122.88 22.57 122.88 22.31 121.5 22.31 121.5 21.21 122.88 21.21 122.88 20.27 121.5 20.27 121.5 19.17 122.88 19.17 122.88 18.23 121.5 18.23 121.5 17.13 122.88 17.13 122.88 14.83 121.5 14.83 121.5 13.73 122.88 13.73 122.88 11.28 95.28 11.28 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; + POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; + POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; + POLYGON 92.15 68.83 92.15 68.53 1.23 68.53 1.23 68.81 1.78 68.81 1.78 68.83 ; + POLYGON 1.545 60.685 1.545 60.67 8.43 60.67 8.43 60.37 1.545 60.37 1.545 60.355 1.215 60.355 1.215 60.685 ; + POLYGON 2.91 47.75 2.91 47.45 1.78 47.45 1.78 47.47 1.23 47.47 1.23 47.75 ; + POLYGON 7.05 28.71 7.05 28.41 1.99 28.41 1.99 27.73 1.78 27.73 1.78 28.43 1.69 28.43 1.69 28.71 ; + POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 117.36 97.52 117.36 82.15 115.98 82.15 115.98 81.05 117.36 81.05 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.03 115.98 76.03 115.98 74.93 117.36 74.93 117.36 74.67 115.98 74.67 115.98 73.57 117.36 73.57 117.36 73.31 115.98 73.31 115.98 72.21 117.36 72.21 117.36 71.95 115.98 71.95 115.98 70.85 117.36 70.85 117.36 70.59 115.98 70.59 115.98 69.49 117.36 69.49 117.36 69.23 115.98 69.23 115.98 68.13 117.36 68.13 117.36 67.87 115.98 67.87 115.98 66.77 117.36 66.77 117.36 65.15 115.98 65.15 115.98 64.05 117.36 64.05 117.36 61.75 115.98 61.75 115.98 60.65 117.36 60.65 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 56.31 115.98 56.31 115.98 55.21 117.36 55.21 117.36 54.27 115.98 54.27 115.98 53.17 117.36 53.17 117.36 52.91 115.98 52.91 115.98 51.81 117.36 51.81 117.36 51.55 115.98 51.55 115.98 50.45 117.36 50.45 117.36 50.19 115.98 50.19 115.98 49.09 117.36 49.09 117.36 48.83 115.98 48.83 115.98 47.73 117.36 47.73 117.36 47.47 115.98 47.47 115.98 46.37 117.36 46.37 117.36 46.11 115.98 46.11 115.98 45.01 117.36 45.01 117.36 44.75 115.98 44.75 115.98 43.65 117.36 43.65 117.36 43.39 115.98 43.39 115.98 42.29 117.36 42.29 117.36 42.03 115.98 42.03 115.98 40.93 117.36 40.93 117.36 40.67 115.98 40.67 115.98 39.57 117.36 39.57 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 33.19 115.98 33.19 115.98 32.09 117.36 32.09 117.36 31.83 115.98 31.83 115.98 30.73 117.36 30.73 117.36 29.79 115.98 29.79 115.98 28.69 117.36 28.69 117.36 28.43 115.98 28.43 115.98 27.33 117.36 27.33 117.36 27.07 115.98 27.07 115.98 25.97 117.36 25.97 117.36 25.03 115.98 25.03 115.98 23.93 117.36 23.93 117.36 23.67 115.98 23.67 115.98 22.57 117.36 22.57 117.36 22.31 115.98 22.31 115.98 21.21 117.36 21.21 117.36 20.95 115.98 20.95 115.98 19.85 117.36 19.85 117.36 16.19 115.98 16.19 115.98 15.09 117.36 15.09 117.36 14.83 115.98 14.83 115.98 13.73 117.36 13.73 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; LAYER met4 ; - POLYGON 122.88 97.52 122.88 11.28 113.86 11.28 113.86 11.88 112.46 11.88 112.46 11.28 95.28 11.28 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 112.46 97.52 112.46 96.92 113.86 96.92 113.86 97.52 ; + POLYGON 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 ; LAYER met5 ; - POLYGON 121.68 96.32 121.68 88.2 118.48 88.2 118.48 81.8 121.68 81.8 121.68 67.8 118.48 67.8 118.48 61.4 121.68 61.4 121.68 47.4 118.48 47.4 118.48 41 121.68 41 121.68 27 118.48 27 118.48 20.6 121.68 20.6 121.68 12.48 94.08 12.48 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; + POLYGON 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; - POLYGON 123 97.4 123 95.72 122.52 95.72 122.52 94.68 123 94.68 123 93 122.52 93 122.52 91.96 123 91.96 123 90.28 122.52 90.28 122.52 89.24 123 89.24 123 87.56 122.52 87.56 122.52 86.52 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; + POLYGON 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; LAYER li1 ; - POLYGON 123.11 97.75 123.11 11.05 95.51 11.05 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 ; + POLYGON 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 122.965 97.835 123.135 98.005 ; - RECT 122.505 97.835 122.675 98.005 ; - RECT 122.045 97.835 122.215 98.005 ; - RECT 121.585 97.835 121.755 98.005 ; - RECT 121.125 97.835 121.295 98.005 ; - RECT 120.665 97.835 120.835 98.005 ; - RECT 120.205 97.835 120.375 98.005 ; - RECT 119.745 97.835 119.915 98.005 ; - RECT 119.285 97.835 119.455 98.005 ; - RECT 118.825 97.835 118.995 98.005 ; - RECT 118.365 97.835 118.535 98.005 ; - RECT 117.905 97.835 118.075 98.005 ; RECT 117.445 97.835 117.615 98.005 ; RECT 116.985 97.835 117.155 98.005 ; RECT 116.525 97.835 116.695 98.005 ; @@ -2083,142 +2103,130 @@ MACRO sb_1__2_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 122.965 95.115 123.135 95.285 ; - RECT 122.505 95.115 122.675 95.285 ; + RECT 117.445 95.115 117.615 95.285 ; + RECT 116.985 95.115 117.155 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 122.965 92.395 123.135 92.565 ; - RECT 122.505 92.395 122.675 92.565 ; + RECT 117.445 92.395 117.615 92.565 ; + RECT 116.985 92.395 117.155 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 122.965 89.675 123.135 89.845 ; - RECT 122.505 89.675 122.675 89.845 ; + RECT 117.445 89.675 117.615 89.845 ; + RECT 116.985 89.675 117.155 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 122.965 86.955 123.135 87.125 ; - RECT 122.505 86.955 122.675 87.125 ; + RECT 117.445 86.955 117.615 87.125 ; + RECT 116.985 86.955 117.155 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 122.965 84.235 123.135 84.405 ; - RECT 122.505 84.235 122.675 84.405 ; + RECT 117.445 84.235 117.615 84.405 ; + RECT 116.985 84.235 117.155 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 122.965 81.515 123.135 81.685 ; - RECT 122.505 81.515 122.675 81.685 ; + RECT 117.445 81.515 117.615 81.685 ; + RECT 116.985 81.515 117.155 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 122.965 78.795 123.135 78.965 ; - RECT 122.505 78.795 122.675 78.965 ; + RECT 117.445 78.795 117.615 78.965 ; + RECT 116.985 78.795 117.155 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 122.965 76.075 123.135 76.245 ; - RECT 122.505 76.075 122.675 76.245 ; + RECT 117.445 76.075 117.615 76.245 ; + RECT 116.985 76.075 117.155 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 122.965 73.355 123.135 73.525 ; - RECT 122.505 73.355 122.675 73.525 ; + RECT 117.445 73.355 117.615 73.525 ; + RECT 116.985 73.355 117.155 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 122.965 70.635 123.135 70.805 ; - RECT 122.505 70.635 122.675 70.805 ; + RECT 117.445 70.635 117.615 70.805 ; + RECT 116.985 70.635 117.155 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 122.965 67.915 123.135 68.085 ; - RECT 122.505 67.915 122.675 68.085 ; + RECT 117.445 67.915 117.615 68.085 ; + RECT 116.985 67.915 117.155 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 122.965 65.195 123.135 65.365 ; - RECT 122.505 65.195 122.675 65.365 ; + RECT 117.445 65.195 117.615 65.365 ; + RECT 116.985 65.195 117.155 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 122.965 62.475 123.135 62.645 ; - RECT 122.505 62.475 122.675 62.645 ; + RECT 117.445 62.475 117.615 62.645 ; + RECT 116.985 62.475 117.155 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 122.965 59.755 123.135 59.925 ; - RECT 122.505 59.755 122.675 59.925 ; + RECT 117.445 59.755 117.615 59.925 ; + RECT 116.985 59.755 117.155 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 122.965 57.035 123.135 57.205 ; - RECT 122.505 57.035 122.675 57.205 ; + RECT 117.445 57.035 117.615 57.205 ; + RECT 116.985 57.035 117.155 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 122.965 54.315 123.135 54.485 ; - RECT 122.505 54.315 122.675 54.485 ; + RECT 117.445 54.315 117.615 54.485 ; + RECT 116.985 54.315 117.155 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 122.965 51.595 123.135 51.765 ; - RECT 122.505 51.595 122.675 51.765 ; + RECT 117.445 51.595 117.615 51.765 ; + RECT 116.985 51.595 117.155 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 122.965 48.875 123.135 49.045 ; - RECT 122.505 48.875 122.675 49.045 ; + RECT 117.445 48.875 117.615 49.045 ; + RECT 116.985 48.875 117.155 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 122.965 46.155 123.135 46.325 ; - RECT 122.505 46.155 122.675 46.325 ; + RECT 117.445 46.155 117.615 46.325 ; + RECT 116.985 46.155 117.155 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 122.965 43.435 123.135 43.605 ; - RECT 122.505 43.435 122.675 43.605 ; + RECT 117.445 43.435 117.615 43.605 ; + RECT 116.985 43.435 117.155 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 122.965 40.715 123.135 40.885 ; - RECT 122.505 40.715 122.675 40.885 ; + RECT 117.445 40.715 117.615 40.885 ; + RECT 116.985 40.715 117.155 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 122.965 37.995 123.135 38.165 ; - RECT 122.505 37.995 122.675 38.165 ; + RECT 117.445 37.995 117.615 38.165 ; + RECT 116.985 37.995 117.155 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 122.965 35.275 123.135 35.445 ; - RECT 122.505 35.275 122.675 35.445 ; + RECT 117.445 35.275 117.615 35.445 ; + RECT 116.985 35.275 117.155 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 122.965 32.555 123.135 32.725 ; - RECT 122.505 32.555 122.675 32.725 ; + RECT 117.445 32.555 117.615 32.725 ; + RECT 116.985 32.555 117.155 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 122.965 29.835 123.135 30.005 ; - RECT 122.505 29.835 122.675 30.005 ; + RECT 117.445 29.835 117.615 30.005 ; + RECT 116.985 29.835 117.155 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 122.965 27.115 123.135 27.285 ; - RECT 122.505 27.115 122.675 27.285 ; + RECT 117.445 27.115 117.615 27.285 ; + RECT 116.985 27.115 117.155 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 122.965 24.395 123.135 24.565 ; - RECT 122.505 24.395 122.675 24.565 ; + RECT 117.445 24.395 117.615 24.565 ; + RECT 116.985 24.395 117.155 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 122.965 21.675 123.135 21.845 ; - RECT 122.505 21.675 122.675 21.845 ; + RECT 117.445 21.675 117.615 21.845 ; + RECT 116.985 21.675 117.155 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 122.965 18.955 123.135 19.125 ; - RECT 122.505 18.955 122.675 19.125 ; + RECT 117.445 18.955 117.615 19.125 ; + RECT 116.985 18.955 117.155 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 122.965 16.235 123.135 16.405 ; - RECT 122.505 16.235 122.675 16.405 ; + RECT 117.445 16.235 117.615 16.405 ; + RECT 116.985 16.235 117.155 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 122.965 13.515 123.135 13.685 ; - RECT 122.505 13.515 122.675 13.685 ; + RECT 117.445 13.515 117.615 13.685 ; + RECT 116.985 13.515 117.155 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 122.965 10.795 123.135 10.965 ; - RECT 122.505 10.795 122.675 10.965 ; - RECT 122.045 10.795 122.215 10.965 ; - RECT 121.585 10.795 121.755 10.965 ; - RECT 121.125 10.795 121.295 10.965 ; - RECT 120.665 10.795 120.835 10.965 ; - RECT 120.205 10.795 120.375 10.965 ; - RECT 119.745 10.795 119.915 10.965 ; - RECT 119.285 10.795 119.455 10.965 ; - RECT 118.825 10.795 118.995 10.965 ; - RECT 118.365 10.795 118.535 10.965 ; - RECT 117.905 10.795 118.075 10.965 ; RECT 117.445 10.795 117.615 10.965 ; RECT 116.985 10.795 117.155 10.965 ; RECT 116.525 10.795 116.695 10.965 ; @@ -2475,26 +2483,18 @@ MACRO sb_1__2_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; - RECT 28.205 8.075 28.375 8.245 ; - RECT 27.745 8.075 27.915 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; - RECT 28.205 5.355 28.375 5.525 ; - RECT 27.745 5.355 27.915 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; - RECT 28.205 2.635 28.375 2.805 ; - RECT 27.745 2.635 27.915 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; + RECT 26.365 8.075 26.535 8.245 ; + RECT 25.905 8.075 26.075 8.245 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; + RECT 26.365 5.355 26.535 5.525 ; + RECT 25.905 5.355 26.075 5.525 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; + RECT 26.365 2.635 26.535 2.805 ; + RECT 25.905 2.635 26.075 2.805 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -2635,53 +2635,50 @@ MACRO sb_1__2_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; LAYER via ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 10.045 97.845 10.195 97.995 ; - RECT 115.845 12.505 115.995 12.655 ; - RECT 14.185 12.505 14.335 12.655 ; - RECT 83.645 10.805 83.795 10.955 ; - RECT 54.205 10.805 54.355 10.955 ; - RECT 10.045 10.805 10.195 10.955 ; - RECT 77.665 1.625 77.815 1.775 ; - RECT 58.805 1.625 58.955 1.775 ; - RECT 52.825 1.625 52.975 1.775 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 10.965 97.845 11.115 97.995 ; + RECT 62.485 96.145 62.635 96.295 ; + RECT 60.645 96.145 60.795 96.295 ; + RECT 110.785 12.505 110.935 12.655 ; + RECT 7.285 12.505 7.435 12.655 ; + RECT 2.225 12.505 2.375 12.655 ; + RECT 80.885 10.805 81.035 10.955 ; + RECT 51.445 10.805 51.595 10.955 ; + RECT 10.965 10.805 11.115 10.955 ; + RECT 76.285 1.625 76.435 1.775 ; + RECT 66.165 1.625 66.315 1.775 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.28 89.66 1.48 89.86 ; - RECT 121.8 74.02 122 74.22 ; - RECT 1.74 72.66 1.94 72.86 ; - RECT 121.8 61.1 122 61.3 ; - RECT 121.8 56.34 122 56.54 ; - RECT 1.28 54.3 1.48 54.5 ; - RECT 1.28 51.58 1.48 51.78 ; - RECT 1.74 48.86 1.94 49.06 ; - RECT 1.28 44.78 1.48 44.98 ; - RECT 121.8 42.74 122 42.94 ; - RECT 121.8 38.66 122 38.86 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 116.28 69.94 116.48 70.14 ; + RECT 115.82 64.5 116.02 64.7 ; + RECT 115.82 46.82 116.02 47.02 ; + RECT 1.28 40.02 1.48 40.22 ; + RECT 115.82 37.98 116.02 38.18 ; RECT 1.74 37.3 1.94 37.5 ; - RECT 1.28 34.58 1.48 34.78 ; - RECT 121.8 29.14 122 29.34 ; - RECT 121.34 27.78 121.54 27.98 ; - RECT 1.28 20.3 1.48 20.5 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 1.28 31.86 1.48 32.06 ; + RECT 1.28 14.86 1.48 15.06 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 121.34 81.5 121.54 81.7 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER OVERLAP ; - POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 123.28 97.92 123.28 10.88 95.68 10.88 95.68 0 ; + POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 117.76 97.92 117.76 10.88 92 10.88 92 0 ; END END sb_1__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef index 76a983c..42599b3 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -356,7 +356,7 @@ END unithddbl MACRO sb_2__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 97.92 ; + SIZE 92 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; @@ -371,7 +371,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -387,7 +387,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 61.49 96.56 61.79 97.92 ; + RECT 72.53 96.56 72.83 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 96.56 52.05 97.92 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; + RECT 67.55 96.56 67.69 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; + RECT 64.79 96.56 64.93 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 96.56 68.15 97.92 ; + RECT 73.07 96.56 73.21 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; + RECT 48.69 96.56 48.83 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.17 96.56 66.31 97.92 ; + RECT 56.05 96.56 56.19 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 96.56 46.15 97.92 ; + RECT 59.65 96.56 59.95 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 44.01 96.56 44.31 97.92 ; + RECT 53.21 96.56 53.51 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 96.56 78.27 97.92 ; + RECT 46.85 96.56 46.99 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 96.56 58.49 97.92 ; + RECT 49.61 96.56 49.75 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 43.63 96.56 43.77 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.77 96.56 70.91 97.92 ; + RECT 69.39 96.56 69.53 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 96.56 64.47 97.92 ; + RECT 61.11 96.56 61.25 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 96.56 81.03 97.92 ; + RECT 68.47 96.56 68.61 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.97 96.56 80.11 97.92 ; + RECT 73.99 96.56 74.13 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 71.23 96.56 71.37 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.05 96.56 79.19 97.92 ; + RECT 65.71 96.56 65.85 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,7 +531,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 85.68 18.01 87.04 ; + RECT 9.13 85.68 9.27 87.04 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,7 +539,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 85.68 12.95 87.04 ; + RECT 6.83 85.68 6.97 87.04 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] @@ -547,7 +547,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 85.68 8.35 87.04 ; + RECT 12.81 85.68 12.95 87.04 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 85.68 12.03 87.04 ; + RECT 18.33 85.68 18.47 87.04 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 85.68 6.51 87.04 ; + RECT 14.19 85.68 14.33 87.04 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 85.68 11.11 87.04 ; + RECT 7.75 85.68 7.89 87.04 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,15 +579,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 85.68 7.43 87.04 ; + RECT 16.03 85.68 16.17 87.04 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 5.45 85.68 5.59 87.04 ; + LAYER met4 ; + RECT 18.25 85.68 18.55 87.04 ; END END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] @@ -595,7 +595,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; + RECT 54.21 96.56 54.35 97.92 ; END END top_right_grid_pin_1_[0] PIN chanx_left_in[0] @@ -603,7 +603,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 11.41 1.38 11.71 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -611,7 +611,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -619,7 +619,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 10.05 1.38 10.35 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 83.49 1.38 83.79 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -683,7 +683,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -691,7 +691,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -699,7 +699,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -707,7 +707,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -715,7 +715,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -755,7 +755,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_1_[0] @@ -763,7 +763,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 63.77 1.38 64.07 ; END END left_bottom_grid_pin_1_[0] PIN left_bottom_grid_pin_3_[0] @@ -771,7 +771,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 31.13 1.38 31.43 ; END END left_bottom_grid_pin_3_[0] PIN left_bottom_grid_pin_5_[0] @@ -779,7 +779,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 43.37 1.38 43.67 ; END END left_bottom_grid_pin_5_[0] PIN left_bottom_grid_pin_7_[0] @@ -787,7 +787,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 54.25 1.38 54.55 ; END END left_bottom_grid_pin_7_[0] PIN left_bottom_grid_pin_9_[0] @@ -795,7 +795,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 61.73 1.38 62.03 ; END END left_bottom_grid_pin_9_[0] PIN left_bottom_grid_pin_11_[0] @@ -803,7 +803,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; + RECT 0 37.25 1.38 37.55 ; END END left_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -811,7 +811,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 96.56 35.49 97.92 ; + RECT 38.57 96.56 38.71 97.92 ; END END ccff_head[0] PIN chany_top_out[0] @@ -819,7 +819,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 37.65 96.56 37.79 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -827,7 +827,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 96.56 51.13 97.92 ; + RECT 50.53 96.56 50.67 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -835,7 +835,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; + RECT 63.87 96.56 64.01 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -843,7 +843,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 96.56 39.17 97.92 ; + RECT 36.73 96.56 36.87 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -851,7 +851,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 96.56 41.93 97.92 ; + RECT 57.43 96.56 57.57 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -859,7 +859,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 96.56 40.09 97.92 ; + RECT 45.93 96.56 46.07 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -867,7 +867,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 96.56 77.35 97.92 ; + RECT 62.95 96.56 63.09 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -875,7 +875,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.11 96.56 38.25 97.92 ; + RECT 42.25 96.56 42.39 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -883,7 +883,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 96.56 65.39 97.92 ; + RECT 60.19 96.56 60.33 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -891,7 +891,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 96.56 63.55 97.92 ; + RECT 39.49 96.56 39.63 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -899,7 +899,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 66.63 96.56 66.77 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -907,7 +907,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.19 96.56 37.33 97.92 ; + RECT 40.41 96.56 40.55 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -915,7 +915,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 96.56 50.21 97.92 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -923,7 +923,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; + RECT 41.33 96.56 41.47 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -931,7 +931,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.09 96.56 67.23 97.92 ; + RECT 72.15 96.56 72.29 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -939,7 +939,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 96.56 42.85 97.92 ; + RECT 47.77 96.56 47.91 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -947,7 +947,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 96.56 43.77 97.92 ; + RECT 81.81 96.56 81.95 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -955,7 +955,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 96.56 41.01 97.92 ; + RECT 44.55 96.56 44.69 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -963,7 +963,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; + RECT 70.31 96.56 70.45 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -971,7 +971,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; + RECT 32.13 96.56 32.27 97.92 ; END END chany_top_out[19] PIN chanx_left_out[0] @@ -979,7 +979,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -987,7 +987,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -995,7 +995,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1003,7 +1003,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1011,7 +1011,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1019,7 +1019,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 82.13 1.38 82.43 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1027,7 +1027,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1035,7 +1035,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1043,7 +1043,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 19.57 1.38 19.87 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1051,7 +1051,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1059,7 +1059,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1067,7 +1067,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1075,7 +1075,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1083,7 +1083,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1091,7 +1091,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1099,7 +1099,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1107,7 +1107,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1115,7 +1115,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 8.69 1.38 8.99 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1123,7 +1123,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1131,7 +1131,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1139,7 +1139,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; + RECT 0 16.85 1.38 17.15 ; END END ccff_tail[0] PIN VDD @@ -1148,51 +1148,51 @@ MACRO sb_2__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; + RECT 91.52 2.48 92 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; - RECT 27.6 89.52 28.08 90 ; - RECT 95.2 89.52 95.68 90 ; - RECT 27.6 94.96 28.08 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; + RECT 91.52 84.08 92 84.56 ; + RECT 25.76 89.52 26.24 90 ; + RECT 91.52 89.52 92 90 ; + RECT 25.76 94.96 26.24 95.44 ; + RECT 91.52 94.96 92 95.44 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 39.26 97.32 39.86 97.92 ; - RECT 68.7 97.32 69.3 97.92 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 36.5 97.32 37.1 97.92 ; + RECT 65.94 97.32 66.54 97.92 ; LAYER met5 ; RECT 0 11.32 3.2 14.52 ; - RECT 92.48 11.32 95.68 14.52 ; + RECT 88.8 11.32 92 14.52 ; RECT 0 52.12 3.2 55.32 ; - RECT 92.48 52.12 95.68 55.32 ; + RECT 88.8 52.12 92 55.32 ; END END VDD PIN VSS @@ -1200,171 +1200,159 @@ MACRO sb_2__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 95.68 0.24 ; + RECT 0 0 92 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; + RECT 91.52 5.2 92 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 95.2 10.64 95.68 11.12 ; + RECT 91.52 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; - RECT 0 86.8 95.68 87.28 ; - RECT 27.6 92.24 28.08 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 27.6 97.68 95.68 97.92 ; + RECT 91.52 81.36 92 81.84 ; + RECT 0 86.8 92 87.28 ; + RECT 25.76 92.24 26.24 92.72 ; + RECT 91.52 92.24 92 92.72 ; + RECT 25.76 97.68 92 97.92 ; LAYER met4 ; - RECT 9.82 0 10.42 0.6 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 86.44 10.42 87.04 ; - RECT 53.98 97.32 54.58 97.92 ; - RECT 83.42 97.32 84.02 97.92 ; + RECT 10.74 0 11.34 0.6 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 86.44 11.34 87.04 ; + RECT 51.22 97.32 51.82 97.92 ; + RECT 80.66 97.32 81.26 97.92 ; LAYER met5 ; RECT 0 31.72 3.2 34.92 ; - RECT 92.48 31.72 95.68 34.92 ; + RECT 88.8 31.72 92 34.92 ; RECT 0 72.52 3.2 75.72 ; - RECT 92.48 72.52 95.68 75.72 ; + RECT 88.8 72.52 92 75.72 ; END END VSS OBS LAYER li1 ; - RECT 27.6 97.835 95.68 98.005 ; - RECT 92 95.115 95.68 95.285 ; - RECT 27.6 95.115 31.28 95.285 ; - RECT 92 92.395 95.68 92.565 ; - RECT 27.6 92.395 31.28 92.565 ; - RECT 95.22 89.675 95.68 89.845 ; - RECT 27.6 89.675 31.28 89.845 ; - RECT 95.22 86.955 95.68 87.125 ; + RECT 25.76 97.835 92 98.005 ; + RECT 91.54 95.115 92 95.285 ; + RECT 25.76 95.115 29.44 95.285 ; + RECT 90.16 92.395 92 92.565 ; + RECT 25.76 92.395 29.44 92.565 ; + RECT 90.16 89.675 92 89.845 ; + RECT 25.76 89.675 27.6 89.845 ; + RECT 91.08 86.955 92 87.125 ; RECT 0 86.955 29.44 87.125 ; - RECT 95.22 84.235 95.68 84.405 ; + RECT 91.08 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 94.76 81.515 95.68 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 94.76 78.795 95.68 78.965 ; + RECT 91.54 81.515 92 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 94.76 76.075 95.68 76.245 ; + RECT 91.08 76.075 92 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 94.76 73.355 95.68 73.525 ; + RECT 91.08 73.355 92 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 95.22 70.635 95.68 70.805 ; + RECT 88.32 70.635 92 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 94.76 67.915 95.68 68.085 ; + RECT 88.32 67.915 92 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 94.76 65.195 95.68 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 95.22 62.475 95.68 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 92 59.755 95.68 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 92 57.035 95.68 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 93.84 54.315 95.68 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 95.22 51.595 95.68 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 95.22 48.875 95.68 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 92 46.155 95.68 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 92 43.435 95.68 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 93.84 40.715 95.68 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 93.84 37.995 95.68 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 95.22 35.275 95.68 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 95.22 32.555 95.68 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 95.22 29.835 95.68 30.005 ; + RECT 91.54 62.475 92 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 88.32 59.755 92 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 88.32 57.035 92 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 91.54 54.315 92 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 91.54 51.595 92 51.765 ; + RECT 0 51.595 1.84 51.765 ; + RECT 91.08 48.875 92 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 91.08 46.155 92 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 90.16 43.435 92 43.605 ; + RECT 0 43.435 3.68 43.605 ; + RECT 90.16 40.715 92 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 91.54 37.995 92 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 91.54 35.275 92 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 91.08 32.555 92 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 91.08 29.835 92 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 95.22 27.115 95.68 27.285 ; + RECT 88.32 27.115 92 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 95.22 24.395 95.68 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 95.22 21.675 95.68 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 95.22 18.955 95.68 19.125 ; + RECT 88.32 24.395 92 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 91.54 21.675 92 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 91.54 18.955 92 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 95.22 16.235 95.68 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 95.22 13.515 95.68 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 95.22 10.795 95.68 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 95.22 8.075 95.68 8.245 ; + RECT 91.54 16.235 92 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 91.54 13.515 92 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 91.54 10.795 92 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 91.54 8.075 92 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 95.22 5.355 95.68 5.525 ; + RECT 91.54 5.355 92 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; + RECT 91.54 2.635 92 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 95.68 0.085 ; + RECT 0 -0.085 92 0.085 ; LAYER met3 ; - POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; - POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; - POLYGON 10.285 87.205 10.285 87.2 10.5 87.2 10.5 86.88 10.285 86.88 10.285 86.875 9.955 86.875 9.955 86.88 9.74 86.88 9.74 87.2 9.955 87.2 9.955 87.205 ; - POLYGON 11.65 66.11 11.65 65.81 1.99 65.81 1.99 65.13 1.78 65.13 1.78 65.83 1.69 65.83 1.69 66.11 ; - POLYGON 7.51 59.31 7.51 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; - POLYGON 1.99 45.03 1.99 44.35 6.59 44.35 6.59 44.05 1.69 44.05 1.69 44.33 1.78 44.33 1.78 45.03 ; - POLYGON 1.99 39.59 1.99 38.91 21.77 38.91 21.77 38.61 1.69 38.61 1.69 38.89 1.78 38.89 1.78 39.59 ; - POLYGON 2.005 28.045 2.005 28.03 15.79 28.03 15.79 27.73 2.005 27.73 2.005 27.715 1.675 27.715 1.675 28.045 ; - POLYGON 6.59 25.99 6.59 25.69 1.99 25.69 1.99 25.01 1.78 25.01 1.78 25.71 1.69 25.71 1.69 25.99 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 10.285 0.165 10.285 0.16 10.5 0.16 10.5 -0.16 10.285 -0.16 10.285 -0.165 9.955 -0.165 9.955 -0.16 9.74 -0.16 9.74 0.16 9.955 0.16 9.955 0.165 ; - POLYGON 95.28 97.52 95.28 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 28 86.64 28 97.52 ; + POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; + POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; + POLYGON 19.47 76.99 19.47 76.69 1.78 76.69 1.78 76.71 1.23 76.71 1.23 76.99 ; + POLYGON 25.91 59.31 25.91 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ; + POLYGON 91.6 97.52 91.6 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 26.16 86.64 26.16 97.52 ; LAYER met2 ; - RECT 83.58 97.735 83.86 98.105 ; - RECT 54.14 97.735 54.42 98.105 ; - RECT 68.41 96.06 68.67 96.38 ; - RECT 49.55 96.06 49.81 96.38 ; - RECT 9.98 86.855 10.26 87.225 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - RECT 9.98 -0.185 10.26 0.185 ; - POLYGON 95.4 97.64 95.4 0.28 0.28 0.28 0.28 86.76 5.17 86.76 5.17 85.4 5.87 85.4 5.87 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 7.93 86.76 7.93 85.4 8.63 85.4 8.63 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 11.61 86.76 11.61 85.4 12.31 85.4 12.31 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 17.59 86.76 17.59 85.4 18.29 85.4 18.29 86.76 27.88 86.76 27.88 97.64 35.07 97.64 35.07 96.28 35.77 96.28 35.77 97.64 36.91 97.64 36.91 96.28 37.61 96.28 37.61 97.64 37.83 97.64 37.83 96.28 38.53 96.28 38.53 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.51 97.64 41.51 96.28 42.21 96.28 42.21 97.64 42.43 97.64 42.43 96.28 43.13 96.28 43.13 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 63.13 97.64 63.13 96.28 63.83 96.28 63.83 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 64.97 97.64 64.97 96.28 65.67 96.28 65.67 97.64 65.89 97.64 65.89 96.28 66.59 96.28 66.59 97.64 66.81 97.64 66.81 96.28 67.51 96.28 67.51 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 70.49 97.64 70.49 96.28 71.19 96.28 71.19 97.64 76.93 97.64 76.93 96.28 77.63 96.28 77.63 97.64 77.85 97.64 77.85 96.28 78.55 96.28 78.55 97.64 78.77 97.64 78.77 96.28 79.47 96.28 79.47 97.64 79.69 97.64 79.69 96.28 80.39 96.28 80.39 97.64 80.61 97.64 80.61 96.28 81.31 96.28 81.31 97.64 ; + RECT 80.82 97.735 81.1 98.105 ; + RECT 51.38 97.735 51.66 98.105 ; + RECT 38.05 96.06 38.31 96.38 ; + RECT 10.9 86.855 11.18 87.225 ; + RECT 15.51 85.18 15.77 85.5 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + RECT 10.9 -0.185 11.18 0.185 ; + POLYGON 91.72 97.64 91.72 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 7.47 86.76 7.47 85.4 8.17 85.4 8.17 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 15.75 86.76 15.75 85.4 16.45 85.4 16.45 86.76 18.05 86.76 18.05 85.4 18.75 85.4 18.75 86.76 26.04 86.76 26.04 97.64 31.85 97.64 31.85 96.28 32.55 96.28 32.55 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.65 97.64 45.65 96.28 46.35 96.28 46.35 97.64 46.57 97.64 46.57 96.28 47.27 96.28 47.27 97.64 47.49 97.64 47.49 96.28 48.19 96.28 48.19 97.64 48.41 97.64 48.41 96.28 49.11 96.28 49.11 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.11 97.64 69.11 96.28 69.81 96.28 69.81 97.64 70.03 97.64 70.03 96.28 70.73 96.28 70.73 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 71.87 97.64 71.87 96.28 72.57 96.28 72.57 97.64 72.79 97.64 72.79 96.28 73.49 96.28 73.49 97.64 73.71 97.64 73.71 96.28 74.41 96.28 74.41 97.64 81.53 97.64 81.53 96.28 82.23 96.28 82.23 97.64 ; LAYER met4 ; - POLYGON 95.28 97.52 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 10.82 0.4 10.82 1 9.42 1 9.42 0.4 0.4 0.4 0.4 86.64 9.42 86.64 9.42 86.04 10.82 86.04 10.82 86.64 28 86.64 28 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 43.61 97.52 43.61 96.16 44.71 96.16 44.71 97.52 45.45 97.52 45.45 96.16 46.55 96.16 46.55 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; + POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 17.85 86.64 17.85 85.28 18.95 85.28 18.95 86.64 26.16 86.64 26.16 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 52.81 97.52 52.81 96.16 53.91 96.16 53.91 97.52 59.25 97.52 59.25 96.16 60.35 96.16 60.35 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 72.13 97.52 72.13 96.16 73.23 96.16 73.23 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; LAYER met5 ; - POLYGON 94.08 96.32 94.08 77.32 90.88 77.32 90.88 70.92 94.08 70.92 94.08 56.92 90.88 56.92 90.88 50.52 94.08 50.52 94.08 36.52 90.88 36.52 90.88 30.12 94.08 30.12 94.08 16.12 90.88 16.12 90.88 9.72 94.08 9.72 94.08 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 29.2 85.44 29.2 96.32 ; + POLYGON 90.4 96.32 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; LAYER met1 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 27.88 87.56 27.88 89.24 28.36 89.24 28.36 90.28 27.88 90.28 27.88 91.96 28.36 91.96 28.36 93 27.88 93 27.88 94.68 28.36 94.68 28.36 95.72 27.88 95.72 27.88 97.4 ; - POLYGON 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 94.92 11.4 94.92 10.36 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 ; + POLYGON 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 95.51 97.75 95.51 0.17 0.17 0.17 0.17 86.87 27.77 86.87 27.77 97.75 ; + POLYGON 91.83 97.75 91.83 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; LAYER mcon ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -1505,26 +1493,22 @@ MACRO sb_2__0_ RECT 28.665 97.835 28.835 98.005 ; RECT 28.205 97.835 28.375 98.005 ; RECT 27.745 97.835 27.915 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; - RECT 28.205 95.115 28.375 95.285 ; - RECT 27.745 95.115 27.915 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; - RECT 28.205 92.395 28.375 92.565 ; - RECT 27.745 92.395 27.915 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; - RECT 28.205 89.675 28.375 89.845 ; - RECT 27.745 89.675 27.915 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; - RECT 94.445 86.955 94.615 87.125 ; - RECT 93.985 86.955 94.155 87.125 ; - RECT 93.525 86.955 93.695 87.125 ; - RECT 93.065 86.955 93.235 87.125 ; - RECT 92.605 86.955 92.775 87.125 ; - RECT 92.145 86.955 92.315 87.125 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; + RECT 26.365 95.115 26.535 95.285 ; + RECT 25.905 95.115 26.075 95.285 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; + RECT 26.365 92.395 26.535 92.565 ; + RECT 25.905 92.395 26.075 92.565 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; + RECT 26.365 89.675 26.535 89.845 ; + RECT 25.905 89.675 26.075 89.845 ; RECT 91.685 86.955 91.855 87.125 ; RECT 91.225 86.955 91.395 87.125 ; RECT 90.765 86.955 90.935 87.125 ; @@ -1725,138 +1709,130 @@ MACRO sb_2__0_ RECT 1.065 86.955 1.235 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -2058,43 +2034,37 @@ MACRO sb_2__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 67.085 96.145 67.235 96.295 ; - RECT 46.385 96.145 46.535 96.295 ; - RECT 38.105 96.145 38.255 96.295 ; - RECT 83.645 86.965 83.795 87.115 ; - RECT 54.205 86.965 54.355 87.115 ; - RECT 10.045 86.965 10.195 87.115 ; - RECT 8.205 85.265 8.355 85.415 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; - RECT 10.045 -0.075 10.195 0.075 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 69.385 96.145 69.535 96.295 ; + RECT 80.885 86.965 81.035 87.115 ; + RECT 51.445 86.965 51.595 87.115 ; + RECT 10.965 86.965 11.115 87.115 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; + RECT 10.965 -0.075 11.115 0.075 ; LAYER via2 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 86.94 10.22 87.14 ; - RECT 1.28 76.74 1.48 76.94 ; - RECT 1.74 74.02 1.94 74.22 ; - RECT 1.74 61.1 1.94 61.3 ; - RECT 1.28 57.02 1.48 57.22 ; - RECT 1.28 52.94 1.48 53.14 ; - RECT 1.28 33.9 1.48 34.1 ; - RECT 1.28 26.42 1.48 26.62 ; - RECT 1.74 20.3 1.94 20.5 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 86.94 11.14 87.14 ; + RECT 1.28 70.62 1.48 70.82 ; + RECT 1.28 46.14 1.48 46.34 ; + RECT 1.28 40.7 1.48 40.9 ; + RECT 1.28 23.02 1.48 23.22 ; + RECT 1.28 16.9 1.48 17.1 ; RECT 1.28 13.5 1.48 13.7 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; - RECT 10.02 -0.1 10.22 0.1 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; + RECT 10.94 -0.1 11.14 0.1 ; LAYER via3 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 86.94 10.22 87.14 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; - RECT 10.02 -0.1 10.22 0.1 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 86.94 11.14 87.14 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; + RECT 10.94 -0.1 11.14 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 87.04 27.6 87.04 27.6 97.92 95.68 97.92 95.68 0 ; + POLYGON 0 0 0 87.04 25.76 87.04 25.76 97.92 92 97.92 92 0 ; END END sb_2__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef index 3bd2d87..44def72 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_2__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 108.8 ; + SIZE 92 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 35.21 1.38 35.51 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 107.44 61.25 108.8 ; + RECT 59.27 107.44 59.41 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -387,7 +387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 61.49 107.44 61.79 108.8 ; + RECT 72.53 107.44 72.83 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 107.44 52.05 108.8 ; + RECT 52.37 107.44 52.51 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 107.44 57.57 108.8 ; + RECT 67.55 107.44 67.69 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 107.44 62.17 108.8 ; + RECT 64.79 107.44 64.93 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 107.44 68.15 108.8 ; + RECT 73.07 107.44 73.21 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 107.44 49.29 108.8 ; + RECT 48.69 107.44 48.83 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.17 107.44 66.31 108.8 ; + RECT 56.05 107.44 56.19 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 107.44 46.15 108.8 ; + RECT 59.65 107.44 59.95 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 44.01 107.44 44.31 108.8 ; + RECT 53.21 107.44 53.51 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 107.44 78.27 108.8 ; + RECT 46.85 107.44 46.99 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 107.44 58.49 108.8 ; + RECT 49.61 107.44 49.75 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 107.44 59.41 108.8 ; + RECT 43.63 107.44 43.77 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.77 107.44 70.91 108.8 ; + RECT 69.39 107.44 69.53 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.33 107.44 64.47 108.8 ; + RECT 61.11 107.44 61.25 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 107.44 81.03 108.8 ; + RECT 68.47 107.44 68.61 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.97 107.44 80.11 108.8 ; + RECT 73.99 107.44 74.13 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 107.44 60.33 108.8 ; + RECT 71.23 107.44 71.37 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.05 107.44 79.19 108.8 ; + RECT 65.71 107.44 65.85 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,7 +531,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 96.56 18.01 97.92 ; + RECT 9.13 96.56 9.27 97.92 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,7 +539,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 96.56 12.95 97.92 ; + RECT 6.83 96.56 6.97 97.92 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] @@ -547,15 +547,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 96.56 8.35 97.92 ; + RECT 12.81 96.56 12.95 97.92 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 11.89 96.56 12.03 97.92 ; + LAYER met4 ; + RECT 18.25 96.56 18.55 97.92 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 96.56 6.51 97.92 ; + RECT 14.19 96.56 14.33 97.92 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 96.56 11.11 97.92 ; + RECT 7.75 96.56 7.89 97.92 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,7 +579,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 96.56 7.43 97.92 ; + RECT 16.03 96.56 16.17 97.92 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] @@ -587,7 +587,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 96.56 5.59 97.92 ; + RECT 18.33 96.56 18.47 97.92 ; END END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] @@ -595,15 +595,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 107.44 44.69 108.8 ; + RECT 54.21 107.44 54.35 108.8 ; END END top_right_grid_pin_1_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 55.59 0 55.73 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -611,7 +611,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -619,7 +619,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; + RECT 56.89 0 57.19 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.97 0 80.11 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 0 84.71 1.36 ; + RECT 72.61 0 72.75 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -699,7 +699,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -707,7 +707,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 44.09 0 44.23 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 0 68.15 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; + RECT 73.53 0 73.67 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,7 +755,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 0 81.03 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -763,23 +763,23 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END bottom_right_grid_pin_1_[0] PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 11.43 10.88 11.57 12.24 ; + LAYER met4 ; + RECT 12.73 10.88 13.03 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; + LAYER met4 ; + RECT 9.05 10.88 9.35 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -787,7 +787,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.35 10.88 12.49 12.24 ; + RECT 27.99 0 28.13 1.36 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -795,7 +795,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 10.88 14.33 12.24 ; + RECT 7.29 10.88 7.43 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -803,7 +803,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] @@ -811,23 +811,23 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 10.88 18.01 12.24 ; + RECT 15.11 10.88 15.25 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 10.88 5.67 12.24 ; + LAYER met2 ; + RECT 8.21 10.88 8.35 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 11.81 10.88 12.11 12.24 ; + LAYER met2 ; + RECT 10.05 10.88 10.19 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -835,7 +835,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -843,7 +843,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 84.17 1.38 84.47 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -859,7 +859,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -867,7 +867,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -875,7 +875,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -883,7 +883,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 90.97 1.38 91.27 ; + RECT 0 89.61 1.38 89.91 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -891,7 +891,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -899,7 +899,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -907,7 +907,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 84.17 1.38 84.47 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -915,7 +915,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 88.25 1.38 88.55 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -923,7 +923,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 86.89 1.38 87.19 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -931,7 +931,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 92.33 1.38 92.63 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -939,7 +939,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -947,7 +947,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 86.89 1.38 87.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -955,7 +955,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -963,7 +963,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -971,7 +971,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -979,7 +979,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -987,7 +987,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_34_[0] @@ -995,7 +995,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; + RECT 28.91 0 29.05 1.36 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] @@ -1003,7 +1003,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 10.88 13.41 12.24 ; + RECT 12.81 10.88 12.95 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -1019,7 +1019,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 10.88 6.05 12.24 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1027,15 +1027,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 10.88 7.89 12.24 ; + RECT 6.37 10.88 6.51 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; + LAYER met4 ; + RECT 4.45 10.88 4.75 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -1043,7 +1043,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; + RECT 11.89 10.88 12.03 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1051,7 +1051,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 10.88 6.97 12.24 ; + RECT 16.03 10.88 16.17 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1059,7 +1059,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 107.44 35.49 108.8 ; + RECT 38.57 107.44 38.71 108.8 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1067,7 +1067,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 107.44 53.43 108.8 ; + RECT 37.65 107.44 37.79 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1075,7 +1075,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 107.44 51.13 108.8 ; + RECT 50.53 107.44 50.67 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1083,7 +1083,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 107.44 55.27 108.8 ; + RECT 63.87 107.44 64.01 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1091,7 +1091,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 107.44 39.17 108.8 ; + RECT 36.73 107.44 36.87 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1099,7 +1099,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 107.44 41.93 108.8 ; + RECT 57.43 107.44 57.57 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1107,7 +1107,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 107.44 40.09 108.8 ; + RECT 45.93 107.44 46.07 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1115,7 +1115,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 107.44 77.35 108.8 ; + RECT 62.95 107.44 63.09 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1123,7 +1123,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.11 107.44 38.25 108.8 ; + RECT 42.25 107.44 42.39 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1131,7 +1131,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 107.44 65.39 108.8 ; + RECT 60.19 107.44 60.33 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1139,7 +1139,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 107.44 63.55 108.8 ; + RECT 39.49 107.44 39.63 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1147,7 +1147,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 107.44 48.37 108.8 ; + RECT 66.63 107.44 66.77 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1155,7 +1155,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.19 107.44 37.33 108.8 ; + RECT 40.41 107.44 40.55 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1163,7 +1163,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 107.44 50.21 108.8 ; + RECT 62.03 107.44 62.17 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1171,7 +1171,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 107.44 47.45 108.8 ; + RECT 41.33 107.44 41.47 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1179,7 +1179,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.09 107.44 67.23 108.8 ; + RECT 72.15 107.44 72.29 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1187,7 +1187,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 107.44 42.85 108.8 ; + RECT 47.77 107.44 47.91 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1195,7 +1195,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 107.44 43.77 108.8 ; + RECT 81.81 107.44 81.95 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1203,7 +1203,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 107.44 41.01 108.8 ; + RECT 44.55 107.44 44.69 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1211,7 +1211,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 107.44 46.53 108.8 ; + RECT 70.31 107.44 70.45 108.8 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1219,7 +1219,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 107.44 45.61 108.8 ; + RECT 32.13 107.44 32.27 108.8 ; END END chany_top_out[19] PIN chany_bottom_out[0] @@ -1227,15 +1227,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 79.05 0 79.19 1.36 ; + LAYER met4 ; + RECT 58.73 0 59.03 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1243,7 +1243,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1251,7 +1251,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1259,7 +1259,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 37.19 0 37.33 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1267,7 +1267,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1275,7 +1275,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1283,7 +1283,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1291,7 +1291,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1299,7 +1299,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 38.11 0 38.25 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1307,7 +1307,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1315,7 +1315,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 33.97 0 34.11 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1323,7 +1323,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 58.81 0 58.95 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1331,7 +1331,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1339,7 +1339,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1347,7 +1347,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1355,7 +1355,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1363,7 +1363,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1371,7 +1371,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 70.77 0 70.91 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1379,7 +1379,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1387,7 +1387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1395,7 +1395,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1403,7 +1403,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1411,7 +1411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.17 1.38 67.47 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1419,7 +1419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1427,7 +1427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 88.25 1.38 88.55 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1435,7 +1435,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1443,7 +1443,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1451,7 +1451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1459,7 +1459,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1467,7 +1467,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1475,7 +1475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1483,7 +1483,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1491,7 +1491,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 90.97 1.38 91.27 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1499,7 +1499,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1507,7 +1507,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1515,7 +1515,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1523,7 +1523,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1531,7 +1531,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1539,7 +1539,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1547,7 +1547,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; + RECT 0 76.69 1.38 76.99 ; END END ccff_tail[0] PIN VDD @@ -1555,56 +1555,56 @@ MACRO sb_2__1_ USE POWER ; PORT LAYER met1 ; - RECT 27.6 2.48 28.08 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; - RECT 27.6 7.92 28.08 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 25.76 2.48 26.24 2.96 ; + RECT 91.52 2.48 92 2.96 ; + RECT 25.76 7.92 26.24 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; + RECT 91.52 84.08 92 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 95.2 89.52 95.68 90 ; + RECT 91.52 89.52 92 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; - RECT 27.6 100.4 28.08 100.88 ; - RECT 95.2 100.4 95.68 100.88 ; - RECT 27.6 105.84 28.08 106.32 ; - RECT 95.2 105.84 95.68 106.32 ; + RECT 91.52 94.96 92 95.44 ; + RECT 25.76 100.4 26.24 100.88 ; + RECT 91.52 100.4 92 100.88 ; + RECT 25.76 105.84 26.24 106.32 ; + RECT 91.52 105.84 92 106.32 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 39.26 108.2 39.86 108.8 ; - RECT 68.7 108.2 69.3 108.8 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 36.5 108.2 37.1 108.8 ; + RECT 65.94 108.2 66.54 108.8 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 92.48 22.2 95.68 25.4 ; + RECT 88.8 22.2 92 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 92.48 63 95.68 66.2 ; + RECT 88.8 63 92 66.2 ; END END VDD PIN VSS @@ -1612,56 +1612,56 @@ MACRO sb_2__1_ USE GROUND ; PORT LAYER met1 ; - RECT 27.6 0 95.68 0.24 ; - RECT 27.6 5.2 28.08 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; - RECT 0 10.64 95.68 11.12 ; + RECT 25.76 0 92 0.24 ; + RECT 25.76 5.2 26.24 5.68 ; + RECT 91.52 5.2 92 5.68 ; + RECT 0 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; + RECT 91.52 81.36 92 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 95.2 86.8 95.68 87.28 ; + RECT 91.52 86.8 92 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 0 97.68 95.68 98.16 ; - RECT 27.6 103.12 28.08 103.6 ; - RECT 95.2 103.12 95.68 103.6 ; - RECT 27.6 108.56 95.68 108.8 ; + RECT 91.52 92.24 92 92.72 ; + RECT 0 97.68 92 98.16 ; + RECT 25.76 103.12 26.24 103.6 ; + RECT 91.52 103.12 92 103.6 ; + RECT 25.76 108.56 92 108.8 ; LAYER met4 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 10.88 10.42 11.48 ; - RECT 9.82 97.32 10.42 97.92 ; - RECT 53.98 108.2 54.58 108.8 ; - RECT 83.42 108.2 84.02 108.8 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 10.88 11.34 11.48 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 51.22 108.2 51.82 108.8 ; + RECT 80.66 108.2 81.26 108.8 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 92.48 42.6 95.68 45.8 ; + RECT 88.8 42.6 92 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 92.48 83.4 95.68 86.6 ; + RECT 88.8 83.4 92 86.6 ; END END VSS PIN Test_en__FEEDTHRU_0[0] @@ -1669,7 +1669,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 10.88 2.37 12.24 ; + RECT 2.23 96.56 2.37 97.92 ; END END Test_en__FEEDTHRU_0[0] PIN Test_en__FEEDTHRU_1[0] @@ -1677,138 +1677,143 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; + RECT 2.23 10.88 2.37 12.24 ; END END Test_en__FEEDTHRU_1[0] + PIN clk__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 96.56 3.29 97.92 ; + END + END clk__FEEDTHRU_0[0] + PIN clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 10.88 3.29 12.24 ; + END + END clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 27.6 108.715 95.68 108.885 ; - RECT 94.76 105.995 95.68 106.165 ; - RECT 27.6 105.995 31.28 106.165 ; - RECT 94.76 103.275 95.68 103.445 ; - RECT 27.6 103.275 29.44 103.445 ; - RECT 95.22 100.555 95.68 100.725 ; - RECT 27.6 100.555 29.44 100.725 ; - RECT 95.22 97.835 95.68 98.005 ; - RECT 0 97.835 29.44 98.005 ; - RECT 95.22 95.115 95.68 95.285 ; + RECT 25.76 108.715 92 108.885 ; + RECT 91.54 105.995 92 106.165 ; + RECT 25.76 105.995 29.44 106.165 ; + RECT 91.08 103.275 92 103.445 ; + RECT 25.76 103.275 27.6 103.445 ; + RECT 91.08 100.555 92 100.725 ; + RECT 25.76 100.555 27.6 100.725 ; + RECT 91.54 97.835 92 98.005 ; + RECT 0 97.835 27.6 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 93.84 92.395 95.68 92.565 ; + RECT 88.32 92.395 92 92.565 ; RECT 0 92.395 1.84 92.565 ; - RECT 93.84 89.675 95.68 89.845 ; + RECT 88.32 89.675 92 89.845 ; RECT 0 89.675 1.84 89.845 ; - RECT 95.22 86.955 95.68 87.125 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 1.84 87.125 ; - RECT 92 84.235 95.68 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 1.84 84.405 ; - RECT 92 81.515 95.68 81.685 ; + RECT 91.08 81.515 92 81.685 ; RECT 0 81.515 1.84 81.685 ; - RECT 94.76 78.795 95.68 78.965 ; + RECT 91.08 78.795 92 78.965 ; RECT 0 78.795 1.84 78.965 ; - RECT 94.76 76.075 95.68 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 94.76 73.355 95.68 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 92 70.635 95.68 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 92 67.915 95.68 68.085 ; + RECT 91.54 76.075 92 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 91.54 73.355 92 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 90.16 70.635 92 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 90.16 67.915 92 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 92 65.195 95.68 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 92 62.475 95.68 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 95.22 59.755 95.68 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 95.22 57.035 95.68 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 95.22 54.315 95.68 54.485 ; + RECT 88.32 65.195 92 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 88.32 62.475 92 62.645 ; + RECT 0 62.475 3.68 62.645 ; + RECT 91.08 59.755 92 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 91.08 57.035 92 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 91.54 54.315 92 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 95.22 51.595 95.68 51.765 ; + RECT 91.54 51.595 92 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 94.76 48.875 95.68 49.045 ; + RECT 91.08 48.875 92 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 94.76 46.155 95.68 46.325 ; + RECT 91.08 46.155 92 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 95.22 43.435 95.68 43.605 ; + RECT 91.54 43.435 92 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 94.76 40.715 95.68 40.885 ; + RECT 91.54 40.715 92 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 94.76 37.995 95.68 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 95.22 35.275 95.68 35.445 ; + RECT 91.08 37.995 92 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 91.08 35.275 92 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 94.76 32.555 95.68 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 94.76 29.835 95.68 30.005 ; + RECT 91.54 32.555 92 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 91.54 29.835 92 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 92 27.115 95.68 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 92 24.395 95.68 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 95.22 21.675 95.68 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 92 18.955 95.68 19.125 ; + RECT 91.54 27.115 92 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 91.54 24.395 92 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 91.08 21.675 92 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 91.08 18.955 92 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 92 16.235 95.68 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 94.76 13.515 95.68 13.685 ; + RECT 91.54 16.235 92 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 94.76 10.795 95.68 10.965 ; + RECT 91.54 10.795 92 10.965 ; RECT 0 10.795 29.44 10.965 ; - RECT 95.22 8.075 95.68 8.245 ; - RECT 27.6 8.075 29.44 8.245 ; - RECT 95.22 5.355 95.68 5.525 ; - RECT 27.6 5.355 29.44 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; - RECT 27.6 2.635 31.28 2.805 ; - RECT 27.6 -0.085 95.68 0.085 ; + RECT 91.54 8.075 92 8.245 ; + RECT 25.76 8.075 27.6 8.245 ; + RECT 91.54 5.355 92 5.525 ; + RECT 25.76 5.355 27.6 5.525 ; + RECT 91.54 2.635 92 2.805 ; + RECT 25.76 2.635 29.44 2.805 ; + RECT 25.76 -0.085 92 0.085 ; LAYER met3 ; - POLYGON 83.885 108.965 83.885 108.96 84.1 108.96 84.1 108.64 83.885 108.64 83.885 108.635 83.555 108.635 83.555 108.64 83.34 108.64 83.34 108.96 83.555 108.96 83.555 108.965 ; - POLYGON 54.445 108.965 54.445 108.96 54.66 108.96 54.66 108.64 54.445 108.64 54.445 108.635 54.115 108.635 54.115 108.64 53.9 108.64 53.9 108.96 54.115 108.96 54.115 108.965 ; - POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; - POLYGON 5.67 74.27 5.67 73.97 1.99 73.97 1.99 73.29 1.78 73.29 1.78 73.99 1.69 73.99 1.69 74.27 ; - POLYGON 2.03 62.72 2.03 62.71 9.35 62.71 9.35 62.41 2.03 62.41 2.03 62.4 1.65 62.4 1.65 62.72 ; - POLYGON 2.005 58.645 2.005 58.63 2.91 58.63 2.91 58.33 2.005 58.33 2.005 58.315 1.675 58.315 1.675 58.645 ; - POLYGON 14.41 51.15 14.41 50.85 1.78 50.85 1.78 50.87 1.23 50.87 1.23 51.15 ; - POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 95.28 108.4 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 97.52 28 97.52 28 108.4 ; + POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; + POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; + POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; + POLYGON 1.99 88.55 1.99 87.87 8.89 87.87 8.89 87.57 1.69 87.57 1.69 87.85 1.78 87.85 1.78 88.55 ; + RECT 1.65 84.84 2.46 85.16 ; + POLYGON 2.45 82.43 2.45 82.13 0.77 82.13 0.77 82.41 1.78 82.41 1.78 82.43 ; + POLYGON 2.005 76.325 2.005 76.31 5.67 76.31 5.67 76.01 2.005 76.01 2.005 75.995 1.675 75.995 1.675 76.325 ; + POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 91.6 108.4 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 97.52 26.16 97.52 26.16 108.4 ; LAYER met2 ; - RECT 83.58 108.615 83.86 108.985 ; - RECT 54.14 108.615 54.42 108.985 ; - RECT 79.45 106.94 79.71 107.26 ; - RECT 70.25 106.94 70.51 107.26 ; - RECT 60.59 106.94 60.85 107.26 ; - RECT 51.39 106.94 51.65 107.26 ; - RECT 40.35 106.94 40.61 107.26 ; - RECT 9.98 97.735 10.26 98.105 ; - RECT 12.29 96.06 12.55 96.38 ; - RECT 9.98 10.695 10.26 11.065 ; - RECT 84.97 1.54 85.23 1.86 ; - RECT 47.25 1.54 47.51 1.86 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - POLYGON 95.4 108.52 95.4 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 5.17 97.64 5.17 96.28 5.87 96.28 5.87 97.64 6.09 97.64 6.09 96.28 6.79 96.28 6.79 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 10.69 97.64 10.69 96.28 11.39 96.28 11.39 97.64 11.61 97.64 11.61 96.28 12.31 96.28 12.31 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 17.59 97.64 17.59 96.28 18.29 96.28 18.29 97.64 27.88 97.64 27.88 108.52 35.07 108.52 35.07 107.16 35.77 107.16 35.77 108.52 36.91 108.52 36.91 107.16 37.61 107.16 37.61 108.52 37.83 108.52 37.83 107.16 38.53 107.16 38.53 108.52 38.75 108.52 38.75 107.16 39.45 107.16 39.45 108.52 39.67 108.52 39.67 107.16 40.37 107.16 40.37 108.52 40.59 108.52 40.59 107.16 41.29 107.16 41.29 108.52 41.51 108.52 41.51 107.16 42.21 107.16 42.21 108.52 42.43 108.52 42.43 107.16 43.13 107.16 43.13 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 63.13 108.52 63.13 107.16 63.83 107.16 63.83 108.52 64.05 108.52 64.05 107.16 64.75 107.16 64.75 108.52 64.97 108.52 64.97 107.16 65.67 107.16 65.67 108.52 65.89 108.52 65.89 107.16 66.59 107.16 66.59 108.52 66.81 108.52 66.81 107.16 67.51 107.16 67.51 108.52 67.73 108.52 67.73 107.16 68.43 107.16 68.43 108.52 70.49 108.52 70.49 107.16 71.19 107.16 71.19 108.52 76.93 108.52 76.93 107.16 77.63 107.16 77.63 108.52 77.85 108.52 77.85 107.16 78.55 107.16 78.55 108.52 78.77 108.52 78.77 107.16 79.47 107.16 79.47 108.52 79.69 108.52 79.69 107.16 80.39 107.16 80.39 108.52 80.61 108.52 80.61 107.16 81.31 107.16 81.31 108.52 ; + RECT 80.82 108.615 81.1 108.985 ; + RECT 51.38 108.615 51.66 108.985 ; + RECT 64.27 106.94 64.53 107.26 ; + RECT 61.51 106.94 61.77 107.26 ; + RECT 38.05 106.94 38.31 107.26 ; + RECT 10.9 97.735 11.18 98.105 ; + RECT 10.9 10.695 11.18 11.065 ; + RECT 55.99 1.54 56.25 1.86 ; + RECT 44.95 1.54 45.21 1.86 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + POLYGON 91.72 108.52 91.72 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 2.87 97.64 2.87 96.28 3.57 96.28 3.57 97.64 6.55 97.64 6.55 96.28 7.25 96.28 7.25 97.64 7.47 97.64 7.47 96.28 8.17 96.28 8.17 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 13.91 97.64 13.91 96.28 14.61 96.28 14.61 97.64 15.75 97.64 15.75 96.28 16.45 96.28 16.45 97.64 18.05 97.64 18.05 96.28 18.75 96.28 18.75 97.64 26.04 97.64 26.04 108.52 31.85 108.52 31.85 107.16 32.55 107.16 32.55 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 37.37 108.52 37.37 107.16 38.07 107.16 38.07 108.52 38.29 108.52 38.29 107.16 38.99 107.16 38.99 108.52 39.21 108.52 39.21 107.16 39.91 107.16 39.91 108.52 40.13 108.52 40.13 107.16 40.83 107.16 40.83 108.52 41.05 108.52 41.05 107.16 41.75 107.16 41.75 108.52 41.97 108.52 41.97 107.16 42.67 107.16 42.67 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.65 108.52 45.65 107.16 46.35 107.16 46.35 108.52 46.57 108.52 46.57 107.16 47.27 107.16 47.27 108.52 47.49 108.52 47.49 107.16 48.19 107.16 48.19 108.52 48.41 108.52 48.41 107.16 49.11 107.16 49.11 108.52 49.33 108.52 49.33 107.16 50.03 107.16 50.03 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.93 108.52 53.93 107.16 54.63 107.16 54.63 108.52 55.77 108.52 55.77 107.16 56.47 107.16 56.47 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 66.35 108.52 66.35 107.16 67.05 107.16 67.05 108.52 67.27 108.52 67.27 107.16 67.97 107.16 67.97 108.52 68.19 108.52 68.19 107.16 68.89 107.16 68.89 108.52 69.11 108.52 69.11 107.16 69.81 107.16 69.81 108.52 70.03 108.52 70.03 107.16 70.73 107.16 70.73 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 71.87 108.52 71.87 107.16 72.57 107.16 72.57 108.52 72.79 108.52 72.79 107.16 73.49 107.16 73.49 108.52 73.71 108.52 73.71 107.16 74.41 107.16 74.41 108.52 81.53 108.52 81.53 107.16 82.23 107.16 82.23 108.52 ; LAYER met4 ; - POLYGON 95.28 108.4 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 28 97.52 28 108.4 38.86 108.4 38.86 107.8 40.26 107.8 40.26 108.4 43.61 108.4 43.61 107.04 44.71 107.04 44.71 108.4 45.45 108.4 45.45 107.04 46.55 107.04 46.55 108.4 53.58 108.4 53.58 107.8 54.98 107.8 54.98 108.4 61.09 108.4 61.09 107.04 62.19 107.04 62.19 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 68.3 108.4 68.3 107.8 69.7 107.8 69.7 108.4 83.02 108.4 83.02 107.8 84.42 107.8 84.42 108.4 ; + POLYGON 91.6 108.4 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 59.43 0.4 59.43 1.76 58.33 1.76 58.33 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 17.85 97.52 17.85 96.16 18.95 96.16 18.95 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 52.81 108.4 52.81 107.04 53.91 107.04 53.91 108.4 59.25 108.4 59.25 107.04 60.35 107.04 60.35 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 72.13 108.4 72.13 107.04 73.23 107.04 73.23 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; LAYER met5 ; - POLYGON 94.08 107.2 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 29.2 96.32 29.2 107.2 ; + POLYGON 90.4 107.2 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; LAYER met1 ; - POLYGON 95.4 108.28 95.4 106.6 94.92 106.6 94.92 105.56 95.4 105.56 95.4 103.88 94.92 103.88 94.92 102.84 95.4 102.84 95.4 101.16 94.92 101.16 94.92 100.12 95.4 100.12 95.4 98.44 27.88 98.44 27.88 100.12 28.36 100.12 28.36 101.16 27.88 101.16 27.88 102.84 28.36 102.84 28.36 103.88 27.88 103.88 27.88 105.56 28.36 105.56 28.36 106.6 27.88 106.6 27.88 108.28 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; + POLYGON 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; LAYER li1 ; - POLYGON 95.51 108.63 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 27.77 97.75 27.77 108.63 ; + POLYGON 91.83 108.63 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; LAYER mcon ; - RECT 95.365 108.715 95.535 108.885 ; - RECT 94.905 108.715 95.075 108.885 ; - RECT 94.445 108.715 94.615 108.885 ; - RECT 93.985 108.715 94.155 108.885 ; - RECT 93.525 108.715 93.695 108.885 ; - RECT 93.065 108.715 93.235 108.885 ; - RECT 92.605 108.715 92.775 108.885 ; - RECT 92.145 108.715 92.315 108.885 ; RECT 91.685 108.715 91.855 108.885 ; RECT 91.225 108.715 91.395 108.885 ; RECT 90.765 108.715 90.935 108.885 ; @@ -1949,26 +1954,22 @@ MACRO sb_2__1_ RECT 28.665 108.715 28.835 108.885 ; RECT 28.205 108.715 28.375 108.885 ; RECT 27.745 108.715 27.915 108.885 ; - RECT 95.365 105.995 95.535 106.165 ; - RECT 94.905 105.995 95.075 106.165 ; - RECT 28.205 105.995 28.375 106.165 ; - RECT 27.745 105.995 27.915 106.165 ; - RECT 95.365 103.275 95.535 103.445 ; - RECT 94.905 103.275 95.075 103.445 ; - RECT 28.205 103.275 28.375 103.445 ; - RECT 27.745 103.275 27.915 103.445 ; - RECT 95.365 100.555 95.535 100.725 ; - RECT 94.905 100.555 95.075 100.725 ; - RECT 28.205 100.555 28.375 100.725 ; - RECT 27.745 100.555 27.915 100.725 ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; + RECT 27.285 108.715 27.455 108.885 ; + RECT 26.825 108.715 26.995 108.885 ; + RECT 26.365 108.715 26.535 108.885 ; + RECT 25.905 108.715 26.075 108.885 ; + RECT 91.685 105.995 91.855 106.165 ; + RECT 91.225 105.995 91.395 106.165 ; + RECT 26.365 105.995 26.535 106.165 ; + RECT 25.905 105.995 26.075 106.165 ; + RECT 91.685 103.275 91.855 103.445 ; + RECT 91.225 103.275 91.395 103.445 ; + RECT 26.365 103.275 26.535 103.445 ; + RECT 25.905 103.275 26.075 103.445 ; + RECT 91.685 100.555 91.855 100.725 ; + RECT 91.225 100.555 91.395 100.725 ; + RECT 26.365 100.555 26.535 100.725 ; + RECT 25.905 100.555 26.075 100.725 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -2169,138 +2170,130 @@ MACRO sb_2__1_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; RECT 91.685 10.795 91.855 10.965 ; RECT 91.225 10.795 91.395 10.965 ; RECT 90.765 10.795 90.935 10.965 ; @@ -2501,26 +2494,18 @@ MACRO sb_2__1_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; - RECT 28.205 8.075 28.375 8.245 ; - RECT 27.745 8.075 27.915 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; - RECT 28.205 5.355 28.375 5.525 ; - RECT 27.745 5.355 27.915 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; - RECT 28.205 2.635 28.375 2.805 ; - RECT 27.745 2.635 27.915 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; + RECT 26.365 8.075 26.535 8.245 ; + RECT 25.905 8.075 26.075 8.245 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; + RECT 26.365 5.355 26.535 5.525 ; + RECT 25.905 5.355 26.075 5.525 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; + RECT 26.365 2.635 26.535 2.805 ; + RECT 25.905 2.635 26.075 2.805 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -2661,44 +2646,49 @@ MACRO sb_2__1_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; LAYER via ; - RECT 83.645 108.725 83.795 108.875 ; - RECT 54.205 108.725 54.355 108.875 ; - RECT 77.205 107.025 77.355 107.175 ; - RECT 67.085 107.025 67.235 107.175 ; - RECT 44.545 107.025 44.695 107.175 ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 10.045 97.845 10.195 97.995 ; - RECT 15.105 12.505 15.255 12.655 ; - RECT 83.645 10.805 83.795 10.955 ; - RECT 54.205 10.805 54.355 10.955 ; - RECT 10.045 10.805 10.195 10.955 ; - RECT 78.125 1.625 78.275 1.775 ; - RECT 66.165 1.625 66.315 1.775 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; + RECT 80.885 108.725 81.035 108.875 ; + RECT 51.445 108.725 51.595 108.875 ; + RECT 62.945 107.025 63.095 107.175 ; + RECT 52.365 107.025 52.515 107.175 ; + RECT 37.645 107.025 37.795 107.175 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 10.965 97.845 11.115 97.995 ; + RECT 16.025 96.145 16.175 96.295 ; + RECT 9.125 12.505 9.275 12.655 ; + RECT 80.885 10.805 81.035 10.955 ; + RECT 51.445 10.805 51.595 10.955 ; + RECT 10.965 10.805 11.115 10.955 ; + RECT 49.145 1.625 49.295 1.775 ; + RECT 41.785 1.625 41.935 1.775 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; - RECT 83.62 108.7 83.82 108.9 ; - RECT 54.18 108.7 54.38 108.9 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.28 89.66 1.48 89.86 ; - RECT 1.74 84.22 1.94 84.42 ; - RECT 1.28 82.86 1.48 83.06 ; - RECT 1.28 77.42 1.48 77.62 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 108.7 81.06 108.9 ; + RECT 51.42 108.7 51.62 108.9 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 1.28 81.5 1.48 81.7 ; + RECT 1.74 76.74 1.94 76.94 ; + RECT 1.28 57.02 1.48 57.22 ; + RECT 1.28 40.02 1.48 40.22 ; + RECT 1.28 33.22 1.48 33.42 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; - RECT 83.62 108.7 83.82 108.9 ; - RECT 54.18 108.7 54.38 108.9 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.74 74.7 1.94 74.9 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 108.7 81.06 108.9 ; + RECT 51.42 108.7 51.62 108.9 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER OVERLAP ; - POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 27.6 97.92 27.6 108.8 95.68 108.8 95.68 0 ; + POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 0 ; END END sb_2__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef index be19040..1c394cc 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -356,22 +356,22 @@ END unithddbl MACRO sb_2__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 95.68 BY 97.92 ; + SIZE 92 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + LAYER met3 ; + RECT 0 35.21 1.38 35.51 ; END END prog_clk[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + LAYER met2 ; + RECT 55.59 0 55.73 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,7 +387,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; + RECT 56.89 0 57.19 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.97 0 80.11 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 84.57 0 84.71 1.36 ; + RECT 72.61 0 72.75 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; + RECT 64.79 0 64.93 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 44.09 0 44.23 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 0 68.15 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; + RECT 73.53 0 73.67 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 0 81.03 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -531,23 +531,23 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END bottom_right_grid_pin_1_[0] PIN bottom_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 11.43 10.88 11.57 12.24 ; + LAYER met4 ; + RECT 12.73 10.88 13.03 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; + LAYER met4 ; + RECT 9.05 10.88 9.35 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -555,7 +555,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.35 10.88 12.49 12.24 ; + RECT 18.33 10.88 18.47 12.24 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -563,7 +563,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 10.88 14.33 12.24 ; + RECT 7.29 10.88 7.43 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -571,7 +571,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] @@ -579,23 +579,23 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 10.88 18.01 12.24 ; + RECT 15.11 10.88 15.25 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 10.88 5.67 12.24 ; + LAYER met2 ; + RECT 8.21 10.88 8.35 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 11.81 10.88 12.11 12.24 ; + LAYER met2 ; + RECT 10.05 10.88 10.19 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -603,7 +603,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 42.69 1.38 42.99 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -611,7 +611,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -619,7 +619,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 49.49 1.38 49.79 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -683,7 +683,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -691,7 +691,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -699,7 +699,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -707,7 +707,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -715,7 +715,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 50.85 1.38 51.15 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -763,7 +763,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 61.05 1.38 61.35 ; END END left_top_grid_pin_1_[0] PIN left_bottom_grid_pin_34_[0] @@ -771,7 +771,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; + RECT 27.99 0 28.13 1.36 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] @@ -779,7 +779,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 10.88 13.41 12.24 ; + RECT 12.81 10.88 12.95 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -795,7 +795,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.91 10.88 6.05 12.24 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -803,15 +803,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 10.88 7.89 12.24 ; + RECT 6.37 10.88 6.51 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; + LAYER met4 ; + RECT 4.45 10.88 4.75 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -819,7 +819,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; + RECT 11.89 10.88 12.03 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -827,15 +827,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 10.88 6.97 12.24 ; + RECT 16.03 10.88 16.17 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 94.3 61.05 95.68 61.35 ; + LAYER met2 ; + RECT 2.23 96.56 2.37 97.92 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -843,15 +843,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 79.05 0 79.19 1.36 ; + LAYER met4 ; + RECT 58.73 0 59.03 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -859,7 +859,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -867,7 +867,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -875,7 +875,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 37.19 0 37.33 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -883,7 +883,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -891,7 +891,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -899,7 +899,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -907,7 +907,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -915,7 +915,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 38.11 0 38.25 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -923,7 +923,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -931,7 +931,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 33.97 0 34.11 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -939,7 +939,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 58.81 0 58.95 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -947,7 +947,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -955,7 +955,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -963,7 +963,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -971,7 +971,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -979,7 +979,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -987,7 +987,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 70.77 0 70.91 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -995,7 +995,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1003,7 +1003,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1019,7 +1019,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1027,7 +1027,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 52.21 1.38 52.51 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1035,7 +1035,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1043,7 +1043,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1051,7 +1051,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1059,7 +1059,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 48.13 1.38 48.43 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1067,7 +1067,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1075,7 +1075,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1083,7 +1083,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1091,7 +1091,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1099,7 +1099,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1107,7 +1107,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1115,7 +1115,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1123,7 +1123,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1131,7 +1131,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1139,7 +1139,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1147,7 +1147,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1155,7 +1155,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1163,7 +1163,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 14.81 1.38 15.11 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1171,7 +1171,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.13 1.38 14.43 ; + RECT 0 16.17 1.38 16.47 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1179,15 +1179,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; + RECT 0 78.73 1.38 79.03 ; END END SC_IN_BOT PIN SC_OUT_TOP DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 94.3 33.17 95.68 33.47 ; + LAYER met2 ; + RECT 31.21 96.56 31.35 97.92 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1195,7 +1195,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 76.01 1.38 76.31 ; END END SC_OUT_BOT PIN VDD @@ -1203,52 +1203,52 @@ MACRO sb_2__2_ USE POWER ; PORT LAYER met1 ; - RECT 27.6 2.48 28.08 2.96 ; - RECT 95.2 2.48 95.68 2.96 ; - RECT 27.6 7.92 28.08 8.4 ; - RECT 95.2 7.92 95.68 8.4 ; + RECT 25.76 2.48 26.24 2.96 ; + RECT 91.52 2.48 92 2.96 ; + RECT 25.76 7.92 26.24 8.4 ; + RECT 91.52 7.92 92 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 95.2 13.36 95.68 13.84 ; + RECT 91.52 13.36 92 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 95.2 18.8 95.68 19.28 ; + RECT 91.52 18.8 92 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 95.2 24.24 95.68 24.72 ; + RECT 91.52 24.24 92 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 95.2 29.68 95.68 30.16 ; + RECT 91.52 29.68 92 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 95.2 35.12 95.68 35.6 ; + RECT 91.52 35.12 92 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 95.2 40.56 95.68 41.04 ; + RECT 91.52 40.56 92 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 95.2 46 95.68 46.48 ; + RECT 91.52 46 92 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 95.2 51.44 95.68 51.92 ; + RECT 91.52 51.44 92 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 95.2 56.88 95.68 57.36 ; + RECT 91.52 56.88 92 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 95.2 62.32 95.68 62.8 ; + RECT 91.52 62.32 92 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 95.2 67.76 95.68 68.24 ; + RECT 91.52 67.76 92 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 95.2 73.2 95.68 73.68 ; + RECT 91.52 73.2 92 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 95.2 78.64 95.68 79.12 ; + RECT 91.52 78.64 92 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 95.2 84.08 95.68 84.56 ; + RECT 91.52 84.08 92 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 95.2 89.52 95.68 90 ; + RECT 91.52 89.52 92 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 95.2 94.96 95.68 95.44 ; + RECT 91.52 94.96 92 95.44 ; LAYER met4 ; - RECT 39.26 0 39.86 0.6 ; - RECT 68.7 0 69.3 0.6 ; - RECT 39.26 97.32 39.86 97.92 ; - RECT 68.7 97.32 69.3 97.92 ; + RECT 36.5 0 37.1 0.6 ; + RECT 65.94 0 66.54 0.6 ; + RECT 36.5 97.32 37.1 97.92 ; + RECT 65.94 97.32 66.54 97.92 ; LAYER met5 ; RECT 0 22.2 3.2 25.4 ; - RECT 92.48 22.2 95.68 25.4 ; + RECT 88.8 22.2 92 25.4 ; RECT 0 63 3.2 66.2 ; - RECT 92.48 63 95.68 66.2 ; + RECT 88.8 63 92 66.2 ; END END VDD PIN VSS @@ -1256,166 +1256,162 @@ MACRO sb_2__2_ USE GROUND ; PORT LAYER met1 ; - RECT 27.6 0 95.68 0.24 ; - RECT 27.6 5.2 28.08 5.68 ; - RECT 95.2 5.2 95.68 5.68 ; - RECT 0 10.64 95.68 11.12 ; + RECT 25.76 0 92 0.24 ; + RECT 25.76 5.2 26.24 5.68 ; + RECT 91.52 5.2 92 5.68 ; + RECT 0 10.64 92 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 95.2 16.08 95.68 16.56 ; + RECT 91.52 16.08 92 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 95.2 21.52 95.68 22 ; + RECT 91.52 21.52 92 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 95.2 26.96 95.68 27.44 ; + RECT 91.52 26.96 92 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 95.2 32.4 95.68 32.88 ; + RECT 91.52 32.4 92 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 95.2 37.84 95.68 38.32 ; + RECT 91.52 37.84 92 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 95.2 43.28 95.68 43.76 ; + RECT 91.52 43.28 92 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 95.2 48.72 95.68 49.2 ; + RECT 91.52 48.72 92 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 95.2 54.16 95.68 54.64 ; + RECT 91.52 54.16 92 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 95.2 59.6 95.68 60.08 ; + RECT 91.52 59.6 92 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 95.2 65.04 95.68 65.52 ; + RECT 91.52 65.04 92 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 95.2 70.48 95.68 70.96 ; + RECT 91.52 70.48 92 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 95.2 75.92 95.68 76.4 ; + RECT 91.52 75.92 92 76.4 ; RECT 0 81.36 0.48 81.84 ; - RECT 95.2 81.36 95.68 81.84 ; + RECT 91.52 81.36 92 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 95.2 86.8 95.68 87.28 ; + RECT 91.52 86.8 92 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 95.2 92.24 95.68 92.72 ; - RECT 0 97.68 95.68 97.92 ; + RECT 91.52 92.24 92 92.72 ; + RECT 0 97.68 92 97.92 ; LAYER met4 ; - RECT 53.98 0 54.58 0.6 ; - RECT 83.42 0 84.02 0.6 ; - RECT 9.82 10.88 10.42 11.48 ; - RECT 9.82 97.32 10.42 97.92 ; - RECT 53.98 97.32 54.58 97.92 ; - RECT 83.42 97.32 84.02 97.92 ; + RECT 51.22 0 51.82 0.6 ; + RECT 80.66 0 81.26 0.6 ; + RECT 10.74 10.88 11.34 11.48 ; + RECT 10.74 97.32 11.34 97.92 ; + RECT 51.22 97.32 51.82 97.92 ; + RECT 80.66 97.32 81.26 97.92 ; LAYER met5 ; RECT 0 42.6 3.2 45.8 ; - RECT 92.48 42.6 95.68 45.8 ; + RECT 88.8 42.6 92 45.8 ; RECT 0 83.4 3.2 86.6 ; - RECT 92.48 83.4 95.68 86.6 ; + RECT 88.8 83.4 92 86.6 ; END END VSS OBS LAYER li1 ; - RECT 0 97.835 95.68 98.005 ; - RECT 95.22 95.115 95.68 95.285 ; + RECT 0 97.835 92 98.005 ; + RECT 91.54 95.115 92 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 95.22 92.395 95.68 92.565 ; + RECT 91.54 92.395 92 92.565 ; RECT 0 92.395 3.68 92.565 ; - RECT 95.22 89.675 95.68 89.845 ; + RECT 91.54 89.675 92 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 95.22 86.955 95.68 87.125 ; + RECT 91.54 86.955 92 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 92 84.235 95.68 84.405 ; + RECT 91.54 84.235 92 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 92 81.515 95.68 81.685 ; + RECT 91.54 81.515 92 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 95.22 78.795 95.68 78.965 ; + RECT 91.54 78.795 92 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 95.22 76.075 95.68 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 95.22 73.355 95.68 73.525 ; + RECT 88.32 76.075 92 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 88.32 73.355 92 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 95.22 70.635 95.68 70.805 ; + RECT 88.32 70.635 92 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 92 67.915 95.68 68.085 ; + RECT 88.32 67.915 92 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 92 65.195 95.68 65.365 ; + RECT 91.54 65.195 92 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 95.22 62.475 95.68 62.645 ; + RECT 91.54 62.475 92 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 95.22 59.755 95.68 59.925 ; + RECT 91.08 59.755 92 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 94.76 57.035 95.68 57.205 ; + RECT 91.08 57.035 92 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 94.76 54.315 95.68 54.485 ; + RECT 90.16 54.315 92 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 94.76 51.595 95.68 51.765 ; + RECT 90.16 51.595 92 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 94.76 48.875 95.68 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 95.22 46.155 95.68 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 95.22 43.435 95.68 43.605 ; + RECT 90.16 48.875 92 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 90.16 46.155 92 46.325 ; + RECT 0 46.155 3.68 46.325 ; + RECT 91.54 43.435 92 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 95.22 40.715 95.68 40.885 ; + RECT 91.54 40.715 92 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 94.76 37.995 95.68 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 92 35.275 95.68 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 92 32.555 95.68 32.725 ; + RECT 91.08 37.995 92 38.165 ; + RECT 0 37.995 3.68 38.165 ; + RECT 91.08 35.275 92 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 91.54 32.555 92 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 95.22 29.835 95.68 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 94.76 27.115 95.68 27.285 ; + RECT 91.54 29.835 92 30.005 ; + RECT 0 29.835 1.84 30.005 ; + RECT 91.54 27.115 92 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 94.76 24.395 95.68 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 94.76 21.675 95.68 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 95.22 18.955 95.68 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 95.22 16.235 95.68 16.405 ; + RECT 91.54 24.395 92 24.565 ; + RECT 0 24.395 1.84 24.565 ; + RECT 91.08 21.675 92 21.845 ; + RECT 0 21.675 1.84 21.845 ; + RECT 91.08 18.955 92 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 91.54 16.235 92 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 94.76 13.515 95.68 13.685 ; + RECT 91.54 13.515 92 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 94.76 10.795 95.68 10.965 ; - RECT 0 10.795 31.28 10.965 ; - RECT 94.76 8.075 95.68 8.245 ; - RECT 27.6 8.075 31.28 8.245 ; - RECT 94.76 5.355 95.68 5.525 ; - RECT 27.6 5.355 31.28 5.525 ; - RECT 95.22 2.635 95.68 2.805 ; - RECT 27.6 2.635 31.28 2.805 ; - RECT 27.6 -0.085 95.68 0.085 ; - LAYER met2 ; - RECT 83.58 97.735 83.86 98.105 ; - RECT 54.14 97.735 54.42 98.105 ; - RECT 9.98 97.735 10.26 98.105 ; - RECT 9.98 10.695 10.26 11.065 ; - RECT 68.41 1.54 68.67 1.86 ; - RECT 55.53 1.54 55.79 1.86 ; - RECT 83.58 -0.185 83.86 0.185 ; - RECT 54.14 -0.185 54.42 0.185 ; - POLYGON 95.4 97.64 95.4 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 0.28 11.16 0.28 97.64 ; - LAYER met4 ; - POLYGON 95.28 97.52 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; + RECT 91.08 10.795 92 10.965 ; + RECT 0 10.795 29.44 10.965 ; + RECT 91.08 8.075 92 8.245 ; + RECT 25.76 8.075 29.44 8.245 ; + RECT 88.32 5.355 92 5.525 ; + RECT 25.76 5.355 27.6 5.525 ; + RECT 88.32 2.635 92 2.805 ; + RECT 25.76 2.635 29.44 2.805 ; + RECT 25.76 -0.085 92 0.085 ; LAYER met3 ; - POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; - POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; - POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; - POLYGON 2.03 15.12 2.03 15.11 33.73 15.11 33.73 14.81 2.03 14.81 2.03 14.8 1.65 14.8 1.65 15.12 ; - POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; - POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; - POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; - POLYGON 95.28 97.52 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 33.87 93.9 33.87 93.9 32.77 95.28 32.77 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; + POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; + POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; + POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; + POLYGON 28.67 68.83 28.67 68.53 1.23 68.53 1.23 68.81 1.78 68.81 1.78 68.83 ; + POLYGON 2.03 18.52 2.03 18.51 6.13 18.51 6.13 18.21 2.03 18.21 2.03 18.2 1.65 18.2 1.65 18.52 ; + POLYGON 24.53 17.15 24.53 16.85 1.23 16.85 1.23 17.13 1.78 17.13 1.78 17.15 ; + POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; + POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; + POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; + POLYGON 91.6 97.52 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; + LAYER met2 ; + RECT 80.82 97.735 81.1 98.105 ; + RECT 51.38 97.735 51.66 98.105 ; + RECT 10.9 97.735 11.18 98.105 ; + RECT 15.51 12.42 15.77 12.74 ; + RECT 10.9 10.695 11.18 11.065 ; + RECT 56.91 1.54 57.17 1.86 ; + RECT 51.85 1.54 52.11 1.86 ; + RECT 48.17 1.54 48.43 1.86 ; + RECT 80.82 -0.185 81.1 0.185 ; + RECT 51.38 -0.185 51.66 0.185 ; + POLYGON 91.72 97.64 91.72 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 18.75 11.16 18.75 12.52 18.05 12.52 18.05 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 30.93 97.64 30.93 96.28 31.63 96.28 31.63 97.64 ; + LAYER met4 ; + POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 59.43 0.4 59.43 1.76 58.33 1.76 58.33 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; LAYER met5 ; - POLYGON 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; + POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; - POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; + POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; LAYER li1 ; - POLYGON 95.51 97.75 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 ; + POLYGON 91.83 97.75 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; RECT 91.685 97.835 91.855 98.005 ; RECT 91.225 97.835 91.395 98.005 ; RECT 90.765 97.835 90.935 98.005 ; @@ -1616,138 +1612,130 @@ MACRO sb_2__2_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 95.365 95.115 95.535 95.285 ; - RECT 94.905 95.115 95.075 95.285 ; + RECT 91.685 95.115 91.855 95.285 ; + RECT 91.225 95.115 91.395 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 95.365 92.395 95.535 92.565 ; - RECT 94.905 92.395 95.075 92.565 ; + RECT 91.685 92.395 91.855 92.565 ; + RECT 91.225 92.395 91.395 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 95.365 89.675 95.535 89.845 ; - RECT 94.905 89.675 95.075 89.845 ; + RECT 91.685 89.675 91.855 89.845 ; + RECT 91.225 89.675 91.395 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 95.365 84.235 95.535 84.405 ; - RECT 94.905 84.235 95.075 84.405 ; + RECT 91.685 84.235 91.855 84.405 ; + RECT 91.225 84.235 91.395 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; + RECT 91.685 81.515 91.855 81.685 ; + RECT 91.225 81.515 91.395 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 95.365 78.795 95.535 78.965 ; - RECT 94.905 78.795 95.075 78.965 ; + RECT 91.685 78.795 91.855 78.965 ; + RECT 91.225 78.795 91.395 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 95.365 76.075 95.535 76.245 ; - RECT 94.905 76.075 95.075 76.245 ; + RECT 91.685 76.075 91.855 76.245 ; + RECT 91.225 76.075 91.395 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 95.365 73.355 95.535 73.525 ; - RECT 94.905 73.355 95.075 73.525 ; + RECT 91.685 73.355 91.855 73.525 ; + RECT 91.225 73.355 91.395 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 95.365 70.635 95.535 70.805 ; - RECT 94.905 70.635 95.075 70.805 ; + RECT 91.685 70.635 91.855 70.805 ; + RECT 91.225 70.635 91.395 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 95.365 67.915 95.535 68.085 ; - RECT 94.905 67.915 95.075 68.085 ; + RECT 91.685 67.915 91.855 68.085 ; + RECT 91.225 67.915 91.395 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; + RECT 91.685 65.195 91.855 65.365 ; + RECT 91.225 65.195 91.395 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 95.365 62.475 95.535 62.645 ; - RECT 94.905 62.475 95.075 62.645 ; + RECT 91.685 62.475 91.855 62.645 ; + RECT 91.225 62.475 91.395 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 95.365 59.755 95.535 59.925 ; - RECT 94.905 59.755 95.075 59.925 ; + RECT 91.685 59.755 91.855 59.925 ; + RECT 91.225 59.755 91.395 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 95.365 57.035 95.535 57.205 ; - RECT 94.905 57.035 95.075 57.205 ; + RECT 91.685 57.035 91.855 57.205 ; + RECT 91.225 57.035 91.395 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 95.365 54.315 95.535 54.485 ; - RECT 94.905 54.315 95.075 54.485 ; + RECT 91.685 54.315 91.855 54.485 ; + RECT 91.225 54.315 91.395 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 95.365 51.595 95.535 51.765 ; - RECT 94.905 51.595 95.075 51.765 ; + RECT 91.685 51.595 91.855 51.765 ; + RECT 91.225 51.595 91.395 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 95.365 48.875 95.535 49.045 ; - RECT 94.905 48.875 95.075 49.045 ; + RECT 91.685 48.875 91.855 49.045 ; + RECT 91.225 48.875 91.395 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 95.365 46.155 95.535 46.325 ; - RECT 94.905 46.155 95.075 46.325 ; + RECT 91.685 46.155 91.855 46.325 ; + RECT 91.225 46.155 91.395 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 95.365 43.435 95.535 43.605 ; - RECT 94.905 43.435 95.075 43.605 ; + RECT 91.685 43.435 91.855 43.605 ; + RECT 91.225 43.435 91.395 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 95.365 40.715 95.535 40.885 ; - RECT 94.905 40.715 95.075 40.885 ; + RECT 91.685 40.715 91.855 40.885 ; + RECT 91.225 40.715 91.395 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 95.365 37.995 95.535 38.165 ; - RECT 94.905 37.995 95.075 38.165 ; + RECT 91.685 37.995 91.855 38.165 ; + RECT 91.225 37.995 91.395 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 95.365 35.275 95.535 35.445 ; - RECT 94.905 35.275 95.075 35.445 ; + RECT 91.685 35.275 91.855 35.445 ; + RECT 91.225 35.275 91.395 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 95.365 32.555 95.535 32.725 ; - RECT 94.905 32.555 95.075 32.725 ; + RECT 91.685 32.555 91.855 32.725 ; + RECT 91.225 32.555 91.395 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 95.365 29.835 95.535 30.005 ; - RECT 94.905 29.835 95.075 30.005 ; + RECT 91.685 29.835 91.855 30.005 ; + RECT 91.225 29.835 91.395 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 95.365 27.115 95.535 27.285 ; - RECT 94.905 27.115 95.075 27.285 ; + RECT 91.685 27.115 91.855 27.285 ; + RECT 91.225 27.115 91.395 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 95.365 24.395 95.535 24.565 ; - RECT 94.905 24.395 95.075 24.565 ; + RECT 91.685 24.395 91.855 24.565 ; + RECT 91.225 24.395 91.395 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 95.365 21.675 95.535 21.845 ; - RECT 94.905 21.675 95.075 21.845 ; + RECT 91.685 21.675 91.855 21.845 ; + RECT 91.225 21.675 91.395 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 95.365 18.955 95.535 19.125 ; - RECT 94.905 18.955 95.075 19.125 ; + RECT 91.685 18.955 91.855 19.125 ; + RECT 91.225 18.955 91.395 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; + RECT 91.685 16.235 91.855 16.405 ; + RECT 91.225 16.235 91.395 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 95.365 13.515 95.535 13.685 ; - RECT 94.905 13.515 95.075 13.685 ; + RECT 91.685 13.515 91.855 13.685 ; + RECT 91.225 13.515 91.395 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; RECT 91.685 10.795 91.855 10.965 ; RECT 91.225 10.795 91.395 10.965 ; RECT 90.765 10.795 90.935 10.965 ; @@ -1948,26 +1936,18 @@ MACRO sb_2__2_ RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 95.365 8.075 95.535 8.245 ; - RECT 94.905 8.075 95.075 8.245 ; - RECT 28.205 8.075 28.375 8.245 ; - RECT 27.745 8.075 27.915 8.245 ; - RECT 95.365 5.355 95.535 5.525 ; - RECT 94.905 5.355 95.075 5.525 ; - RECT 28.205 5.355 28.375 5.525 ; - RECT 27.745 5.355 27.915 5.525 ; - RECT 95.365 2.635 95.535 2.805 ; - RECT 94.905 2.635 95.075 2.805 ; - RECT 28.205 2.635 28.375 2.805 ; - RECT 27.745 2.635 27.915 2.805 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 8.075 91.855 8.245 ; + RECT 91.225 8.075 91.395 8.245 ; + RECT 26.365 8.075 26.535 8.245 ; + RECT 25.905 8.075 26.075 8.245 ; + RECT 91.685 5.355 91.855 5.525 ; + RECT 91.225 5.355 91.395 5.525 ; + RECT 26.365 5.355 26.535 5.525 ; + RECT 25.905 5.355 26.075 5.525 ; + RECT 91.685 2.635 91.855 2.805 ; + RECT 91.225 2.635 91.395 2.805 ; + RECT 26.365 2.635 26.535 2.805 ; + RECT 25.905 2.635 26.075 2.805 ; RECT 91.685 -0.085 91.855 0.085 ; RECT 91.225 -0.085 91.395 0.085 ; RECT 90.765 -0.085 90.935 0.085 ; @@ -2108,45 +2088,48 @@ MACRO sb_2__2_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; + RECT 27.285 -0.085 27.455 0.085 ; + RECT 26.825 -0.085 26.995 0.085 ; + RECT 26.365 -0.085 26.535 0.085 ; + RECT 25.905 -0.085 26.075 0.085 ; LAYER via ; - RECT 83.645 97.845 83.795 97.995 ; - RECT 54.205 97.845 54.355 97.995 ; - RECT 10.045 97.845 10.195 97.995 ; + RECT 80.885 97.845 81.035 97.995 ; + RECT 51.445 97.845 51.595 97.995 ; + RECT 10.965 97.845 11.115 97.995 ; + RECT 31.205 96.145 31.355 96.295 ; RECT 9.125 12.505 9.275 12.655 ; - RECT 83.645 10.805 83.795 10.955 ; - RECT 54.205 10.805 54.355 10.955 ; - RECT 10.045 10.805 10.195 10.955 ; - RECT 77.205 1.625 77.355 1.775 ; - RECT 50.525 1.625 50.675 1.775 ; - RECT 83.645 -0.075 83.795 0.075 ; - RECT 54.205 -0.075 54.355 0.075 ; + RECT 80.885 10.805 81.035 10.955 ; + RECT 51.445 10.805 51.595 10.955 ; + RECT 10.965 10.805 11.115 10.955 ; + RECT 52.365 1.625 52.515 1.775 ; + RECT 49.145 1.625 49.295 1.775 ; + RECT 45.465 1.625 45.615 1.775 ; + RECT 39.945 1.625 40.095 1.775 ; + RECT 80.885 -0.075 81.035 0.075 ; + RECT 51.445 -0.075 51.595 0.075 ; LAYER via2 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.28 89.66 1.48 89.86 ; - RECT 1.74 76.74 1.94 76.94 ; - RECT 1.28 75.38 1.48 75.58 ; - RECT 1.74 59.74 1.94 59.94 ; - RECT 1.28 31.86 1.48 32.06 ; - RECT 1.28 30.5 1.48 30.7 ; - RECT 1.28 26.42 1.48 26.62 ; - RECT 1.28 22.34 1.48 22.54 ; - RECT 1.28 17.58 1.48 17.78 ; - RECT 1.28 14.18 1.48 14.38 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 1.28 78.78 1.48 78.98 ; + RECT 1.74 70.62 1.94 70.82 ; + RECT 1.28 37.3 1.48 37.5 ; + RECT 1.28 33.22 1.48 33.42 ; + RECT 1.28 16.22 1.48 16.42 ; + RECT 1.28 14.86 1.48 15.06 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER via3 ; - RECT 83.62 97.82 83.82 98.02 ; - RECT 54.18 97.82 54.38 98.02 ; - RECT 10.02 97.82 10.22 98.02 ; - RECT 1.74 57.02 1.94 57.22 ; - RECT 10.02 10.78 10.22 10.98 ; - RECT 83.62 -0.1 83.82 0.1 ; - RECT 54.18 -0.1 54.38 0.1 ; + RECT 80.86 97.82 81.06 98.02 ; + RECT 51.42 97.82 51.62 98.02 ; + RECT 10.94 97.82 11.14 98.02 ; + RECT 1.74 59.06 1.94 59.26 ; + RECT 10.94 10.78 11.14 10.98 ; + RECT 80.86 -0.1 81.06 0.1 ; + RECT 51.42 -0.1 51.62 0.1 ; LAYER OVERLAP ; - POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 95.68 97.92 95.68 0 ; + POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 92 97.92 92 0 ; END END sb_2__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef index dd9f950..6340d3d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4459f54f80efe83b578590c9748f03265d0ac8d4ed1c7788b3f5572b5b07e375 -size 779620 +oid sha256:0d1e1f9cd67109ad2a9d86647c83c4ce556135e18c2e43fb6a472830dc51cf43 +size 802012 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef index e520000..9af8da5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9cacb82c62dabd60d49e997c2ac82c72c8b6b995fedfda6fc6fbf9fc778e7a79 -size 1156324 +oid sha256:b9c08bd41f0442b3b200226fe53d7442e52e8ba4fd1e0bda981c56faae729776 +size 1196339 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef index b7528b3..b3901da 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__2__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1445be08c289b4e53412e586a891cfac0696bc56f5b12b83e17b1794a6959760 -size 1248894 +oid sha256:73658bc7a7defde062cb72cc53f0b6ff2639011f2a9a016d4a834b3074156e30 +size 1278970 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef index 434cc03..3956237 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cby_0__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4926d754b46158426444f67f0dc1ea7b2527ec042d4d65162c32582b19d608e8 -size 314390 +oid sha256:b6742a70b2adb90065766e5700d6ba25e89970911d3e46a14a07b38682bf059f +size 311080 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef index 4f25ee3..f04feb4 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cby_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:573bbd5ff376f96c50e969b9c17969154c062f66d93b075ae91736ed689acfd2 -size 1094398 +oid sha256:649a38d837e30f3c053631013b6f976c6a37eeb56582f385c1c2c58cf511085b +size 1114961 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef index c95c9ad..8e82eb1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cby_2__1__icv_in_design.nominal_25.spef +++ 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sha256:395eeacb637de0eefd6d1c0b23661a1990d0990e811928c25058b387b1e3aa4d +size 1617902 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef index 0a9c249..770d8c0 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_2__2__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:6f8becabbf5313c19ba8a44de6017cedf9b60b7498f5ae9dfc55c987a5adbeea -size 978015 +oid sha256:ec2567b1bc0a86dccd1b4fe48ebda45be6e1d13cd86d3cc74a8716d81bb1f49f +size 967817 diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v index 08b58a3..261fb17 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v @@ -4,25 +4,24 @@ // // // -module cbx_1__0__direct_interc_5 ( in , out ) ; +module cbx_1__0__direct_interc_3 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -40,11 +39,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -70,10 +67,9 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -99,7 +95,7 @@ cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__io .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_5 direct_interc_0_ ( +cbx_1__0__direct_interc_3 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( @@ -108,24 +104,23 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__direct_interc_4 ( in , out ) ; +module cbx_1__0__direct_interc_2 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -142,8 +137,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -169,11 +165,9 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -197,36 +191,34 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_4 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_2 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_3 ( in , out ) ; +module cbx_1__0__direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -240,11 +232,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_3_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) ) ; endmodule @@ -270,11 +267,9 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -298,41 +293,33 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_1 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -340,19 +327,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -362,6 +351,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -370,12 +360,11 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -399,36 +388,34 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -445,9 +432,8 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -473,11 +459,9 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -501,14 +485,13 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc_0 direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule @@ -521,29 +504,22 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -551,19 +527,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -573,6 +551,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -581,12 +560,11 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -610,139 +588,132 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -769,12 +740,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -800,10 +768,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -1113,7 +1080,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1153,35 +1120,38 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -1189,388 +1159,402 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , + .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , + .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , + .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , + .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , + .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v index 7bd822e..daa2237 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -4,25 +4,23 @@ // // // -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46,12 +44,10 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -82,11 +78,10 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -123,24 +118,22 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -163,9 +156,9 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -197,12 +190,10 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -231,33 +222,30 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -274,16 +262,19 @@ input VDD ; input VSS ; supply1 VDD ; +wire aps_rename_3_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -314,12 +305,10 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -348,38 +337,35 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -387,6 +373,7 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; input VDD ; input VSS ; @@ -395,11 +382,13 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -407,7 +396,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -419,6 +408,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; @@ -429,14 +419,12 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -465,33 +453,33 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -514,9 +502,9 @@ assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -548,12 +536,10 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -582,11 +568,10 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule @@ -599,29 +584,27 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -629,6 +612,7 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; input VDD ; input VSS ; @@ -637,11 +621,13 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -649,7 +635,7 @@ endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -661,6 +647,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; @@ -671,14 +658,12 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -707,9 +692,11 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; @@ -717,180 +704,150 @@ endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -915,13 +872,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -952,10 +905,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1285,7 +1238,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1327,37 +1280,40 @@ output SC_OUT_BOT ; input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; supply1 VDD ; supply0 VSS ; // assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -1365,446 +1321,454 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_184 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_182 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_182 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_183 ) ) ; + .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1582 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1583 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1584 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1585 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1586 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1587 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1588 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1589 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1590 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1591 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1477 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1592 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1593 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1594 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1595 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1596 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1597 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1598 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -1819,16 +1783,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -1843,822 +1807,780 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( @@ -2673,18 +2595,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( @@ -2699,16 +2615,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( @@ -2723,11 +2639,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v index 51c1902..a7d62d2 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -4,19 +4,18 @@ // // // -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( net_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -34,11 +33,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , - .X ( BUF_net_82 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , - .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -64,10 +61,9 @@ cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -99,18 +95,17 @@ cbx_1__0__direct_interc direct_interc_1_ ( endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb14_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -127,8 +122,9 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -154,11 +150,9 @@ cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -182,27 +176,25 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb11_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -216,11 +208,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_3_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , + .X ( SOC_DIR ) ) ; endmodule @@ -246,11 +243,9 @@ cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -274,32 +269,30 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb8_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -307,19 +300,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -329,6 +324,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -337,12 +333,11 @@ cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -366,27 +361,28 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb5_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule @@ -403,9 +399,8 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -431,11 +426,9 @@ cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -459,11 +452,10 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( io_outpad ) ) ; endmodule @@ -476,23 +468,22 @@ assign out[0] = in[0] ; endmodule -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb2_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -500,19 +491,21 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; + ccff_tail , p_abuf0 , p_abuf1 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -522,6 +515,7 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; +output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; @@ -530,12 +524,11 @@ cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -559,9 +552,11 @@ cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__ .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) ) ; + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +cbx_1__0__direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; @@ -569,126 +564,120 @@ endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -710,10 +699,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -739,10 +725,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -1017,7 +1002,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1057,35 +1042,38 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_204 ; -wire ropt_net_209 ; -wire ropt_net_188 ; +wire ropt_net_191 ; wire ropt_net_197 ; -wire ropt_net_189 ; -wire ropt_net_200 ; +wire ropt_net_179 ; +wire ropt_net_177 ; +wire ropt_net_190 ; +wire ropt_net_178 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , @@ -1093,388 +1081,402 @@ cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_5_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_204 ) ) ; + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , + .p_abuf0 ( ropt_net_191 ) ) ; cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_6_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_209 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( { aps_rename_10_ } ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , + .p_abuf0 ( ropt_net_197 ) ) ; cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( { aps_rename_12_ } ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , + .p_abuf0 ( ropt_net_179 ) ) ; cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_9_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_197 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , + .p_abuf0 ( ropt_net_177 ) ) ; cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_189 ) ) ; + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( { aps_rename_14_ } ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , + .p_abuf0 ( ropt_net_190 ) ) ; cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_11_ } ) , - .ccff_tail ( { ropt_net_227 } ) , - .p_abuf0 ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , - .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , - .X ( ropt_net_271 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , - .X ( BUF_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , - .X ( ropt_net_272 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( { aps_rename_15_ } ) , + .ccff_tail ( { ropt_net_212 } ) , + .p_abuf0 ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_174 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1176 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , + .X ( ropt_net_240 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , + .X ( ropt_net_241 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , + .X ( ropt_net_242 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v index 136d078..262dc60 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -5,168 +5,160 @@ // // module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -293,9 +285,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -315,9 +310,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -548,6 +544,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -571,174 +569,166 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1060,9 +1050,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1088,9 +1081,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -1178,6 +1172,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1207,8 +1203,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1250,22 +1244,30 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1274,21 +1276,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1307,377 +1301,353 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) ) ; + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v index 4491fe9..52cd0d2 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -5,240 +5,200 @@ // // module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -369,9 +329,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -395,10 +359,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -639,6 +603,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -666,247 +633,206 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1246,9 +1172,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1279,10 +1209,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1372,6 +1302,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1406,9 +1339,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1452,22 +1382,30 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1476,21 +1414,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1511,441 +1441,403 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1600 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1601 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1602 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1603 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1604 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1605 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1606 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1607 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1493 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1608 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1609 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1610 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1611 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1612 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1613 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1499 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1614 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1615 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1616 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -1960,16 +1852,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -1984,647 +1876,683 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2640,16 +2568,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( @@ -2664,11 +2592,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v index c728f3e..03a2b22 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -5,168 +5,160 @@ // // module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -274,7 +266,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -294,9 +289,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -492,6 +488,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -515,174 +513,166 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -964,7 +954,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -990,9 +983,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -1066,6 +1060,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1095,8 +1091,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1138,22 +1132,30 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1162,21 +1164,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1195,377 +1189,353 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_113 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_124 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( { ropt_net_114 } ) , - .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_131 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , + .X ( chanx_left_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_153 ) ) ; + .X ( chanx_right_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_105 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , + .X ( ropt_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , - .X ( bottom_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , - .X ( bottom_grid_pin_1_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , + .X ( chanx_right_out[10] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v index 123fa91..d0ac78c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -18,19 +18,18 @@ output [0:0] out ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -45,12 +44,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_1_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -76,10 +79,9 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -115,169 +117,161 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -607,9 +601,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cbx_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -629,9 +626,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -687,190 +685,181 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1254,6 +1243,65 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1288,61 +1336,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module cbx_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule @@ -1413,7 +1406,7 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1448,26 +1441,36 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1477,21 +1480,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1510,375 +1505,372 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) ) ; + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v index 88acf4a..9f421da 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -12,25 +12,23 @@ assign out[0] = in[0] ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48,15 +46,18 @@ input VDD ; input VSS ; supply1 VDD ; +wire aps_rename_1_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -88,11 +89,10 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -130,241 +130,201 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -710,9 +670,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -736,10 +700,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -798,271 +762,226 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1468,6 +1387,69 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1508,65 +1490,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -1641,7 +1564,8 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1678,26 +1602,36 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1707,21 +1641,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1742,451 +1668,431 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; + .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1618 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1619 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1620 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1621 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1622 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1623 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1509 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1624 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1510 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1625 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1511 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1626 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1512 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1627 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1513 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1628 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1514 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1629 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1515 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1630 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1516 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1631 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1517 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1632 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1518 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1633 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1519 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1634 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( @@ -2195,16 +2101,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -2219,227 +2125,261 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2449,329 +2389,313 @@ sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2779,21 +2703,11 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2809,16 +2723,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( @@ -2833,11 +2747,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v index 3676d3d..90762f8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -12,19 +12,18 @@ assign out[0] = in[0] ; endmodule -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_76 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -39,12 +38,16 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; +wire aps_rename_1_ ; + assign SOC_OUT = FPGA_OUT ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -70,10 +73,9 @@ cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -106,169 +108,161 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -551,7 +545,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -571,9 +568,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -622,190 +620,181 @@ endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1140,6 +1129,58 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1174,54 +1215,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -1285,7 +1278,7 @@ module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1320,26 +1313,36 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; -wire ropt_net_123 ; +wire ropt_net_112 ; +wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_0_undriven_sram_inv ; +wire [0:3] mux_top_ipin_10_undriven_sram_inv ; +wire [0:3] mux_top_ipin_11_undriven_sram_inv ; +wire [0:3] mux_top_ipin_12_undriven_sram_inv ; +wire [0:3] mux_top_ipin_13_undriven_sram_inv ; +wire [0:3] mux_top_ipin_14_undriven_sram_inv ; +wire [0:3] mux_top_ipin_15_undriven_sram_inv ; +wire [0:3] mux_top_ipin_1_undriven_sram_inv ; +wire [0:3] mux_top_ipin_2_undriven_sram_inv ; +wire [0:3] mux_top_ipin_3_undriven_sram_inv ; +wire [0:3] mux_top_ipin_4_undriven_sram_inv ; +wire [0:3] mux_top_ipin_5_undriven_sram_inv ; +wire [0:3] mux_top_ipin_6_undriven_sram_inv ; +wire [0:3] mux_top_ipin_7_undriven_sram_inv ; +wire [0:3] mux_top_ipin_8_undriven_sram_inv ; +wire [0:3] mux_top_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1349,21 +1352,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1382,375 +1377,372 @@ cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , + .out ( { ropt_net_117 } ) , + .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; + .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; + .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; + .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; + .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_131 } ) , - .p_abuf0 ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; + .io_inpad ( { aps_rename_3_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_107 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , - .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , .X ( chanx_right_out[5] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , .X ( chanx_right_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_2111 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_138 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( aps_rename_2_ ) ) ; + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , + .X ( chanx_right_out[8] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , + .X ( bottom_grid_pin_3_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , + .X ( chanx_left_out[15] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v index 08c7846..5d156f0 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -12,19 +12,18 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -48,9 +47,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -78,10 +80,9 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -117,21 +118,20 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -162,6 +162,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -191,8 +193,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -201,7 +201,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -216,11 +216,10 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; // cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( @@ -229,230 +228,222 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v index 6ee7a67..1417c44 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -12,25 +12,23 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -60,10 +58,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -95,11 +95,10 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -140,30 +139,25 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -192,6 +186,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -226,9 +223,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -237,7 +231,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower , VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -254,11 +248,10 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; supply1 VDD ; supply0 VSS ; // @@ -269,252 +262,235 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1521 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1636 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1522 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1637 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1523 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1638 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1524 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1639 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1525 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1640 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1526 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1641 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1527 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1642 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1528 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1643 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1529 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1644 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1530 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1645 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1531 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1646 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1532 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1647 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1533 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1648 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1534 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1649 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1535 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1650 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -529,18 +505,18 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -553,59 +529,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -615,13 +595,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -633,21 +619,17 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -665,29 +647,25 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -703,70 +681,68 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( @@ -781,35 +757,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -825,111 +795,109 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -945,30 +913,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( @@ -989,23 +951,23 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1021,36 +983,28 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( @@ -1071,12 +1025,14 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( @@ -1087,8 +1043,6 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( @@ -1103,34 +1057,30 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( @@ -1155,20 +1105,24 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( @@ -1183,31 +1137,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1229,21 +1183,27 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1259,35 +1219,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1295,141 +1251,129 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1445,16 +1389,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( @@ -1469,11 +1413,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v index 1000fb9..b5fb6fb 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -12,19 +12,18 @@ assign out[0] = in[0] ; endmodule -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -48,9 +47,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , + .X ( BUF_net_46 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule @@ -78,10 +80,9 @@ cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -117,21 +118,20 @@ endmodule module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -155,6 +155,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -184,8 +186,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -194,7 +194,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; + right_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -209,11 +209,10 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_166 ; +wire ropt_net_168 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; // cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( @@ -222,230 +221,222 @@ cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_155 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( { ropt_net_195 } ) , - .p_abuf0 ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , - .X ( left_grid_pin_0_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( { ropt_net_170 } ) , + .p_abuf0 ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , - .X ( BUF_net_49 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( BUF_net_53 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_55 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( + .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_165 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v index 46b8690..bbf7737 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -5,169 +5,161 @@ // // module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -191,12 +183,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -216,10 +205,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -293,12 +281,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -318,10 +303,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -497,9 +481,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -519,9 +506,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -577,171 +565,163 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1225,9 +1205,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1253,25 +1231,31 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1280,21 +1264,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1305,350 +1281,335 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v index 40e4c34..647c46c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -5,241 +5,201 @@ // // module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -261,13 +221,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -291,10 +247,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -369,13 +325,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -399,10 +351,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -585,9 +537,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -611,10 +567,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -673,243 +629,203 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1425,9 +1341,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1455,25 +1369,31 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1482,21 +1402,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1509,440 +1421,409 @@ supply1 VDD ; supply0 VSS ; // -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; + .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; + .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1537 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1652 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1538 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1653 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1539 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1654 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1540 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1655 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1541 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1656 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1542 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1657 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1543 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1658 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1544 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1659 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1545 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1660 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1546 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1661 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1547 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1662 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1548 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1663 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1549 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1664 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1550 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1665 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1551 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1666 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( @@ -1955,389 +1836,409 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2353,16 +2254,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( @@ -2377,11 +2278,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v index dcdd6e1..22cbefd 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -5,169 +5,161 @@ // // module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -186,10 +178,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -209,10 +198,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -274,10 +262,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -297,10 +282,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -450,7 +434,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -470,9 +457,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; endmodule @@ -521,171 +509,163 @@ endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , + .X ( net_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1113,9 +1093,7 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1141,25 +1119,31 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1168,21 +1152,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1193,350 +1169,335 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_126 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .ccff_tail ( { ropt_net_120 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( aps_rename_8_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , - .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , + .X ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_69 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , + .X ( ropt_net_127 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v index 8ee40cd..3fad510 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v @@ -18,19 +18,20 @@ output [0:0] out ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -45,21 +46,12 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -wire aps_rename_1_ ; - assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -85,10 +77,9 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -124,168 +115,160 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -412,12 +395,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; cby_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -437,10 +417,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -700,189 +679,180 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1428,8 +1398,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - prog_clk__FEEDTHRU_1 ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1460,26 +1429,34 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1489,21 +1466,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1520,229 +1489,212 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -1750,113 +1702,116 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v index c6f7761..35666d3 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v @@ -12,25 +12,25 @@ assign out[0] = in[0] ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48,23 +48,16 @@ input VDD ; input VSS ; supply1 VDD ; -wire aps_rename_1_ ; supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -95,11 +88,10 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; endmodule @@ -137,240 +129,200 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -501,13 +453,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -531,10 +479,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -809,270 +757,225 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1655,7 +1558,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS , prog_clk__FEEDTHRU_1 ) ; + VDD , VSS ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1688,26 +1591,34 @@ output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1717,21 +1628,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1750,263 +1653,229 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; + .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; + .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -2014,122 +1883,122 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1553 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1668 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1554 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1669 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1555 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1670 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1556 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1671 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1557 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1672 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1558 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1673 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1559 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1674 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1560 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1675 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1561 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1676 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1562 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1677 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1563 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1678 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1564 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1679 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1565 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1680 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1566 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1681 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1567 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1682 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( @@ -2138,45 +2007,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -2191,331 +2065,363 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x41400y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2531,16 +2437,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( @@ -2555,11 +2461,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v index 9c803e6..6e25fde 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v @@ -12,19 +12,20 @@ assign out[0] = in[0] ; endmodule -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -output [0:0] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_aps_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_net_80 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -39,21 +40,12 @@ input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -wire aps_rename_1_ ; - assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule @@ -79,10 +71,9 @@ cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; endmodule @@ -115,168 +106,160 @@ endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -384,10 +367,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -407,10 +387,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule @@ -635,189 +614,180 @@ endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1300,8 +1270,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - prog_clk__FEEDTHRU_1 ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1332,26 +1301,34 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; -output [0:0] prog_clk__FEEDTHRU_1 ; +wire ropt_net_114 ; +wire [0:3] mux_left_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_0_undriven_sram_inv ; +wire [0:3] mux_right_ipin_10_undriven_sram_inv ; +wire [0:3] mux_right_ipin_11_undriven_sram_inv ; +wire [0:3] mux_right_ipin_12_undriven_sram_inv ; +wire [0:3] mux_right_ipin_13_undriven_sram_inv ; +wire [0:3] mux_right_ipin_14_undriven_sram_inv ; +wire [0:3] mux_right_ipin_15_undriven_sram_inv ; +wire [0:3] mux_right_ipin_1_undriven_sram_inv ; +wire [0:3] mux_right_ipin_2_undriven_sram_inv ; +wire [0:3] mux_right_ipin_3_undriven_sram_inv ; +wire [0:3] mux_right_ipin_4_undriven_sram_inv ; +wire [0:3] mux_right_ipin_5_undriven_sram_inv ; +wire [0:3] mux_right_ipin_6_undriven_sram_inv ; +wire [0:3] mux_right_ipin_7_undriven_sram_inv ; +wire [0:3] mux_right_ipin_8_undriven_sram_inv ; +wire [0:3] mux_right_ipin_9_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; @@ -1361,21 +1338,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -1392,229 +1361,212 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; + .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; + .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , @@ -1622,113 +1574,116 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_107 } ) , - .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1103 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .io_inpad ( { aps_rename_8_ } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , + .X ( aps_rename_4_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( aps_rename_6_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , + .X ( aps_rename_9_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v index e4304d9..5df43c6 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -5,76 +5,72 @@ // // module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -200,9 +196,12 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -210,281 +209,266 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -507,13 +491,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -534,13 +518,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -561,13 +545,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -584,17 +568,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -696,13 +676,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -723,13 +703,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -750,13 +730,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -804,13 +784,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -942,38 +922,42 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:0] ccff_tail ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -990,13 +974,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -1006,342 +986,283 @@ wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v index 806c3e5..4a381c8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -5,108 +5,92 @@ // // module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -233,9 +217,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -245,394 +233,346 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -653,87 +593,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -746,6 +605,83 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -842,15 +778,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -869,33 +805,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -908,6 +817,33 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -950,15 +886,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1092,38 +1028,42 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1140,13 +1080,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -1158,449 +1094,373 @@ supply0 VSS ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; + .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1128 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1129 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1130 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1131 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1132 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1133 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1134 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1135 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1136 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1235 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1137 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1138 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1139 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1140 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1141 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1240 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1142 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1143 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1144 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1145 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1146 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1147 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1148 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1149 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1150 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1151 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1152 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1153 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1154 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1155 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1156 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1255 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1157 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1158 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1159 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1160 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1161 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1162 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1163 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -1615,16 +1475,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -1645,21 +1505,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1673,47 +1531,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1729,49 +1587,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1793,43 +1651,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1845,46 +1701,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( @@ -1905,40 +1765,42 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -1953,49 +1815,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2017,41 +1879,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2067,47 +1929,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2129,43 +1993,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2181,44 +2043,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( @@ -2239,42 +2107,42 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( @@ -2289,42 +2157,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( @@ -2345,29 +2221,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2383,36 +2267,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( @@ -2433,35 +2327,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2477,22 +2367,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( @@ -2505,33 +2413,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2541,46 +2453,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( @@ -2589,35 +2489,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2633,42 +2535,38 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( @@ -2677,41 +2575,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2725,87 +2627,79 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2817,81 +2711,73 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2901,42 +2787,34 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( @@ -2945,102 +2823,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( @@ -3051,52 +2915,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( @@ -3109,53 +2965,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3165,65 +3005,73 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3231,35 +3079,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3275,16 +3133,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( @@ -3299,11 +3157,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v index 753dbe4..f9ba787 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -5,76 +5,72 @@ // // module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -174,7 +170,10 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -182,281 +181,266 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -472,66 +456,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -542,6 +466,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -612,13 +592,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -632,26 +612,6 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -662,6 +622,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -692,13 +672,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -802,38 +782,42 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:0] ccff_tail ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; +wire [0:1] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_4_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -850,13 +834,9 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -866,342 +846,283 @@ wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_83 } ) , + .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( { ropt_net_84 } ) , + .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_101 } ) , - .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_107 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_97 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_102 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .ccff_tail ( { ropt_net_85 } ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_78 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_79 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_80 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , + .X ( ropt_net_101 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , + .X ( ropt_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_93 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v index 073bb51..3af8e7b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -5,102 +5,96 @@ // // module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -196,13 +190,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -250,98 +248,93 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -503,57 +496,54 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -701,133 +691,126 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -852,6 +835,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -863,8 +848,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -887,8 +870,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -900,6 +881,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -992,8 +975,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1005,6 +986,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1062,8 +1045,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1075,99 +1056,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1349,8 +1327,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1365,137 +1341,134 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1565,8 +1538,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1584,6 +1555,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; endmodule @@ -1651,6 +1626,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1668,10 +1645,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) ) ; endmodule @@ -1692,12 +1665,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1711,10 +1681,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1832,18 +1801,45 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -1851,33 +1847,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -1886,34 +1870,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -1922,11 +1894,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1936,539 +1905,486 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v index 6a29590..e4ffb0d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -5,144 +5,126 @@ // // module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -236,15 +218,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -290,135 +276,120 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -585,81 +556,69 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -816,189 +775,161 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1021,42 +952,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1076,6 +971,42 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:3] in ; @@ -1165,9 +1096,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1181,6 +1109,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1237,9 +1168,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1253,139 +1181,122 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1573,9 +1484,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1593,193 +1501,170 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1849,9 +1734,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1872,6 +1754,11 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1939,53 +1826,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2012,6 +1852,47 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; @@ -2132,18 +2013,45 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -2151,33 +2059,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -2186,34 +2082,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -2222,11 +2106,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2238,684 +2119,594 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1165 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1166 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1167 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1168 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1169 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1170 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1171 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1172 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1272 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1175 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1176 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1177 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1178 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1277 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1179 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1180 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1181 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1182 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1183 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1184 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1185 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1186 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1187 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1188 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1189 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1190 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1191 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1192 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1193 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1194 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1195 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1196 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1197 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1198 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1199 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1200 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1201 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1202 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( @@ -2928,16 +2719,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -2952,43 +2743,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2996,45 +2793,79 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3044,45 +2875,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3094,36 +2917,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( @@ -3132,138 +2963,126 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( @@ -3272,43 +3091,51 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3316,41 +3143,55 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3360,49 +3201,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3410,47 +3241,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3458,131 +3289,149 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3594,121 +3443,145 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3720,107 +3593,95 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3828,347 +3689,381 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4176,46 +4071,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( @@ -4224,29 +4117,25 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4254,13 +4143,13 @@ sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4270,39 +4159,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4310,48 +4199,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( @@ -4360,77 +4241,93 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4438,65 +4335,69 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4512,16 +4413,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( @@ -4536,11 +4437,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v index 541c426..0143dae 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -5,102 +5,96 @@ // // module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -170,11 +164,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -208,98 +206,93 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_aps_53 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , + .X ( net_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -426,57 +419,54 @@ endmodule module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -603,133 +593,126 @@ endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -747,34 +730,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -791,6 +746,34 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; @@ -859,8 +842,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -872,6 +853,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -915,8 +898,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -928,99 +909,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1167,8 +1145,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1183,137 +1159,134 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , + .X ( out[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1369,8 +1342,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1388,6 +1359,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , + .X ( out[0] ) ) ; endmodule @@ -1441,44 +1416,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1501,6 +1438,38 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -1601,18 +1570,45 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_33_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_10_undriven_sram_inv ; +wire [0:2] mux_right_track_12_undriven_sram_inv ; +wire [0:2] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; @@ -1620,33 +1616,21 @@ wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; @@ -1655,34 +1639,22 @@ wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -1691,11 +1663,8 @@ wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1705,539 +1674,486 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( { ropt_net_137 } ) , - .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_167 } ) , + .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_155 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( { ropt_net_136 } ) , - .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_151 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .ccff_tail ( { ropt_net_179 } ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_151 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( - .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , + .X ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( + .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , + .X ( chany_bottom_out[17] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v index 88ad7ae..25dc3c8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -5,310 +5,290 @@ // // module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -435,13 +415,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -489,13 +473,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -512,17 +496,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -566,17 +546,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -705,13 +681,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -797,34 +773,32 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -893,38 +867,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1009,38 +981,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1161,42 +1131,48 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1215,21 +1191,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // @@ -1241,374 +1211,333 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v index 7c720fc..6e9bee1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -5,436 +5,380 @@ // // module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -559,15 +503,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -613,15 +561,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -636,19 +584,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -690,19 +634,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -829,15 +769,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -923,48 +863,42 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1035,54 +969,46 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1171,54 +1097,46 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1345,42 +1263,48 @@ output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1399,21 +1323,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; @@ -1427,522 +1345,458 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1204 ( .VNB ( VSS ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1205 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1206 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1305 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1207 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1306 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1208 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1307 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1209 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1308 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1210 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1309 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1211 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1310 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1212 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1311 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1213 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1312 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1214 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1313 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1215 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1216 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1217 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1316 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1218 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1235 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1335 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1338 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( @@ -1951,53 +1805,59 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2005,230 +1865,224 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( @@ -2237,203 +2091,221 @@ sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2445,97 +2317,97 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2545,33 +2417,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2587,9 +2467,13 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2597,33 +2481,21 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2635,45 +2507,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2683,50 +2551,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( @@ -2739,42 +2601,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( @@ -2787,37 +2657,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2833,42 +2705,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( @@ -2883,46 +2757,38 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( @@ -2937,43 +2803,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2995,14 +2863,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y680000 ( @@ -3013,18 +2891,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( @@ -3039,45 +2915,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3099,46 +2971,42 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( @@ -3153,52 +3021,50 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( @@ -3219,41 +3085,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3269,50 +3135,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( @@ -3333,44 +3195,42 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( @@ -3385,49 +3245,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3449,43 +3309,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3501,49 +3359,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3559,16 +3417,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( @@ -3589,21 +3447,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v index 5cae38b..b147b8a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -5,310 +5,290 @@ // // module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , - .X ( net_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -402,11 +382,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -440,13 +424,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -458,15 +442,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -498,15 +478,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -600,13 +576,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -671,34 +647,32 @@ endmodule module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -753,38 +727,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -855,38 +827,36 @@ endmodule module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -993,42 +963,48 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_5_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:1] mux_right_track_10_undriven_sram_inv ; +wire [0:1] mux_right_track_12_undriven_sram_inv ; +wire [0:1] mux_right_track_14_undriven_sram_inv ; +wire [0:1] mux_right_track_16_undriven_sram_inv ; +wire [0:1] mux_right_track_18_undriven_sram_inv ; +wire [0:1] mux_right_track_20_undriven_sram_inv ; +wire [0:1] mux_right_track_22_undriven_sram_inv ; +wire [0:1] mux_right_track_24_undriven_sram_inv ; +wire [0:1] mux_right_track_26_undriven_sram_inv ; +wire [0:1] mux_right_track_28_undriven_sram_inv ; +wire [0:2] mux_right_track_2_undriven_sram_inv ; +wire [0:1] mux_right_track_30_undriven_sram_inv ; +wire [0:1] mux_right_track_32_undriven_sram_inv ; +wire [0:1] mux_right_track_34_undriven_sram_inv ; +wire [0:1] mux_right_track_36_undriven_sram_inv ; +wire [0:1] mux_right_track_38_undriven_sram_inv ; +wire [0:2] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_6_undriven_sram_inv ; +wire [0:1] mux_right_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1047,21 +1023,15 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // @@ -1073,374 +1043,333 @@ sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_6_undriven_sram_inv ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_10_undriven_sram_inv ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_12_undriven_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_14_undriven_sram_inv ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( { ropt_net_125 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_18_undriven_sram_inv ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_20_undriven_sram_inv ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; + .sram_inv ( mux_right_track_22_undriven_sram_inv ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; + .sram_inv ( mux_right_track_26_undriven_sram_inv ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_28_undriven_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_30_undriven_sram_inv ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_111 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_34_undriven_sram_inv ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_36_undriven_sram_inv ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_right_track_38_undriven_sram_inv ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_121 } ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( aps_rename_10_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , - .X ( BUF_net_48 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , + .X ( BUF_net_59 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , + .X ( ropt_net_139 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v index abeca44..adff765 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -5,41 +5,41 @@ // // module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -123,39 +123,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -247,43 +245,41 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -377,6 +373,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -409,24 +407,21 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -459,120 +454,113 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -795,39 +783,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -903,172 +889,163 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1232,12 +1209,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1254,10 +1228,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1497,64 +1470,61 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1723,11 +1693,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1763,38 +1729,48 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -1803,40 +1779,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1847,19 +1808,14 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( @@ -1868,271 +1824,249 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -2140,9 +2074,8 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -2150,257 +2083,220 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v index 362f3bd..feaa59e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -5,57 +5,51 @@ // // module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -143,55 +137,47 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -287,61 +273,51 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -438,6 +414,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -476,32 +455,26 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -534,169 +507,148 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -926,55 +878,47 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1052,244 +996,208 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1460,13 +1368,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1487,10 +1391,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1745,91 +1649,76 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2007,11 +1896,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2049,38 +1934,48 @@ input VDD ; input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -2089,40 +1984,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2133,11 +2013,8 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; @@ -2146,8 +2023,6 @@ supply0 VSS ; // assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( @@ -2156,315 +2031,271 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_133 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_133 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_132 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_135 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -2472,9 +2303,9 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -2482,342 +2313,301 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_136 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_134 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1340 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1341 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1342 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1343 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1344 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1345 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1346 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1347 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1348 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1349 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1350 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1353 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1255 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1263 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1365 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1368 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1369 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1370 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1272 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1371 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1372 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1373 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1374 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1375 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1376 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1377 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -2832,16 +2622,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -2862,37 +2652,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2914,65 +2700,57 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2984,64 +2762,60 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( @@ -3062,32 +2836,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( @@ -3108,13 +2882,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3126,73 +2896,69 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3210,32 +2976,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( @@ -3256,13 +3022,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3278,65 +3040,57 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3358,1255 +3112,1251 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1081000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1081000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1062600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1081000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1030400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1058000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1090200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1062600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1058000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1071800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1081000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4622,37 +4372,29 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4666,95 +4408,99 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v index aa0a8f0..ec9c14b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -5,41 +5,41 @@ // // module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , - .X ( net_net_88 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , + .X ( net_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -109,39 +109,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -219,43 +217,41 @@ endmodule module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -335,6 +331,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -367,24 +365,21 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -410,120 +405,113 @@ endmodule module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -697,39 +685,37 @@ endmodule module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -791,172 +777,163 @@ endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1094,10 +1071,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1114,10 +1088,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1322,64 +1295,61 @@ endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1527,11 +1497,7 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1567,38 +1533,48 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; output [0:0] prog_clk__FEEDTHRU_1 ; output [0:0] prog_clk__FEEDTHRU_2 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:2] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:1] mux_top_track_38_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:2] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -1607,40 +1583,25 @@ wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1651,19 +1612,14 @@ wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( @@ -1672,271 +1628,249 @@ sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; + .sram_inv ( mux_top_track_38_undriven_sram_inv ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , @@ -1944,9 +1878,8 @@ sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( { ropt_net_142 } ) , - .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , @@ -1954,257 +1887,220 @@ sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_135 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_136 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_3139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .ccff_tail ( { ropt_net_147 } ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_124 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[19] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v index 90de602..0d7b2b7 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -5,80 +5,74 @@ // // module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -243,9 +237,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -262,259 +259,248 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1229,92 +1215,88 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1338,7 +1320,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -1394,12 +1375,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; endmodule @@ -1481,8 +1459,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) ) ; endmodule @@ -1600,6 +1580,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1647,174 +1629,164 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1914,8 +1886,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1951,6 +1921,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -2373,7 +2345,8 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -2422,33 +2395,51 @@ output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -2462,21 +2453,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -2486,30 +2469,24 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -2517,7 +2494,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , @@ -2526,8 +2503,8 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -2535,8 +2512,8 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2544,8 +2521,8 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -2553,8 +2530,8 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -2562,8 +2539,8 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -2571,8 +2548,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -2580,54 +2558,46 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -2637,9 +2607,8 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -2649,8 +2618,8 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -2660,9 +2629,8 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -2672,39 +2640,34 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , @@ -2712,468 +2675,448 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v index 5f16111..02e5af4 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -5,112 +5,94 @@ // // module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -282,9 +264,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -305,368 +291,308 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1429,132 +1355,108 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1576,7 +1478,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -1640,13 +1541,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1734,9 +1632,11 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1859,6 +1759,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1914,247 +1817,204 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2257,9 +2117,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2301,6 +2158,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -2754,6 +2614,7 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -2804,33 +2665,51 @@ input VSS ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -2844,21 +2723,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -2868,25 +2739,17 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2894,6 +2757,8 @@ supply1 VDD ; supply0 VSS ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -2901,7 +2766,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( @@ -2911,9 +2776,9 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -2921,9 +2786,9 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2931,9 +2796,9 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -2941,9 +2806,9 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -2951,9 +2816,9 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -2961,9 +2826,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -2971,63 +2836,47 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -3037,9 +2886,9 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -3049,9 +2898,9 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -3061,9 +2910,9 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -3073,43 +2922,35 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( @@ -3118,188 +2959,166 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( @@ -3307,469 +3126,464 @@ sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1379 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1382 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1390 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1393 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1394 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1395 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1396 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1397 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1398 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1399 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1402 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1302 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1305 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1306 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1307 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1308 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1309 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1310 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1311 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1312 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1313 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1419 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( @@ -3784,1508 +3598,1494 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1104000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x984400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1136200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x915400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1076400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x975200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x993600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1113200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1122400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1140800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( @@ -5300,20 +5100,18 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( @@ -5326,89 +5124,99 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v index 609f326..bfc1ff6 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -5,80 +5,74 @@ // // module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , - .X ( net_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -217,7 +211,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -234,259 +231,248 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1117,92 +1103,88 @@ endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:4] mem_out ; -output [0:4] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1221,7 +1203,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; @@ -1275,12 +1256,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; endmodule @@ -1355,8 +1333,10 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , + .X ( out[0] ) ) ; endmodule @@ -1460,6 +1440,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1507,174 +1489,164 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1760,8 +1732,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1797,6 +1767,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -2177,7 +2149,8 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; @@ -2226,33 +2199,51 @@ output [0:0] ccff_tail ; output [0:0] prog_clk__FEEDTHRU_1 ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:3] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:3] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:4] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:3] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:3] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:4] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:3] mux_right_track_16_undriven_sram_inv ; +wire [0:3] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:4] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:3] mux_top_track_16_undriven_sram_inv ; +wire [0:3] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:4] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; @@ -2266,21 +2257,13 @@ wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram_inv ; wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; @@ -2290,30 +2273,24 @@ wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_0_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram_inv ; wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , @@ -2321,7 +2298,7 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , @@ -2330,8 +2307,8 @@ sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , @@ -2339,8 +2316,8 @@ sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , @@ -2348,8 +2325,8 @@ sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , @@ -2357,8 +2334,8 @@ sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , @@ -2366,8 +2343,8 @@ sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , @@ -2375,8 +2352,9 @@ sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( { ropt_net_158 } ) , + .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , @@ -2384,54 +2362,46 @@ sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -2441,9 +2411,8 @@ sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( { ropt_net_151 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , @@ -2453,8 +2422,8 @@ sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , @@ -2464,9 +2433,8 @@ sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( { ropt_net_148 } ) , - .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , @@ -2476,39 +2444,34 @@ sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( { ropt_net_152 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , @@ -2516,468 +2479,448 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_172 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .ccff_tail ( { ropt_net_155 } ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , - .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1151 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_187 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , .X ( chany_top_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v index 6a42f1f..fd41205 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -5,22 +5,21 @@ // // module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -69,18 +68,17 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -102,114 +100,108 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_1__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -232,6 +224,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -240,8 +234,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -321,20 +313,16 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -352,20 +340,16 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_1__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -401,58 +385,55 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -476,8 +457,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -489,6 +468,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -546,8 +527,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -559,24 +538,25 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -621,153 +601,145 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -931,6 +903,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; @@ -952,7 +925,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1068,12 +1044,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1090,10 +1063,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1145,43 +1117,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1289,43 +1259,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1481,64 +1449,61 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1709,22 +1674,21 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1803,9 +1767,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , + clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -1845,33 +1809,55 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -1879,35 +1865,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1917,23 +1890,20 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -1942,55 +1912,51 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -2000,8 +1966,8 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -2010,467 +1976,456 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v index 2f359de..e5c31b3 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -5,30 +5,26 @@ // // module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -79,25 +75,22 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -117,158 +110,140 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -289,6 +264,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -299,9 +277,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -381,23 +356,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -413,23 +384,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -466,82 +433,70 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -563,9 +518,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -579,6 +531,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -635,9 +590,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -651,32 +603,31 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -723,217 +674,185 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1104,6 +1023,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; @@ -1129,8 +1049,11 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -1250,13 +1173,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1277,10 +1196,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1335,61 +1254,51 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1503,61 +1412,51 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1725,91 +1624,76 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1992,31 +1876,26 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2099,9 +1978,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , Test_en__FEEDTHRU_0 , + Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , + clk__FEEDTHRU_1 , clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -2143,33 +2022,55 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -2177,35 +2078,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2215,17 +2103,12 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; @@ -2234,6 +2117,8 @@ supply0 VSS ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -2242,63 +2127,55 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -2308,9 +2185,9 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -2319,705 +2196,655 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_139 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1429 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1433 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1335 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1338 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1339 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1340 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1341 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1342 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1447 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1343 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1344 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1345 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1346 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1347 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1348 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1349 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1350 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3033,1430 +2860,1346 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1048800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1039600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1048800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1076400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1117800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1039600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1090200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1099400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1094800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1136200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1154600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1163800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1209800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1081000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x78200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( @@ -4469,64 +4212,60 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( @@ -4541,67 +4280,63 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4623,32 +4358,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( @@ -4669,13 +4404,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4691,42 +4422,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y924800 ( @@ -4741,13 +4470,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4763,16 +4490,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( @@ -4793,37 +4520,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v index 36e4727..804da25 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -5,22 +5,21 @@ // // module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , - .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , + .X ( net_net_120 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -62,18 +61,17 @@ endmodule module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -88,114 +86,108 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -211,6 +203,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -219,8 +213,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -281,18 +273,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -305,18 +293,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -345,58 +329,55 @@ endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -413,8 +394,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -426,6 +405,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -469,8 +450,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -482,24 +461,25 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -537,153 +517,145 @@ endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -821,6 +793,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -840,7 +813,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -937,10 +913,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -957,10 +930,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1005,43 +977,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1135,43 +1105,41 @@ endmodule module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1313,64 +1281,61 @@ endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1520,22 +1485,21 @@ endmodule module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1607,9 +1571,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; + SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , + clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -1649,33 +1613,55 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +wire [0:2] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:2] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_17_undriven_sram_inv ; +wire [0:3] mux_left_track_1_undriven_sram_inv ; +wire [0:2] mux_left_track_25_undriven_sram_inv ; +wire [0:2] mux_left_track_33_undriven_sram_inv ; +wire [0:3] mux_left_track_3_undriven_sram_inv ; +wire [0:3] mux_left_track_5_undriven_sram_inv ; +wire [0:3] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_right_track_0_undriven_sram_inv ; +wire [0:2] mux_right_track_16_undriven_sram_inv ; +wire [0:2] mux_right_track_24_undriven_sram_inv ; +wire [0:3] mux_right_track_2_undriven_sram_inv ; +wire [0:2] mux_right_track_32_undriven_sram_inv ; +wire [0:3] mux_right_track_4_undriven_sram_inv ; +wire [0:3] mux_right_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; @@ -1683,35 +1669,22 @@ wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1721,23 +1694,20 @@ wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , @@ -1746,55 +1716,51 @@ sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_0_undriven_sram_inv ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_2_undriven_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , @@ -1804,8 +1770,8 @@ sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_right_track_4_undriven_sram_inv ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , @@ -1814,467 +1780,456 @@ sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_8_undriven_sram_inv ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_16_undriven_sram_inv ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_24_undriven_sram_inv ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( { ropt_net_145 } ) , - .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_right_track_32_undriven_sram_inv ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_153 } ) , - .p0 ( optlc_net_142 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_147 } ) , - .p0 ( optlc_net_143 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_165 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .ccff_tail ( { ropt_net_164 } ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , + .X ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , + .X ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_178 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v index fa5e8ab..1123cf1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -5,76 +5,72 @@ // // module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -204,6 +200,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -215,348 +213,328 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -575,17 +553,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -602,13 +576,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -629,13 +607,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -656,13 +634,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -679,17 +657,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -710,13 +684,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -733,17 +707,13 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -787,13 +757,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -810,13 +780,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -837,13 +811,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -864,13 +838,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1091,34 +1065,32 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1187,38 +1159,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1303,38 +1273,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1457,46 +1425,56 @@ output [0:19] chany_top_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1517,33 +1495,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // @@ -1553,445 +1521,380 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v index ec8914c..5b4d894 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -5,108 +5,92 @@ // // module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -237,6 +221,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -250,489 +237,428 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -749,73 +675,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -842,7 +714,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -863,12 +762,35 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -884,15 +806,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -907,19 +829,15 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -961,15 +879,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -984,15 +902,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1011,15 +933,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1038,15 +960,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1267,48 +1189,42 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1379,54 +1295,46 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1515,54 +1423,46 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1691,46 +1591,56 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1751,33 +1661,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; @@ -1789,567 +1689,485 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_112 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_113 ) ) ; + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; + .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1461 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1466 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1365 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1368 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1369 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1370 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1477 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1371 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1372 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1373 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1374 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1375 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1376 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1377 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1484 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1378 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1379 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1382 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1493 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -2364,16 +2182,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( @@ -2394,21 +2212,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2430,43 +2246,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2482,53 +2296,53 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2546,47 +2360,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2598,66 +2410,76 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( @@ -2678,9 +2500,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2688,365 +2508,367 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3056,41 +2878,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3100,78 +2928,94 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( @@ -3180,587 +3024,603 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3776,147 +3636,167 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v index 507d5cd..7f406ab 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -5,76 +5,72 @@ // // module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -176,6 +172,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -187,348 +185,328 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , + .X ( net_net_64 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -542,55 +520,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -610,7 +548,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -625,11 +583,27 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -640,13 +614,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -658,15 +632,11 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -696,13 +666,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -714,11 +684,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -732,13 +706,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -752,13 +726,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -923,34 +897,32 @@ endmodule module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1005,38 +977,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1107,38 +1077,36 @@ endmodule module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1247,46 +1215,56 @@ output [0:19] chany_top_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; +wire [0:2] mux_top_track_0_undriven_sram_inv ; +wire [0:1] mux_top_track_10_undriven_sram_inv ; +wire [0:1] mux_top_track_12_undriven_sram_inv ; +wire [0:1] mux_top_track_14_undriven_sram_inv ; +wire [0:1] mux_top_track_16_undriven_sram_inv ; +wire [0:1] mux_top_track_18_undriven_sram_inv ; +wire [0:1] mux_top_track_20_undriven_sram_inv ; +wire [0:1] mux_top_track_22_undriven_sram_inv ; +wire [0:1] mux_top_track_24_undriven_sram_inv ; +wire [0:1] mux_top_track_26_undriven_sram_inv ; +wire [0:2] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_4_undriven_sram_inv ; +wire [0:2] mux_top_track_6_undriven_sram_inv ; +wire [0:1] mux_top_track_8_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1307,33 +1285,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // @@ -1343,445 +1311,380 @@ sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_6_undriven_sram_inv ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_10_undriven_sram_inv ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_top_track_12_undriven_sram_inv ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_14_undriven_sram_inv ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; + .sram_inv ( mux_top_track_18_undriven_sram_inv ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_20_undriven_sram_inv ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_22_undriven_sram_inv ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_top_track_26_undriven_sram_inv ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( { ropt_net_123 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( { ropt_net_124 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_121 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( { ropt_net_119 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( { ropt_net_120 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_114 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .ccff_tail ( { ropt_net_130 } ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_128 } ) , - .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_113 ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , - .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[19] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v index 0417782..d9e0f8e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -5,106 +5,98 @@ // // module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -181,13 +173,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -262,96 +254,91 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -507,82 +494,78 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -642,8 +625,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -655,6 +636,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) ) ; endmodule @@ -712,6 +697,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -723,27 +710,24 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -773,8 +757,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sb_2__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -801,61 +783,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -968,6 +949,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -985,139 +968,130 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1145,6 +1119,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1165,8 +1141,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1192,6 +1166,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1212,8 +1188,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1286,6 +1260,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1306,8 +1282,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1376,9 +1350,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_2__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1395,9 +1372,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -1449,42 +1427,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1641,63 +1617,60 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1726,6 +1699,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_2__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1749,8 +1724,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1857,42 +1830,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1923,6 +1894,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1952,8 +1925,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -2029,7 +2000,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2067,86 +2039,92 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2155,87 +2133,78 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -2244,8 +2213,8 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -2254,513 +2223,468 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) ) ; + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) ) ; + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) ) ; + .X ( ropt_net_144 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v index 0744bc4..8dda202 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -5,148 +5,128 @@ // // module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -221,15 +201,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -302,133 +282,118 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -588,115 +553,99 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -755,9 +704,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -771,6 +717,11 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -827,6 +778,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -840,37 +794,29 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -898,9 +844,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -932,85 +875,76 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1125,6 +1059,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1145,196 +1082,165 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1360,6 +1266,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1384,9 +1293,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1410,6 +1316,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1434,9 +1343,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1510,6 +1416,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1534,9 +1443,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1606,9 +1512,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1629,10 +1539,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1687,60 +1597,50 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1909,90 +1809,75 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2019,6 +1904,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2046,9 +1934,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -2161,60 +2046,50 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2243,6 +2118,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -2277,9 +2155,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -2360,7 +2235,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 ) ; + Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2400,86 +2275,92 @@ input VDD ; input VSS ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -2488,97 +2369,85 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -2587,9 +2456,9 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -2598,726 +2467,668 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1393 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1502 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1394 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1395 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1396 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1397 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1398 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1399 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1509 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1510 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1402 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1511 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1512 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1513 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1514 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1515 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1516 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1517 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1518 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1519 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1520 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1521 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1522 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1523 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1524 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1525 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1526 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1527 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1419 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1528 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1529 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1530 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1531 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1532 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1533 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1534 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1535 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1536 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1537 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1538 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1539 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1540 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1541 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3333,453 +3144,481 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3787,745 +3626,833 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4541,25 +4468,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4567,99 +4488,113 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v index 67887b2..0dfd962 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -5,106 +5,98 @@ // // module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , - .X ( net_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , + .X ( net_net_79 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -160,13 +152,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -220,96 +212,91 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -430,82 +417,78 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -551,8 +534,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -564,6 +545,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , + .X ( out[0] ) ) ; endmodule @@ -607,6 +592,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -618,27 +605,24 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -661,8 +645,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -689,61 +671,60 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -835,6 +816,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -852,139 +835,130 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1005,6 +979,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1025,8 +1001,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1045,6 +1019,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1065,8 +1041,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1125,6 +1099,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1145,8 +1121,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1203,7 +1177,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1220,9 +1197,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; endmodule @@ -1267,42 +1245,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1445,63 +1421,60 @@ endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1523,6 +1496,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1546,8 +1521,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1640,42 +1613,40 @@ endmodule module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -output [0:3] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1699,6 +1670,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1728,8 +1701,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1798,7 +1769,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1836,86 +1808,92 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input [0:0] Test_en__FEEDTHRU_0 ; output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +wire [0:2] mux_bottom_track_17_undriven_sram_inv ; +wire [0:3] mux_bottom_track_1_undriven_sram_inv ; +wire [0:2] mux_bottom_track_25_undriven_sram_inv ; +wire [0:2] mux_bottom_track_33_undriven_sram_inv ; +wire [0:3] mux_bottom_track_3_undriven_sram_inv ; +wire [0:3] mux_bottom_track_5_undriven_sram_inv ; +wire [0:3] mux_bottom_track_9_undriven_sram_inv ; +wire [0:2] mux_left_track_11_undriven_sram_inv ; +wire [0:2] mux_left_track_13_undriven_sram_inv ; +wire [0:2] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:2] mux_left_track_9_undriven_sram_inv ; +wire [0:3] mux_top_track_0_undriven_sram_inv ; +wire [0:2] mux_top_track_16_undriven_sram_inv ; +wire [0:2] mux_top_track_24_undriven_sram_inv ; +wire [0:3] mux_top_track_2_undriven_sram_inv ; +wire [0:2] mux_top_track_32_undriven_sram_inv ; +wire [0:3] mux_top_track_4_undriven_sram_inv ; +wire [0:3] mux_top_track_8_undriven_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram_inv ; wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram_inv ; wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; @@ -1924,87 +1902,78 @@ wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; + sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_0_undriven_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_top_track_2_undriven_sram_inv ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_top_track_8_undriven_sram_inv ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , @@ -2013,8 +1982,8 @@ sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_4_undriven_sram_inv ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , @@ -2023,513 +1992,468 @@ sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_top_track_16_undriven_sram_inv ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_24_undriven_sram_inv ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_161 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( { ropt_net_164 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_171 } ) , - .p0 ( optlc_net_160 ) ) ; + .sram_inv ( mux_top_track_32_undriven_sram_inv ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; + .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( { ropt_net_132 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( { ropt_net_170 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_158 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_125 ) ) ; sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_180 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_158 ) ) ; + .ccff_tail ( { ropt_net_134 } ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_127 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_150 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , - .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_148 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_159 ) ) ; + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_142 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_194 ) ) ; + .X ( ropt_net_144 ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( + .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[3] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v index 6ac85c9..4766e13 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -5,51 +5,48 @@ // // module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -149,408 +146,386 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1082,13 +1057,17 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -1186,87 +1165,87 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1327,12 +1306,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1343,10 +1319,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1366,12 +1341,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1382,10 +1354,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1409,6 +1380,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_2__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1423,84 +1396,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1652,9 +1617,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_2__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1668,9 +1636,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule @@ -1715,54 +1684,65 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1787,34 +1767,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -1828,442 +1797,406 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v index 2184480..c5e6c55 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -5,72 +5,63 @@ // // module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -173,576 +164,506 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1272,15 +1193,19 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1376,121 +1301,109 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1551,13 +1464,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1571,10 +1480,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1592,13 +1501,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1612,10 +1517,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1637,6 +1542,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1654,117 +1562,96 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; + mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; + ccff_tail , mem_out , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; input VDD ; input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1920,9 +1807,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1939,10 +1830,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1989,54 +1880,65 @@ output SC_OUT_BOT ; input VDD ; input VSS ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -2061,34 +1963,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -2104,7 +1995,7 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( @@ -2112,73 +2003,65 @@ sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( @@ -2186,586 +2069,544 @@ sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; + .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; + .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1543 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1544 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1545 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1433 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1546 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1547 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1548 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1549 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1550 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1551 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1552 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1553 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1554 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1555 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1556 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1557 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1558 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1559 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1447 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1560 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1561 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1562 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1563 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1564 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1565 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1566 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1567 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1568 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1569 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1570 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1571 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1572 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1460 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1573 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1461 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1574 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1575 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1576 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1577 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1578 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1579 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1580 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2773,22 +2614,36 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( @@ -2803,985 +2658,1017 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x59800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x96600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3789,59 +3676,59 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3851,43 +3738,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3901,39 +3778,43 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3949,36 +3830,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( @@ -3987,59 +3872,53 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4055,49 +3934,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4119,43 +3998,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4171,49 +4048,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4229,16 +4106,16 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( @@ -4259,21 +4136,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v index d20f294..17a48d8 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -5,51 +5,48 @@ // // module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -128,408 +125,386 @@ endmodule module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , + .X ( net_net_51 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -output [0:1] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -923,11 +898,15 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -999,85 +978,85 @@ output [0:0] out ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1126,10 +1105,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1140,10 +1116,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1158,10 +1133,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1172,10 +1144,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1192,6 +1163,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1206,84 +1179,76 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , - .X ( out[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; + mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; + ccff_tail , mem_out ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -output [0:2] mem_outb ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -1409,7 +1374,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1423,9 +1391,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule @@ -1470,54 +1439,65 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +wire [0:1] mux_bottom_track_11_undriven_sram_inv ; +wire [0:1] mux_bottom_track_13_undriven_sram_inv ; +wire [0:1] mux_bottom_track_15_undriven_sram_inv ; +wire [0:1] mux_bottom_track_17_undriven_sram_inv ; +wire [0:1] mux_bottom_track_19_undriven_sram_inv ; +wire [0:2] mux_bottom_track_1_undriven_sram_inv ; +wire [0:1] mux_bottom_track_21_undriven_sram_inv ; +wire [0:1] mux_bottom_track_23_undriven_sram_inv ; +wire [0:1] mux_bottom_track_25_undriven_sram_inv ; +wire [0:1] mux_bottom_track_27_undriven_sram_inv ; +wire [0:1] mux_bottom_track_29_undriven_sram_inv ; +wire [0:2] mux_bottom_track_3_undriven_sram_inv ; +wire [0:2] mux_bottom_track_5_undriven_sram_inv ; +wire [0:2] mux_bottom_track_7_undriven_sram_inv ; +wire [0:1] mux_bottom_track_9_undriven_sram_inv ; +wire [0:1] mux_left_track_11_undriven_sram_inv ; +wire [0:1] mux_left_track_13_undriven_sram_inv ; +wire [0:1] mux_left_track_15_undriven_sram_inv ; +wire [0:1] mux_left_track_17_undriven_sram_inv ; +wire [0:1] mux_left_track_19_undriven_sram_inv ; +wire [0:2] mux_left_track_1_undriven_sram_inv ; +wire [0:1] mux_left_track_21_undriven_sram_inv ; +wire [0:1] mux_left_track_23_undriven_sram_inv ; +wire [0:1] mux_left_track_25_undriven_sram_inv ; +wire [0:1] mux_left_track_27_undriven_sram_inv ; +wire [0:1] mux_left_track_29_undriven_sram_inv ; +wire [0:1] mux_left_track_31_undriven_sram_inv ; +wire [0:1] mux_left_track_33_undriven_sram_inv ; +wire [0:1] mux_left_track_35_undriven_sram_inv ; +wire [0:1] mux_left_track_37_undriven_sram_inv ; +wire [0:1] mux_left_track_39_undriven_sram_inv ; +wire [0:2] mux_left_track_3_undriven_sram_inv ; +wire [0:2] mux_left_track_5_undriven_sram_inv ; +wire [0:2] mux_left_track_7_undriven_sram_inv ; +wire [0:1] mux_left_track_9_undriven_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram_inv ; wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram_inv ; wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; @@ -1542,34 +1522,23 @@ wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_0_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram_inv ; wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram_inv ; wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_0_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram_inv ; wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; @@ -1583,442 +1552,406 @@ sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_1_undriven_sram_inv ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_5_undriven_sram_inv ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( { ropt_net_87 } ) , - .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , + .sram_inv ( mux_left_track_3_undriven_sram_inv ) , .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , + .sram_inv ( mux_left_track_7_undriven_sram_inv ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , + .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , + .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; + .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , + .sram_inv ( mux_left_track_11_undriven_sram_inv ) , .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; + .sram_inv ( mux_left_track_13_undriven_sram_inv ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_15_undriven_sram_inv ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_17_undriven_sram_inv ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_19_undriven_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .sram_inv ( mux_left_track_21_undriven_sram_inv ) , .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_23_undriven_sram_inv ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .sram_inv ( mux_left_track_27_undriven_sram_inv ) , .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .sram_inv ( mux_left_track_29_undriven_sram_inv ) , .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_31_undriven_sram_inv ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_33_undriven_sram_inv ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_35_undriven_sram_inv ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; + .sram_inv ( mux_left_track_37_undriven_sram_inv ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_left_track_39_undriven_sram_inv ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_92 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , - .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; + .ccff_tail ( { ropt_net_91 } ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; + .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , + .sram_inv ( mux_left_track_9_undriven_sram_inv ) , .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , + .sram_inv ( mux_left_track_25_undriven_sram_inv ) , .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_92 ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_50 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , - .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_99 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , .X ( ropt_net_94 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , + .X ( ropt_net_95 ) ) ; endmodule